1 /* 2 * QEMU MOS6522 VIA emulation 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2018 Mark Cave-Ayland 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/input/adb.h" 29 #include "hw/irq.h" 30 #include "hw/misc/mos6522.h" 31 #include "hw/qdev-properties.h" 32 #include "migration/vmstate.h" 33 #include "qemu/timer.h" 34 #include "qemu/cutils.h" 35 #include "qemu/log.h" 36 #include "qemu/module.h" 37 #include "trace.h" 38 39 /* XXX: implement all timer modes */ 40 41 static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti, 42 int64_t current_time); 43 static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti, 44 int64_t current_time); 45 46 static void mos6522_update_irq(MOS6522State *s) 47 { 48 if (s->ifr & s->ier) { 49 qemu_irq_raise(s->irq); 50 } else { 51 qemu_irq_lower(s->irq); 52 } 53 } 54 55 static void mos6522_set_irq(void *opaque, int n, int level) 56 { 57 MOS6522State *s = MOS6522(opaque); 58 59 if (level) { 60 s->ifr |= 1 << n; 61 } else { 62 s->ifr &= ~(1 << n); 63 } 64 65 mos6522_update_irq(s); 66 } 67 68 static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti) 69 { 70 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 71 72 if (ti->index == 0) { 73 return mdc->get_timer1_counter_value(s, ti); 74 } else { 75 return mdc->get_timer2_counter_value(s, ti); 76 } 77 } 78 79 static uint64_t get_load_time(MOS6522State *s, MOS6522Timer *ti) 80 { 81 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 82 83 if (ti->index == 0) { 84 return mdc->get_timer1_load_time(s, ti); 85 } else { 86 return mdc->get_timer2_load_time(s, ti); 87 } 88 } 89 90 static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti) 91 { 92 int64_t d; 93 unsigned int counter; 94 95 d = get_counter_value(s, ti); 96 97 if (ti->index == 0) { 98 /* the timer goes down from latch to -1 (period of latch + 2) */ 99 if (d <= (ti->counter_value + 1)) { 100 counter = (ti->counter_value - d) & 0xffff; 101 } else { 102 counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); 103 counter = (ti->latch - counter) & 0xffff; 104 } 105 } else { 106 counter = (ti->counter_value - d) & 0xffff; 107 } 108 return counter; 109 } 110 111 static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val) 112 { 113 trace_mos6522_set_counter(1 + ti->index, val); 114 ti->load_time = get_load_time(s, ti); 115 ti->counter_value = val; 116 if (ti->index == 0) { 117 mos6522_timer1_update(s, ti, ti->load_time); 118 } else { 119 mos6522_timer2_update(s, ti, ti->load_time); 120 } 121 } 122 123 static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti, 124 int64_t current_time) 125 { 126 int64_t d, next_time; 127 unsigned int counter; 128 129 if (ti->frequency == 0) { 130 return INT64_MAX; 131 } 132 133 /* current counter value */ 134 d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, 135 ti->frequency, NANOSECONDS_PER_SECOND); 136 137 /* the timer goes down from latch to -1 (period of latch + 2) */ 138 if (d <= (ti->counter_value + 1)) { 139 counter = (ti->counter_value - d) & 0xffff; 140 } else { 141 counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); 142 counter = (ti->latch - counter) & 0xffff; 143 } 144 145 /* Note: we consider the irq is raised on 0 */ 146 if (counter == 0xffff) { 147 next_time = d + ti->latch + 1; 148 } else if (counter == 0) { 149 next_time = d + ti->latch + 2; 150 } else { 151 next_time = d + counter; 152 } 153 trace_mos6522_get_next_irq_time(ti->latch, d, next_time - d); 154 next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequency) + 155 ti->load_time; 156 157 if (next_time <= current_time) { 158 next_time = current_time + 1; 159 } 160 return next_time; 161 } 162 163 static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti, 164 int64_t current_time) 165 { 166 if (!ti->timer) { 167 return; 168 } 169 ti->next_irq_time = get_next_irq_time(s, ti, current_time); 170 if ((s->ier & T1_INT) == 0 || (s->acr & T1MODE) != T1MODE_CONT) { 171 timer_del(ti->timer); 172 } else { 173 timer_mod(ti->timer, ti->next_irq_time); 174 } 175 } 176 177 static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti, 178 int64_t current_time) 179 { 180 if (!ti->timer) { 181 return; 182 } 183 ti->next_irq_time = get_next_irq_time(s, ti, current_time); 184 if ((s->ier & T2_INT) == 0) { 185 timer_del(ti->timer); 186 } else { 187 timer_mod(ti->timer, ti->next_irq_time); 188 } 189 } 190 191 static void mos6522_timer1(void *opaque) 192 { 193 MOS6522State *s = opaque; 194 MOS6522Timer *ti = &s->timers[0]; 195 196 mos6522_timer1_update(s, ti, ti->next_irq_time); 197 s->ifr |= T1_INT; 198 mos6522_update_irq(s); 199 } 200 201 static void mos6522_timer2(void *opaque) 202 { 203 MOS6522State *s = opaque; 204 MOS6522Timer *ti = &s->timers[1]; 205 206 mos6522_timer2_update(s, ti, ti->next_irq_time); 207 s->ifr |= T2_INT; 208 mos6522_update_irq(s); 209 } 210 211 static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *ti) 212 { 213 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, 214 ti->frequency, NANOSECONDS_PER_SECOND); 215 } 216 217 static uint64_t mos6522_get_load_time(MOS6522State *s, MOS6522Timer *ti) 218 { 219 uint64_t load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 220 221 return load_time; 222 } 223 224 static void mos6522_portA_write(MOS6522State *s) 225 { 226 qemu_log_mask(LOG_UNIMP, "portA_write unimplemented\n"); 227 } 228 229 static void mos6522_portB_write(MOS6522State *s) 230 { 231 qemu_log_mask(LOG_UNIMP, "portB_write unimplemented\n"); 232 } 233 234 uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) 235 { 236 MOS6522State *s = opaque; 237 uint32_t val; 238 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 239 240 if (now >= s->timers[0].next_irq_time) { 241 mos6522_timer1_update(s, &s->timers[0], now); 242 s->ifr |= T1_INT; 243 } 244 if (now >= s->timers[1].next_irq_time) { 245 mos6522_timer2_update(s, &s->timers[1], now); 246 s->ifr |= T2_INT; 247 } 248 switch (addr) { 249 case VIA_REG_B: 250 val = s->b; 251 break; 252 case VIA_REG_A: 253 qemu_log_mask(LOG_UNIMP, "Read access to register A with handshake"); 254 /* fall through */ 255 case VIA_REG_ANH: 256 val = s->a; 257 break; 258 case VIA_REG_DIRB: 259 val = s->dirb; 260 break; 261 case VIA_REG_DIRA: 262 val = s->dira; 263 break; 264 case VIA_REG_T1CL: 265 val = get_counter(s, &s->timers[0]) & 0xff; 266 s->ifr &= ~T1_INT; 267 mos6522_update_irq(s); 268 break; 269 case VIA_REG_T1CH: 270 val = get_counter(s, &s->timers[0]) >> 8; 271 mos6522_update_irq(s); 272 break; 273 case VIA_REG_T1LL: 274 val = s->timers[0].latch & 0xff; 275 break; 276 case VIA_REG_T1LH: 277 /* XXX: check this */ 278 val = (s->timers[0].latch >> 8) & 0xff; 279 break; 280 case VIA_REG_T2CL: 281 val = get_counter(s, &s->timers[1]) & 0xff; 282 s->ifr &= ~T2_INT; 283 mos6522_update_irq(s); 284 break; 285 case VIA_REG_T2CH: 286 val = get_counter(s, &s->timers[1]) >> 8; 287 break; 288 case VIA_REG_SR: 289 val = s->sr; 290 s->ifr &= ~SR_INT; 291 mos6522_update_irq(s); 292 break; 293 case VIA_REG_ACR: 294 val = s->acr; 295 break; 296 case VIA_REG_PCR: 297 val = s->pcr; 298 break; 299 case VIA_REG_IFR: 300 val = s->ifr; 301 if (s->ifr & s->ier) { 302 val |= 0x80; 303 } 304 break; 305 case VIA_REG_IER: 306 val = s->ier | 0x80; 307 break; 308 default: 309 g_assert_not_reached(); 310 } 311 312 if (addr != VIA_REG_IFR || val != 0) { 313 trace_mos6522_read(addr, val); 314 } 315 316 return val; 317 } 318 319 void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) 320 { 321 MOS6522State *s = opaque; 322 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 323 324 trace_mos6522_write(addr, val); 325 326 switch (addr) { 327 case VIA_REG_B: 328 s->b = (s->b & ~s->dirb) | (val & s->dirb); 329 mdc->portB_write(s); 330 break; 331 case VIA_REG_A: 332 qemu_log_mask(LOG_UNIMP, "Write access to register A with handshake"); 333 /* fall through */ 334 case VIA_REG_ANH: 335 s->a = (s->a & ~s->dira) | (val & s->dira); 336 mdc->portA_write(s); 337 break; 338 case VIA_REG_DIRB: 339 s->dirb = val; 340 break; 341 case VIA_REG_DIRA: 342 s->dira = val; 343 break; 344 case VIA_REG_T1CL: 345 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; 346 mos6522_timer1_update(s, &s->timers[0], 347 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 348 break; 349 case VIA_REG_T1CH: 350 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); 351 s->ifr &= ~T1_INT; 352 set_counter(s, &s->timers[0], s->timers[0].latch); 353 break; 354 case VIA_REG_T1LL: 355 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; 356 mos6522_timer1_update(s, &s->timers[0], 357 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 358 break; 359 case VIA_REG_T1LH: 360 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); 361 s->ifr &= ~T1_INT; 362 mos6522_timer1_update(s, &s->timers[0], 363 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 364 break; 365 case VIA_REG_T2CL: 366 s->timers[1].latch = (s->timers[1].latch & 0xff00) | val; 367 break; 368 case VIA_REG_T2CH: 369 /* To ensure T2 generates an interrupt on zero crossing with the 370 common timer code, write the value directly from the latch to 371 the counter */ 372 s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8); 373 s->ifr &= ~T2_INT; 374 set_counter(s, &s->timers[1], s->timers[1].latch); 375 break; 376 case VIA_REG_SR: 377 s->sr = val; 378 break; 379 case VIA_REG_ACR: 380 s->acr = val; 381 mos6522_timer1_update(s, &s->timers[0], 382 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 383 break; 384 case VIA_REG_PCR: 385 s->pcr = val; 386 break; 387 case VIA_REG_IFR: 388 /* reset bits */ 389 s->ifr &= ~val; 390 mos6522_update_irq(s); 391 break; 392 case VIA_REG_IER: 393 if (val & IER_SET) { 394 /* set bits */ 395 s->ier |= val & 0x7f; 396 } else { 397 /* reset bits */ 398 s->ier &= ~val; 399 } 400 mos6522_update_irq(s); 401 /* if IER is modified starts needed timers */ 402 mos6522_timer1_update(s, &s->timers[0], 403 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 404 mos6522_timer2_update(s, &s->timers[1], 405 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 406 break; 407 default: 408 g_assert_not_reached(); 409 } 410 } 411 412 static const MemoryRegionOps mos6522_ops = { 413 .read = mos6522_read, 414 .write = mos6522_write, 415 .endianness = DEVICE_NATIVE_ENDIAN, 416 .valid = { 417 .min_access_size = 1, 418 .max_access_size = 1, 419 }, 420 }; 421 422 static const VMStateDescription vmstate_mos6522_timer = { 423 .name = "mos6522_timer", 424 .version_id = 0, 425 .minimum_version_id = 0, 426 .fields = (VMStateField[]) { 427 VMSTATE_UINT16(latch, MOS6522Timer), 428 VMSTATE_UINT16(counter_value, MOS6522Timer), 429 VMSTATE_INT64(load_time, MOS6522Timer), 430 VMSTATE_INT64(next_irq_time, MOS6522Timer), 431 VMSTATE_TIMER_PTR(timer, MOS6522Timer), 432 VMSTATE_END_OF_LIST() 433 } 434 }; 435 436 const VMStateDescription vmstate_mos6522 = { 437 .name = "mos6522", 438 .version_id = 0, 439 .minimum_version_id = 0, 440 .fields = (VMStateField[]) { 441 VMSTATE_UINT8(a, MOS6522State), 442 VMSTATE_UINT8(b, MOS6522State), 443 VMSTATE_UINT8(dira, MOS6522State), 444 VMSTATE_UINT8(dirb, MOS6522State), 445 VMSTATE_UINT8(sr, MOS6522State), 446 VMSTATE_UINT8(acr, MOS6522State), 447 VMSTATE_UINT8(pcr, MOS6522State), 448 VMSTATE_UINT8(ifr, MOS6522State), 449 VMSTATE_UINT8(ier, MOS6522State), 450 VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 0, 451 vmstate_mos6522_timer, MOS6522Timer), 452 VMSTATE_END_OF_LIST() 453 } 454 }; 455 456 static void mos6522_reset(DeviceState *dev) 457 { 458 MOS6522State *s = MOS6522(dev); 459 460 s->b = 0; 461 s->a = 0; 462 s->dirb = 0xff; 463 s->dira = 0; 464 s->sr = 0; 465 s->acr = 0; 466 s->pcr = 0; 467 s->ifr = 0; 468 s->ier = 0; 469 /* s->ier = T1_INT | SR_INT; */ 470 471 s->timers[0].frequency = s->frequency; 472 s->timers[0].latch = 0xffff; 473 set_counter(s, &s->timers[0], 0xffff); 474 timer_del(s->timers[0].timer); 475 476 s->timers[1].frequency = s->frequency; 477 s->timers[1].latch = 0xffff; 478 timer_del(s->timers[1].timer); 479 } 480 481 static void mos6522_init(Object *obj) 482 { 483 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 484 MOS6522State *s = MOS6522(obj); 485 int i; 486 487 memory_region_init_io(&s->mem, obj, &mos6522_ops, s, "mos6522", 0x10); 488 sysbus_init_mmio(sbd, &s->mem); 489 sysbus_init_irq(sbd, &s->irq); 490 491 for (i = 0; i < ARRAY_SIZE(s->timers); i++) { 492 s->timers[i].index = i; 493 } 494 495 s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1, s); 496 s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2, s); 497 498 qdev_init_gpio_in(DEVICE(obj), mos6522_set_irq, VIA_NUM_INTS); 499 } 500 501 static void mos6522_finalize(Object *obj) 502 { 503 MOS6522State *s = MOS6522(obj); 504 505 timer_free(s->timers[0].timer); 506 timer_free(s->timers[1].timer); 507 } 508 509 static Property mos6522_properties[] = { 510 DEFINE_PROP_UINT64("frequency", MOS6522State, frequency, 0), 511 DEFINE_PROP_END_OF_LIST() 512 }; 513 514 static void mos6522_class_init(ObjectClass *oc, void *data) 515 { 516 DeviceClass *dc = DEVICE_CLASS(oc); 517 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); 518 519 dc->reset = mos6522_reset; 520 dc->vmsd = &vmstate_mos6522; 521 device_class_set_props(dc, mos6522_properties); 522 mdc->parent_reset = dc->reset; 523 mdc->portB_write = mos6522_portB_write; 524 mdc->portA_write = mos6522_portA_write; 525 mdc->get_timer1_counter_value = mos6522_get_counter_value; 526 mdc->get_timer2_counter_value = mos6522_get_counter_value; 527 mdc->get_timer1_load_time = mos6522_get_load_time; 528 mdc->get_timer2_load_time = mos6522_get_load_time; 529 } 530 531 static const TypeInfo mos6522_type_info = { 532 .name = TYPE_MOS6522, 533 .parent = TYPE_SYS_BUS_DEVICE, 534 .instance_size = sizeof(MOS6522State), 535 .instance_init = mos6522_init, 536 .instance_finalize = mos6522_finalize, 537 .abstract = true, 538 .class_size = sizeof(MOS6522DeviceClass), 539 .class_init = mos6522_class_init, 540 }; 541 542 static void mos6522_register_types(void) 543 { 544 type_register_static(&mos6522_type_info); 545 } 546 547 type_init(mos6522_register_types) 548