1 /* 2 * QEMU MOS6522 VIA emulation 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2018 Mark Cave-Ayland 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/input/adb.h" 29 #include "hw/irq.h" 30 #include "hw/misc/mos6522.h" 31 #include "hw/qdev-properties.h" 32 #include "migration/vmstate.h" 33 #include "qemu/timer.h" 34 #include "qemu/cutils.h" 35 #include "qemu/log.h" 36 #include "qemu/module.h" 37 #include "trace.h" 38 39 40 static const char *mos6522_reg_names[MOS6522_NUM_REGS] = { 41 "ORB", "ORA", "DDRB", "DDRA", "T1CL", "T1CH", "T1LL", "T1LH", 42 "T2CL", "T2CH", "SR", "ACR", "PCR", "IFR", "IER", "ANH" 43 }; 44 45 /* XXX: implement all timer modes */ 46 47 static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti, 48 int64_t current_time); 49 static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti, 50 int64_t current_time); 51 52 static void mos6522_update_irq(MOS6522State *s) 53 { 54 if (s->ifr & s->ier) { 55 qemu_irq_raise(s->irq); 56 } else { 57 qemu_irq_lower(s->irq); 58 } 59 } 60 61 static void mos6522_set_irq(void *opaque, int n, int level) 62 { 63 MOS6522State *s = MOS6522(opaque); 64 65 if (level) { 66 s->ifr |= 1 << n; 67 } else { 68 s->ifr &= ~(1 << n); 69 } 70 71 mos6522_update_irq(s); 72 } 73 74 static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti) 75 { 76 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 77 78 if (ti->index == 0) { 79 return mdc->get_timer1_counter_value(s, ti); 80 } else { 81 return mdc->get_timer2_counter_value(s, ti); 82 } 83 } 84 85 static uint64_t get_load_time(MOS6522State *s, MOS6522Timer *ti) 86 { 87 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 88 89 if (ti->index == 0) { 90 return mdc->get_timer1_load_time(s, ti); 91 } else { 92 return mdc->get_timer2_load_time(s, ti); 93 } 94 } 95 96 static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti) 97 { 98 int64_t d; 99 unsigned int counter; 100 101 d = get_counter_value(s, ti); 102 103 if (ti->index == 0) { 104 /* the timer goes down from latch to -1 (period of latch + 2) */ 105 if (d <= (ti->counter_value + 1)) { 106 counter = (ti->counter_value - d) & 0xffff; 107 } else { 108 counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); 109 counter = (ti->latch - counter) & 0xffff; 110 } 111 } else { 112 counter = (ti->counter_value - d) & 0xffff; 113 } 114 return counter; 115 } 116 117 static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val) 118 { 119 trace_mos6522_set_counter(1 + ti->index, val); 120 ti->load_time = get_load_time(s, ti); 121 ti->counter_value = val; 122 if (ti->index == 0) { 123 mos6522_timer1_update(s, ti, ti->load_time); 124 } else { 125 mos6522_timer2_update(s, ti, ti->load_time); 126 } 127 } 128 129 static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti, 130 int64_t current_time) 131 { 132 int64_t d, next_time; 133 unsigned int counter; 134 135 if (ti->frequency == 0) { 136 return INT64_MAX; 137 } 138 139 /* current counter value */ 140 d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, 141 ti->frequency, NANOSECONDS_PER_SECOND); 142 143 /* the timer goes down from latch to -1 (period of latch + 2) */ 144 if (d <= (ti->counter_value + 1)) { 145 counter = (ti->counter_value - d) & 0xffff; 146 } else { 147 counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); 148 counter = (ti->latch - counter) & 0xffff; 149 } 150 151 /* Note: we consider the irq is raised on 0 */ 152 if (counter == 0xffff) { 153 next_time = d + ti->latch + 1; 154 } else if (counter == 0) { 155 next_time = d + ti->latch + 2; 156 } else { 157 next_time = d + counter; 158 } 159 trace_mos6522_get_next_irq_time(ti->latch, d, next_time - d); 160 next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequency) + 161 ti->load_time; 162 163 if (next_time <= current_time) { 164 next_time = current_time + 1; 165 } 166 return next_time; 167 } 168 169 static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti, 170 int64_t current_time) 171 { 172 if (!ti->timer) { 173 return; 174 } 175 ti->next_irq_time = get_next_irq_time(s, ti, current_time); 176 if ((s->ier & T1_INT) == 0 || (s->acr & T1MODE) != T1MODE_CONT) { 177 timer_del(ti->timer); 178 } else { 179 timer_mod(ti->timer, ti->next_irq_time); 180 } 181 } 182 183 static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti, 184 int64_t current_time) 185 { 186 if (!ti->timer) { 187 return; 188 } 189 ti->next_irq_time = get_next_irq_time(s, ti, current_time); 190 if ((s->ier & T2_INT) == 0) { 191 timer_del(ti->timer); 192 } else { 193 timer_mod(ti->timer, ti->next_irq_time); 194 } 195 } 196 197 static void mos6522_timer1(void *opaque) 198 { 199 MOS6522State *s = opaque; 200 MOS6522Timer *ti = &s->timers[0]; 201 202 mos6522_timer1_update(s, ti, ti->next_irq_time); 203 s->ifr |= T1_INT; 204 mos6522_update_irq(s); 205 } 206 207 static void mos6522_timer2(void *opaque) 208 { 209 MOS6522State *s = opaque; 210 MOS6522Timer *ti = &s->timers[1]; 211 212 mos6522_timer2_update(s, ti, ti->next_irq_time); 213 s->ifr |= T2_INT; 214 mos6522_update_irq(s); 215 } 216 217 static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *ti) 218 { 219 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, 220 ti->frequency, NANOSECONDS_PER_SECOND); 221 } 222 223 static uint64_t mos6522_get_load_time(MOS6522State *s, MOS6522Timer *ti) 224 { 225 uint64_t load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 226 227 return load_time; 228 } 229 230 static void mos6522_portA_write(MOS6522State *s) 231 { 232 qemu_log_mask(LOG_UNIMP, "portA_write unimplemented\n"); 233 } 234 235 static void mos6522_portB_write(MOS6522State *s) 236 { 237 qemu_log_mask(LOG_UNIMP, "portB_write unimplemented\n"); 238 } 239 240 uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) 241 { 242 MOS6522State *s = opaque; 243 uint32_t val; 244 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 245 246 if (now >= s->timers[0].next_irq_time) { 247 mos6522_timer1_update(s, &s->timers[0], now); 248 s->ifr |= T1_INT; 249 } 250 if (now >= s->timers[1].next_irq_time) { 251 mos6522_timer2_update(s, &s->timers[1], now); 252 s->ifr |= T2_INT; 253 } 254 switch (addr) { 255 case VIA_REG_B: 256 val = s->b; 257 break; 258 case VIA_REG_A: 259 qemu_log_mask(LOG_UNIMP, "Read access to register A with handshake"); 260 /* fall through */ 261 case VIA_REG_ANH: 262 val = s->a; 263 break; 264 case VIA_REG_DIRB: 265 val = s->dirb; 266 break; 267 case VIA_REG_DIRA: 268 val = s->dira; 269 break; 270 case VIA_REG_T1CL: 271 val = get_counter(s, &s->timers[0]) & 0xff; 272 s->ifr &= ~T1_INT; 273 mos6522_update_irq(s); 274 break; 275 case VIA_REG_T1CH: 276 val = get_counter(s, &s->timers[0]) >> 8; 277 mos6522_update_irq(s); 278 break; 279 case VIA_REG_T1LL: 280 val = s->timers[0].latch & 0xff; 281 break; 282 case VIA_REG_T1LH: 283 /* XXX: check this */ 284 val = (s->timers[0].latch >> 8) & 0xff; 285 break; 286 case VIA_REG_T2CL: 287 val = get_counter(s, &s->timers[1]) & 0xff; 288 s->ifr &= ~T2_INT; 289 mos6522_update_irq(s); 290 break; 291 case VIA_REG_T2CH: 292 val = get_counter(s, &s->timers[1]) >> 8; 293 break; 294 case VIA_REG_SR: 295 val = s->sr; 296 s->ifr &= ~SR_INT; 297 mos6522_update_irq(s); 298 break; 299 case VIA_REG_ACR: 300 val = s->acr; 301 break; 302 case VIA_REG_PCR: 303 val = s->pcr; 304 break; 305 case VIA_REG_IFR: 306 val = s->ifr; 307 if (s->ifr & s->ier) { 308 val |= 0x80; 309 } 310 break; 311 case VIA_REG_IER: 312 val = s->ier | 0x80; 313 break; 314 default: 315 g_assert_not_reached(); 316 } 317 318 if (addr != VIA_REG_IFR || val != 0) { 319 trace_mos6522_read(addr, mos6522_reg_names[addr], val); 320 } 321 322 return val; 323 } 324 325 void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) 326 { 327 MOS6522State *s = opaque; 328 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 329 330 trace_mos6522_write(addr, mos6522_reg_names[addr], val); 331 332 switch (addr) { 333 case VIA_REG_B: 334 s->b = (s->b & ~s->dirb) | (val & s->dirb); 335 mdc->portB_write(s); 336 break; 337 case VIA_REG_A: 338 qemu_log_mask(LOG_UNIMP, "Write access to register A with handshake"); 339 /* fall through */ 340 case VIA_REG_ANH: 341 s->a = (s->a & ~s->dira) | (val & s->dira); 342 mdc->portA_write(s); 343 break; 344 case VIA_REG_DIRB: 345 s->dirb = val; 346 break; 347 case VIA_REG_DIRA: 348 s->dira = val; 349 break; 350 case VIA_REG_T1CL: 351 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; 352 mos6522_timer1_update(s, &s->timers[0], 353 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 354 break; 355 case VIA_REG_T1CH: 356 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); 357 s->ifr &= ~T1_INT; 358 set_counter(s, &s->timers[0], s->timers[0].latch); 359 break; 360 case VIA_REG_T1LL: 361 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; 362 mos6522_timer1_update(s, &s->timers[0], 363 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 364 break; 365 case VIA_REG_T1LH: 366 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); 367 s->ifr &= ~T1_INT; 368 mos6522_timer1_update(s, &s->timers[0], 369 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 370 break; 371 case VIA_REG_T2CL: 372 s->timers[1].latch = (s->timers[1].latch & 0xff00) | val; 373 break; 374 case VIA_REG_T2CH: 375 /* To ensure T2 generates an interrupt on zero crossing with the 376 common timer code, write the value directly from the latch to 377 the counter */ 378 s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8); 379 s->ifr &= ~T2_INT; 380 set_counter(s, &s->timers[1], s->timers[1].latch); 381 break; 382 case VIA_REG_SR: 383 s->sr = val; 384 break; 385 case VIA_REG_ACR: 386 s->acr = val; 387 mos6522_timer1_update(s, &s->timers[0], 388 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 389 break; 390 case VIA_REG_PCR: 391 s->pcr = val; 392 break; 393 case VIA_REG_IFR: 394 /* reset bits */ 395 s->ifr &= ~val; 396 mos6522_update_irq(s); 397 break; 398 case VIA_REG_IER: 399 if (val & IER_SET) { 400 /* set bits */ 401 s->ier |= val & 0x7f; 402 } else { 403 /* reset bits */ 404 s->ier &= ~val; 405 } 406 mos6522_update_irq(s); 407 /* if IER is modified starts needed timers */ 408 mos6522_timer1_update(s, &s->timers[0], 409 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 410 mos6522_timer2_update(s, &s->timers[1], 411 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 412 break; 413 default: 414 g_assert_not_reached(); 415 } 416 } 417 418 static const MemoryRegionOps mos6522_ops = { 419 .read = mos6522_read, 420 .write = mos6522_write, 421 .endianness = DEVICE_NATIVE_ENDIAN, 422 .valid = { 423 .min_access_size = 1, 424 .max_access_size = 1, 425 }, 426 }; 427 428 static const VMStateDescription vmstate_mos6522_timer = { 429 .name = "mos6522_timer", 430 .version_id = 0, 431 .minimum_version_id = 0, 432 .fields = (VMStateField[]) { 433 VMSTATE_UINT16(latch, MOS6522Timer), 434 VMSTATE_UINT16(counter_value, MOS6522Timer), 435 VMSTATE_INT64(load_time, MOS6522Timer), 436 VMSTATE_INT64(next_irq_time, MOS6522Timer), 437 VMSTATE_TIMER_PTR(timer, MOS6522Timer), 438 VMSTATE_END_OF_LIST() 439 } 440 }; 441 442 const VMStateDescription vmstate_mos6522 = { 443 .name = "mos6522", 444 .version_id = 0, 445 .minimum_version_id = 0, 446 .fields = (VMStateField[]) { 447 VMSTATE_UINT8(a, MOS6522State), 448 VMSTATE_UINT8(b, MOS6522State), 449 VMSTATE_UINT8(dira, MOS6522State), 450 VMSTATE_UINT8(dirb, MOS6522State), 451 VMSTATE_UINT8(sr, MOS6522State), 452 VMSTATE_UINT8(acr, MOS6522State), 453 VMSTATE_UINT8(pcr, MOS6522State), 454 VMSTATE_UINT8(ifr, MOS6522State), 455 VMSTATE_UINT8(ier, MOS6522State), 456 VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 0, 457 vmstate_mos6522_timer, MOS6522Timer), 458 VMSTATE_END_OF_LIST() 459 } 460 }; 461 462 static void mos6522_reset(DeviceState *dev) 463 { 464 MOS6522State *s = MOS6522(dev); 465 466 s->b = 0; 467 s->a = 0; 468 s->dirb = 0xff; 469 s->dira = 0; 470 s->sr = 0; 471 s->acr = 0; 472 s->pcr = 0; 473 s->ifr = 0; 474 s->ier = 0; 475 /* s->ier = T1_INT | SR_INT; */ 476 477 s->timers[0].frequency = s->frequency; 478 s->timers[0].latch = 0xffff; 479 set_counter(s, &s->timers[0], 0xffff); 480 timer_del(s->timers[0].timer); 481 482 s->timers[1].frequency = s->frequency; 483 s->timers[1].latch = 0xffff; 484 timer_del(s->timers[1].timer); 485 } 486 487 static void mos6522_init(Object *obj) 488 { 489 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 490 MOS6522State *s = MOS6522(obj); 491 int i; 492 493 memory_region_init_io(&s->mem, obj, &mos6522_ops, s, "mos6522", 494 MOS6522_NUM_REGS); 495 sysbus_init_mmio(sbd, &s->mem); 496 sysbus_init_irq(sbd, &s->irq); 497 498 for (i = 0; i < ARRAY_SIZE(s->timers); i++) { 499 s->timers[i].index = i; 500 } 501 502 s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1, s); 503 s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2, s); 504 505 qdev_init_gpio_in(DEVICE(obj), mos6522_set_irq, VIA_NUM_INTS); 506 } 507 508 static void mos6522_finalize(Object *obj) 509 { 510 MOS6522State *s = MOS6522(obj); 511 512 timer_free(s->timers[0].timer); 513 timer_free(s->timers[1].timer); 514 } 515 516 static Property mos6522_properties[] = { 517 DEFINE_PROP_UINT64("frequency", MOS6522State, frequency, 0), 518 DEFINE_PROP_END_OF_LIST() 519 }; 520 521 static void mos6522_class_init(ObjectClass *oc, void *data) 522 { 523 DeviceClass *dc = DEVICE_CLASS(oc); 524 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); 525 526 dc->reset = mos6522_reset; 527 dc->vmsd = &vmstate_mos6522; 528 device_class_set_props(dc, mos6522_properties); 529 mdc->portB_write = mos6522_portB_write; 530 mdc->portA_write = mos6522_portA_write; 531 mdc->get_timer1_counter_value = mos6522_get_counter_value; 532 mdc->get_timer2_counter_value = mos6522_get_counter_value; 533 mdc->get_timer1_load_time = mos6522_get_load_time; 534 mdc->get_timer2_load_time = mos6522_get_load_time; 535 } 536 537 static const TypeInfo mos6522_type_info = { 538 .name = TYPE_MOS6522, 539 .parent = TYPE_SYS_BUS_DEVICE, 540 .instance_size = sizeof(MOS6522State), 541 .instance_init = mos6522_init, 542 .instance_finalize = mos6522_finalize, 543 .abstract = true, 544 .class_size = sizeof(MOS6522DeviceClass), 545 .class_init = mos6522_class_init, 546 }; 547 548 static void mos6522_register_types(void) 549 { 550 type_register_static(&mos6522_type_info); 551 } 552 553 type_init(mos6522_register_types) 554