1 /* 2 * QEMU MOS6522 VIA emulation 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2018 Mark Cave-Ayland 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/input/adb.h" 29 #include "hw/irq.h" 30 #include "hw/misc/mos6522.h" 31 #include "hw/qdev-properties.h" 32 #include "migration/vmstate.h" 33 #include "monitor/monitor.h" 34 #include "monitor/hmp.h" 35 #include "qapi/type-helpers.h" 36 #include "qemu/timer.h" 37 #include "qemu/cutils.h" 38 #include "qemu/log.h" 39 #include "qemu/module.h" 40 #include "trace.h" 41 42 43 static const char *mos6522_reg_names[MOS6522_NUM_REGS] = { 44 "ORB", "ORA", "DDRB", "DDRA", "T1CL", "T1CH", "T1LL", "T1LH", 45 "T2CL", "T2CH", "SR", "ACR", "PCR", "IFR", "IER", "ANH" 46 }; 47 48 /* XXX: implement all timer modes */ 49 50 static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti, 51 int64_t current_time); 52 static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti, 53 int64_t current_time); 54 55 static void mos6522_update_irq(MOS6522State *s) 56 { 57 if (s->ifr & s->ier) { 58 qemu_irq_raise(s->irq); 59 } else { 60 qemu_irq_lower(s->irq); 61 } 62 } 63 64 static void mos6522_set_irq(void *opaque, int n, int level) 65 { 66 MOS6522State *s = MOS6522(opaque); 67 68 if (level) { 69 s->ifr |= 1 << n; 70 } else { 71 s->ifr &= ~(1 << n); 72 } 73 74 mos6522_update_irq(s); 75 } 76 77 static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti) 78 { 79 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 80 81 if (ti->index == 0) { 82 return mdc->get_timer1_counter_value(s, ti); 83 } else { 84 return mdc->get_timer2_counter_value(s, ti); 85 } 86 } 87 88 static uint64_t get_load_time(MOS6522State *s, MOS6522Timer *ti) 89 { 90 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 91 92 if (ti->index == 0) { 93 return mdc->get_timer1_load_time(s, ti); 94 } else { 95 return mdc->get_timer2_load_time(s, ti); 96 } 97 } 98 99 static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti) 100 { 101 int64_t d; 102 unsigned int counter; 103 104 d = get_counter_value(s, ti); 105 106 if (ti->index == 0) { 107 /* the timer goes down from latch to -1 (period of latch + 2) */ 108 if (d <= (ti->counter_value + 1)) { 109 counter = (ti->counter_value - d) & 0xffff; 110 } else { 111 counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); 112 counter = (ti->latch - counter) & 0xffff; 113 } 114 } else { 115 counter = (ti->counter_value - d) & 0xffff; 116 } 117 return counter; 118 } 119 120 static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val) 121 { 122 trace_mos6522_set_counter(1 + ti->index, val); 123 ti->load_time = get_load_time(s, ti); 124 ti->counter_value = val; 125 if (ti->index == 0) { 126 mos6522_timer1_update(s, ti, ti->load_time); 127 } else { 128 mos6522_timer2_update(s, ti, ti->load_time); 129 } 130 } 131 132 static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti, 133 int64_t current_time) 134 { 135 int64_t d, next_time; 136 unsigned int counter; 137 138 if (ti->frequency == 0) { 139 return INT64_MAX; 140 } 141 142 /* current counter value */ 143 d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, 144 ti->frequency, NANOSECONDS_PER_SECOND); 145 146 /* the timer goes down from latch to -1 (period of latch + 2) */ 147 if (d <= (ti->counter_value + 1)) { 148 counter = (ti->counter_value - d) & 0xffff; 149 } else { 150 counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); 151 counter = (ti->latch - counter) & 0xffff; 152 } 153 154 /* Note: we consider the irq is raised on 0 */ 155 if (counter == 0xffff) { 156 next_time = d + ti->latch + 1; 157 } else if (counter == 0) { 158 next_time = d + ti->latch + 2; 159 } else { 160 next_time = d + counter; 161 } 162 trace_mos6522_get_next_irq_time(ti->latch, d, next_time - d); 163 next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequency) + 164 ti->load_time; 165 166 if (next_time <= current_time) { 167 next_time = current_time + 1; 168 } 169 return next_time; 170 } 171 172 static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti, 173 int64_t current_time) 174 { 175 if (!ti->timer) { 176 return; 177 } 178 ti->next_irq_time = get_next_irq_time(s, ti, current_time); 179 if ((s->ier & T1_INT) == 0 || (s->acr & T1MODE) != T1MODE_CONT) { 180 timer_del(ti->timer); 181 } else { 182 timer_mod(ti->timer, ti->next_irq_time); 183 } 184 } 185 186 static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti, 187 int64_t current_time) 188 { 189 if (!ti->timer) { 190 return; 191 } 192 ti->next_irq_time = get_next_irq_time(s, ti, current_time); 193 if ((s->ier & T2_INT) == 0) { 194 timer_del(ti->timer); 195 } else { 196 timer_mod(ti->timer, ti->next_irq_time); 197 } 198 } 199 200 static void mos6522_timer1(void *opaque) 201 { 202 MOS6522State *s = opaque; 203 MOS6522Timer *ti = &s->timers[0]; 204 205 mos6522_timer1_update(s, ti, ti->next_irq_time); 206 s->ifr |= T1_INT; 207 mos6522_update_irq(s); 208 } 209 210 static void mos6522_timer2(void *opaque) 211 { 212 MOS6522State *s = opaque; 213 MOS6522Timer *ti = &s->timers[1]; 214 215 mos6522_timer2_update(s, ti, ti->next_irq_time); 216 s->ifr |= T2_INT; 217 mos6522_update_irq(s); 218 } 219 220 static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *ti) 221 { 222 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, 223 ti->frequency, NANOSECONDS_PER_SECOND); 224 } 225 226 static uint64_t mos6522_get_load_time(MOS6522State *s, MOS6522Timer *ti) 227 { 228 uint64_t load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 229 230 return load_time; 231 } 232 233 static void mos6522_portA_write(MOS6522State *s) 234 { 235 qemu_log_mask(LOG_UNIMP, "portA_write unimplemented\n"); 236 } 237 238 static void mos6522_portB_write(MOS6522State *s) 239 { 240 qemu_log_mask(LOG_UNIMP, "portB_write unimplemented\n"); 241 } 242 243 uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) 244 { 245 MOS6522State *s = opaque; 246 uint32_t val; 247 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 248 249 if (now >= s->timers[0].next_irq_time) { 250 mos6522_timer1_update(s, &s->timers[0], now); 251 s->ifr |= T1_INT; 252 } 253 if (now >= s->timers[1].next_irq_time) { 254 mos6522_timer2_update(s, &s->timers[1], now); 255 s->ifr |= T2_INT; 256 } 257 switch (addr) { 258 case VIA_REG_B: 259 val = s->b; 260 break; 261 case VIA_REG_A: 262 qemu_log_mask(LOG_UNIMP, "Read access to register A with handshake"); 263 /* fall through */ 264 case VIA_REG_ANH: 265 val = s->a; 266 break; 267 case VIA_REG_DIRB: 268 val = s->dirb; 269 break; 270 case VIA_REG_DIRA: 271 val = s->dira; 272 break; 273 case VIA_REG_T1CL: 274 val = get_counter(s, &s->timers[0]) & 0xff; 275 s->ifr &= ~T1_INT; 276 mos6522_update_irq(s); 277 break; 278 case VIA_REG_T1CH: 279 val = get_counter(s, &s->timers[0]) >> 8; 280 mos6522_update_irq(s); 281 break; 282 case VIA_REG_T1LL: 283 val = s->timers[0].latch & 0xff; 284 break; 285 case VIA_REG_T1LH: 286 /* XXX: check this */ 287 val = (s->timers[0].latch >> 8) & 0xff; 288 break; 289 case VIA_REG_T2CL: 290 val = get_counter(s, &s->timers[1]) & 0xff; 291 s->ifr &= ~T2_INT; 292 mos6522_update_irq(s); 293 break; 294 case VIA_REG_T2CH: 295 val = get_counter(s, &s->timers[1]) >> 8; 296 break; 297 case VIA_REG_SR: 298 val = s->sr; 299 s->ifr &= ~SR_INT; 300 mos6522_update_irq(s); 301 break; 302 case VIA_REG_ACR: 303 val = s->acr; 304 break; 305 case VIA_REG_PCR: 306 val = s->pcr; 307 break; 308 case VIA_REG_IFR: 309 val = s->ifr; 310 if (s->ifr & s->ier) { 311 val |= 0x80; 312 } 313 break; 314 case VIA_REG_IER: 315 val = s->ier | 0x80; 316 break; 317 default: 318 g_assert_not_reached(); 319 } 320 321 if (addr != VIA_REG_IFR || val != 0) { 322 trace_mos6522_read(addr, mos6522_reg_names[addr], val); 323 } 324 325 return val; 326 } 327 328 void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) 329 { 330 MOS6522State *s = opaque; 331 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 332 333 trace_mos6522_write(addr, mos6522_reg_names[addr], val); 334 335 switch (addr) { 336 case VIA_REG_B: 337 s->b = (s->b & ~s->dirb) | (val & s->dirb); 338 mdc->portB_write(s); 339 break; 340 case VIA_REG_A: 341 qemu_log_mask(LOG_UNIMP, "Write access to register A with handshake"); 342 /* fall through */ 343 case VIA_REG_ANH: 344 s->a = (s->a & ~s->dira) | (val & s->dira); 345 mdc->portA_write(s); 346 break; 347 case VIA_REG_DIRB: 348 s->dirb = val; 349 break; 350 case VIA_REG_DIRA: 351 s->dira = val; 352 break; 353 case VIA_REG_T1CL: 354 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; 355 mos6522_timer1_update(s, &s->timers[0], 356 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 357 break; 358 case VIA_REG_T1CH: 359 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); 360 s->ifr &= ~T1_INT; 361 set_counter(s, &s->timers[0], s->timers[0].latch); 362 break; 363 case VIA_REG_T1LL: 364 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; 365 mos6522_timer1_update(s, &s->timers[0], 366 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 367 break; 368 case VIA_REG_T1LH: 369 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); 370 s->ifr &= ~T1_INT; 371 mos6522_timer1_update(s, &s->timers[0], 372 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 373 break; 374 case VIA_REG_T2CL: 375 s->timers[1].latch = (s->timers[1].latch & 0xff00) | val; 376 break; 377 case VIA_REG_T2CH: 378 /* To ensure T2 generates an interrupt on zero crossing with the 379 common timer code, write the value directly from the latch to 380 the counter */ 381 s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8); 382 s->ifr &= ~T2_INT; 383 set_counter(s, &s->timers[1], s->timers[1].latch); 384 break; 385 case VIA_REG_SR: 386 s->sr = val; 387 break; 388 case VIA_REG_ACR: 389 s->acr = val; 390 mos6522_timer1_update(s, &s->timers[0], 391 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 392 break; 393 case VIA_REG_PCR: 394 s->pcr = val; 395 break; 396 case VIA_REG_IFR: 397 /* reset bits */ 398 s->ifr &= ~val; 399 mos6522_update_irq(s); 400 break; 401 case VIA_REG_IER: 402 if (val & IER_SET) { 403 /* set bits */ 404 s->ier |= val & 0x7f; 405 } else { 406 /* reset bits */ 407 s->ier &= ~val; 408 } 409 mos6522_update_irq(s); 410 /* if IER is modified starts needed timers */ 411 mos6522_timer1_update(s, &s->timers[0], 412 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 413 mos6522_timer2_update(s, &s->timers[1], 414 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 415 break; 416 default: 417 g_assert_not_reached(); 418 } 419 } 420 421 static int qmp_x_query_via_foreach(Object *obj, void *opaque) 422 { 423 GString *buf = opaque; 424 425 if (object_dynamic_cast(obj, TYPE_MOS6522)) { 426 MOS6522State *s = MOS6522(obj); 427 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 428 uint16_t t1counter = get_counter(s, &s->timers[0]); 429 uint16_t t2counter = get_counter(s, &s->timers[1]); 430 431 g_string_append_printf(buf, "%s:\n", object_get_typename(obj)); 432 433 g_string_append_printf(buf, " Registers:\n"); 434 g_string_append_printf(buf, " %-*s: 0x%x\n", 4, 435 mos6522_reg_names[0], s->b); 436 g_string_append_printf(buf, " %-*s: 0x%x\n", 4, 437 mos6522_reg_names[1], s->a); 438 g_string_append_printf(buf, " %-*s: 0x%x\n", 4, 439 mos6522_reg_names[2], s->dirb); 440 g_string_append_printf(buf, " %-*s: 0x%x\n", 4, 441 mos6522_reg_names[3], s->dira); 442 g_string_append_printf(buf, " %-*s: 0x%x\n", 4, 443 mos6522_reg_names[4], t1counter & 0xff); 444 g_string_append_printf(buf, " %-*s: 0x%x\n", 4, 445 mos6522_reg_names[5], t1counter >> 8); 446 g_string_append_printf(buf, " %-*s: 0x%x\n", 4, 447 mos6522_reg_names[6], 448 s->timers[0].latch & 0xff); 449 g_string_append_printf(buf, " %-*s: 0x%x\n", 4, 450 mos6522_reg_names[7], 451 s->timers[0].latch >> 8); 452 g_string_append_printf(buf, " %-*s: 0x%x\n", 4, 453 mos6522_reg_names[8], t2counter & 0xff); 454 g_string_append_printf(buf, " %-*s: 0x%x\n", 4, 455 mos6522_reg_names[9], t2counter >> 8); 456 g_string_append_printf(buf, " %-*s: 0x%x\n", 4, 457 mos6522_reg_names[10], s->sr); 458 g_string_append_printf(buf, " %-*s: 0x%x\n", 4, 459 mos6522_reg_names[11], s->acr); 460 g_string_append_printf(buf, " %-*s: 0x%x\n", 4, 461 mos6522_reg_names[12], s->pcr); 462 g_string_append_printf(buf, " %-*s: 0x%x\n", 4, 463 mos6522_reg_names[13], s->ifr); 464 g_string_append_printf(buf, " %-*s: 0x%x\n", 4, 465 mos6522_reg_names[14], s->ier); 466 467 g_string_append_printf(buf, " Timers:\n"); 468 g_string_append_printf(buf, " Using current time now(ns)=%"PRId64 469 "\n", now); 470 g_string_append_printf(buf, " T1 freq(hz)=%"PRId64 471 " mode=%s" 472 " counter=0x%x" 473 " latch=0x%x\n" 474 " load_time(ns)=%"PRId64 475 " next_irq_time(ns)=%"PRId64 "\n", 476 s->timers[0].frequency, 477 ((s->acr & T1MODE) == T1MODE_CONT) ? "continuous" 478 : "one-shot", 479 t1counter, 480 s->timers[0].latch, 481 s->timers[0].load_time, 482 get_next_irq_time(s, &s->timers[0], now)); 483 g_string_append_printf(buf, " T2 freq(hz)=%"PRId64 484 " mode=%s" 485 " counter=0x%x" 486 " latch=0x%x\n" 487 " load_time(ns)=%"PRId64 488 " next_irq_time(ns)=%"PRId64 "\n", 489 s->timers[1].frequency, 490 "one-shot", 491 t2counter, 492 s->timers[1].latch, 493 s->timers[1].load_time, 494 get_next_irq_time(s, &s->timers[1], now)); 495 } 496 497 return 0; 498 } 499 500 static HumanReadableText *qmp_x_query_via(Error **errp) 501 { 502 g_autoptr(GString) buf = g_string_new(""); 503 504 object_child_foreach_recursive(object_get_root(), 505 qmp_x_query_via_foreach, buf); 506 507 return human_readable_text_from_str(buf); 508 } 509 510 void hmp_info_via(Monitor *mon, const QDict *qdict) 511 { 512 Error *err = NULL; 513 g_autoptr(HumanReadableText) info = qmp_x_query_via(&err); 514 515 if (hmp_handle_error(mon, err)) { 516 return; 517 } 518 monitor_printf(mon, "%s", info->human_readable_text); 519 } 520 521 static const MemoryRegionOps mos6522_ops = { 522 .read = mos6522_read, 523 .write = mos6522_write, 524 .endianness = DEVICE_NATIVE_ENDIAN, 525 .valid = { 526 .min_access_size = 1, 527 .max_access_size = 1, 528 }, 529 }; 530 531 static const VMStateDescription vmstate_mos6522_timer = { 532 .name = "mos6522_timer", 533 .version_id = 0, 534 .minimum_version_id = 0, 535 .fields = (VMStateField[]) { 536 VMSTATE_UINT16(latch, MOS6522Timer), 537 VMSTATE_UINT16(counter_value, MOS6522Timer), 538 VMSTATE_INT64(load_time, MOS6522Timer), 539 VMSTATE_INT64(next_irq_time, MOS6522Timer), 540 VMSTATE_TIMER_PTR(timer, MOS6522Timer), 541 VMSTATE_END_OF_LIST() 542 } 543 }; 544 545 const VMStateDescription vmstate_mos6522 = { 546 .name = "mos6522", 547 .version_id = 0, 548 .minimum_version_id = 0, 549 .fields = (VMStateField[]) { 550 VMSTATE_UINT8(a, MOS6522State), 551 VMSTATE_UINT8(b, MOS6522State), 552 VMSTATE_UINT8(dira, MOS6522State), 553 VMSTATE_UINT8(dirb, MOS6522State), 554 VMSTATE_UINT8(sr, MOS6522State), 555 VMSTATE_UINT8(acr, MOS6522State), 556 VMSTATE_UINT8(pcr, MOS6522State), 557 VMSTATE_UINT8(ifr, MOS6522State), 558 VMSTATE_UINT8(ier, MOS6522State), 559 VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 0, 560 vmstate_mos6522_timer, MOS6522Timer), 561 VMSTATE_END_OF_LIST() 562 } 563 }; 564 565 static void mos6522_reset(DeviceState *dev) 566 { 567 MOS6522State *s = MOS6522(dev); 568 569 s->b = 0; 570 s->a = 0; 571 s->dirb = 0xff; 572 s->dira = 0; 573 s->sr = 0; 574 s->acr = 0; 575 s->pcr = 0; 576 s->ifr = 0; 577 s->ier = 0; 578 /* s->ier = T1_INT | SR_INT; */ 579 580 s->timers[0].frequency = s->frequency; 581 s->timers[0].latch = 0xffff; 582 set_counter(s, &s->timers[0], 0xffff); 583 timer_del(s->timers[0].timer); 584 585 s->timers[1].frequency = s->frequency; 586 s->timers[1].latch = 0xffff; 587 timer_del(s->timers[1].timer); 588 } 589 590 static void mos6522_init(Object *obj) 591 { 592 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 593 MOS6522State *s = MOS6522(obj); 594 int i; 595 596 memory_region_init_io(&s->mem, obj, &mos6522_ops, s, "mos6522", 597 MOS6522_NUM_REGS); 598 sysbus_init_mmio(sbd, &s->mem); 599 sysbus_init_irq(sbd, &s->irq); 600 601 for (i = 0; i < ARRAY_SIZE(s->timers); i++) { 602 s->timers[i].index = i; 603 } 604 605 s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1, s); 606 s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2, s); 607 608 qdev_init_gpio_in(DEVICE(obj), mos6522_set_irq, VIA_NUM_INTS); 609 } 610 611 static void mos6522_finalize(Object *obj) 612 { 613 MOS6522State *s = MOS6522(obj); 614 615 timer_free(s->timers[0].timer); 616 timer_free(s->timers[1].timer); 617 } 618 619 static Property mos6522_properties[] = { 620 DEFINE_PROP_UINT64("frequency", MOS6522State, frequency, 0), 621 DEFINE_PROP_END_OF_LIST() 622 }; 623 624 static void mos6522_class_init(ObjectClass *oc, void *data) 625 { 626 DeviceClass *dc = DEVICE_CLASS(oc); 627 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); 628 629 dc->reset = mos6522_reset; 630 dc->vmsd = &vmstate_mos6522; 631 device_class_set_props(dc, mos6522_properties); 632 mdc->portB_write = mos6522_portB_write; 633 mdc->portA_write = mos6522_portA_write; 634 mdc->get_timer1_counter_value = mos6522_get_counter_value; 635 mdc->get_timer2_counter_value = mos6522_get_counter_value; 636 mdc->get_timer1_load_time = mos6522_get_load_time; 637 mdc->get_timer2_load_time = mos6522_get_load_time; 638 } 639 640 static const TypeInfo mos6522_type_info = { 641 .name = TYPE_MOS6522, 642 .parent = TYPE_SYS_BUS_DEVICE, 643 .instance_size = sizeof(MOS6522State), 644 .instance_init = mos6522_init, 645 .instance_finalize = mos6522_finalize, 646 .abstract = true, 647 .class_size = sizeof(MOS6522DeviceClass), 648 .class_init = mos6522_class_init, 649 }; 650 651 static void mos6522_register_types(void) 652 { 653 type_register_static(&mos6522_type_info); 654 } 655 656 type_init(mos6522_register_types) 657