1 /* 2 * Inter-Thread Communication Unit emulation. 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "cpu.h" 23 #include "hw/hw.h" 24 #include "hw/sysbus.h" 25 #include "sysemu/sysemu.h" 26 #include "hw/misc/mips_itu.h" 27 28 #define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8) 29 /* Initialize as 4kB area to fit all 32 cells with default 128B grain. 30 Storage may be resized by the software. */ 31 #define ITC_STORAGE_ADDRSPACE_SZ 0x1000 32 33 #define ITC_FIFO_NUM_MAX 16 34 #define ITC_SEMAPH_NUM_MAX 16 35 #define ITC_AM1_NUMENTRIES_OFS 20 36 37 #define ITC_CELL_PV_MAX_VAL 0xFFFF 38 39 #define ITC_CELL_TAG_FIFO_DEPTH 28 40 #define ITC_CELL_TAG_FIFO_PTR 18 41 #define ITC_CELL_TAG_FIFO 17 42 #define ITC_CELL_TAG_T 16 43 #define ITC_CELL_TAG_F 1 44 #define ITC_CELL_TAG_E 0 45 46 #define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL 47 #define ITC_AM0_EN_MASK 0x1 48 49 #define ITC_AM1_ADDR_MASK_MASK 0x1FC00 50 #define ITC_AM1_ENTRY_GRAIN_MASK 0x7 51 52 typedef enum ITCView { 53 ITCVIEW_BYPASS = 0, 54 ITCVIEW_CONTROL = 1, 55 ITCVIEW_EF_SYNC = 2, 56 ITCVIEW_EF_TRY = 3, 57 ITCVIEW_PV_SYNC = 4, 58 ITCVIEW_PV_TRY = 5 59 } ITCView; 60 61 MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu) 62 { 63 return &itu->tag_io; 64 } 65 66 static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size) 67 { 68 MIPSITUState *tag = (MIPSITUState *)opaque; 69 uint64_t index = addr >> 3; 70 71 if (index >= ITC_ADDRESSMAP_NUM) { 72 qemu_log_mask(LOG_GUEST_ERROR, "Read 0x%" PRIx64 "\n", addr); 73 return 0; 74 } 75 76 return tag->ITCAddressMap[index]; 77 } 78 79 static void itc_reconfigure(MIPSITUState *tag) 80 { 81 uint64_t *am = &tag->ITCAddressMap[0]; 82 MemoryRegion *mr = &tag->storage_io; 83 hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK; 84 uint64_t size = (1 << 10) + (am[1] & ITC_AM1_ADDR_MASK_MASK); 85 bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0; 86 87 memory_region_transaction_begin(); 88 if (!(size & (size - 1))) { 89 memory_region_set_size(mr, size); 90 } 91 memory_region_set_address(mr, address); 92 memory_region_set_enabled(mr, is_enabled); 93 memory_region_transaction_commit(); 94 } 95 96 static void itc_tag_write(void *opaque, hwaddr addr, 97 uint64_t data, unsigned size) 98 { 99 MIPSITUState *tag = (MIPSITUState *)opaque; 100 uint64_t *am = &tag->ITCAddressMap[0]; 101 uint64_t am_old, mask; 102 uint64_t index = addr >> 3; 103 104 switch (index) { 105 case 0: 106 mask = ITC_AM0_BASE_ADDRESS_MASK | ITC_AM0_EN_MASK; 107 break; 108 case 1: 109 mask = ITC_AM1_ADDR_MASK_MASK | ITC_AM1_ENTRY_GRAIN_MASK; 110 break; 111 default: 112 qemu_log_mask(LOG_GUEST_ERROR, "Bad write 0x%" PRIx64 "\n", addr); 113 return; 114 } 115 116 am_old = am[index]; 117 am[index] = (data & mask) | (am_old & ~mask); 118 if (am_old != am[index]) { 119 itc_reconfigure(tag); 120 } 121 } 122 123 static const MemoryRegionOps itc_tag_ops = { 124 .read = itc_tag_read, 125 .write = itc_tag_write, 126 .impl = { 127 .max_access_size = 8, 128 }, 129 .endianness = DEVICE_NATIVE_ENDIAN, 130 }; 131 132 static inline uint32_t get_num_cells(MIPSITUState *s) 133 { 134 return s->num_fifo + s->num_semaphores; 135 } 136 137 static inline ITCView get_itc_view(hwaddr addr) 138 { 139 return (addr >> 3) & 0xf; 140 } 141 142 static inline int get_cell_stride_shift(const MIPSITUState *s) 143 { 144 /* Minimum interval (for EntryGain = 0) is 128 B */ 145 return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); 146 } 147 148 static inline ITCStorageCell *get_cell(MIPSITUState *s, 149 hwaddr addr) 150 { 151 uint32_t cell_idx = addr >> get_cell_stride_shift(s); 152 uint32_t num_cells = get_num_cells(s); 153 154 if (cell_idx >= num_cells) { 155 cell_idx = num_cells - 1; 156 } 157 158 return &s->cell[cell_idx]; 159 } 160 161 static void wake_blocked_threads(ITCStorageCell *c) 162 { 163 CPUState *cs; 164 CPU_FOREACH(cs) { 165 if (cs->halted && (c->blocked_threads & (1ULL << cs->cpu_index))) { 166 cpu_interrupt(cs, CPU_INTERRUPT_WAKE); 167 } 168 } 169 c->blocked_threads = 0; 170 } 171 172 static void QEMU_NORETURN block_thread_and_exit(ITCStorageCell *c) 173 { 174 c->blocked_threads |= 1ULL << current_cpu->cpu_index; 175 cpu_restore_state(current_cpu, current_cpu->mem_io_pc); 176 current_cpu->halted = 1; 177 current_cpu->exception_index = EXCP_HLT; 178 cpu_loop_exit(current_cpu); 179 } 180 181 /* ITC Bypass View */ 182 183 static inline uint64_t view_bypass_read(ITCStorageCell *c) 184 { 185 if (c->tag.FIFO) { 186 return c->data[c->fifo_out]; 187 } else { 188 return c->data[0]; 189 } 190 } 191 192 static inline void view_bypass_write(ITCStorageCell *c, uint64_t val) 193 { 194 if (c->tag.FIFO && (c->tag.FIFOPtr > 0)) { 195 int idx = (c->fifo_out + c->tag.FIFOPtr - 1) % ITC_CELL_DEPTH; 196 c->data[idx] = val; 197 } 198 199 /* ignore a write to the semaphore cell */ 200 } 201 202 /* ITC Control View */ 203 204 static inline uint64_t view_control_read(ITCStorageCell *c) 205 { 206 return ((uint64_t)c->tag.FIFODepth << ITC_CELL_TAG_FIFO_DEPTH) | 207 (c->tag.FIFOPtr << ITC_CELL_TAG_FIFO_PTR) | 208 (c->tag.FIFO << ITC_CELL_TAG_FIFO) | 209 (c->tag.T << ITC_CELL_TAG_T) | 210 (c->tag.E << ITC_CELL_TAG_E) | 211 (c->tag.F << ITC_CELL_TAG_F); 212 } 213 214 static inline void view_control_write(ITCStorageCell *c, uint64_t val) 215 { 216 c->tag.T = (val >> ITC_CELL_TAG_T) & 1; 217 c->tag.E = (val >> ITC_CELL_TAG_E) & 1; 218 c->tag.F = (val >> ITC_CELL_TAG_F) & 1; 219 220 if (c->tag.E) { 221 c->tag.FIFOPtr = 0; 222 } 223 } 224 225 /* ITC Empty/Full View */ 226 227 static uint64_t view_ef_common_read(ITCStorageCell *c, bool blocking) 228 { 229 uint64_t ret = 0; 230 231 if (!c->tag.FIFO) { 232 return 0; 233 } 234 235 c->tag.F = 0; 236 237 if (blocking && c->tag.E) { 238 block_thread_and_exit(c); 239 } 240 241 if (c->blocked_threads) { 242 wake_blocked_threads(c); 243 } 244 245 if (c->tag.FIFOPtr > 0) { 246 ret = c->data[c->fifo_out]; 247 c->fifo_out = (c->fifo_out + 1) % ITC_CELL_DEPTH; 248 c->tag.FIFOPtr--; 249 } 250 251 if (c->tag.FIFOPtr == 0) { 252 c->tag.E = 1; 253 } 254 255 return ret; 256 } 257 258 static uint64_t view_ef_sync_read(ITCStorageCell *c) 259 { 260 return view_ef_common_read(c, true); 261 } 262 263 static uint64_t view_ef_try_read(ITCStorageCell *c) 264 { 265 return view_ef_common_read(c, false); 266 } 267 268 static inline void view_ef_common_write(ITCStorageCell *c, uint64_t val, 269 bool blocking) 270 { 271 if (!c->tag.FIFO) { 272 return; 273 } 274 275 c->tag.E = 0; 276 277 if (blocking && c->tag.F) { 278 block_thread_and_exit(c); 279 } 280 281 if (c->blocked_threads) { 282 wake_blocked_threads(c); 283 } 284 285 if (c->tag.FIFOPtr < ITC_CELL_DEPTH) { 286 int idx = (c->fifo_out + c->tag.FIFOPtr) % ITC_CELL_DEPTH; 287 c->data[idx] = val; 288 c->tag.FIFOPtr++; 289 } 290 291 if (c->tag.FIFOPtr == ITC_CELL_DEPTH) { 292 c->tag.F = 1; 293 } 294 } 295 296 static void view_ef_sync_write(ITCStorageCell *c, uint64_t val) 297 { 298 view_ef_common_write(c, val, true); 299 } 300 301 static void view_ef_try_write(ITCStorageCell *c, uint64_t val) 302 { 303 view_ef_common_write(c, val, false); 304 } 305 306 /* ITC P/V View */ 307 308 static uint64_t view_pv_common_read(ITCStorageCell *c, bool blocking) 309 { 310 uint64_t ret = c->data[0]; 311 312 if (c->tag.FIFO) { 313 return 0; 314 } 315 316 if (c->data[0] > 0) { 317 c->data[0]--; 318 } else if (blocking) { 319 block_thread_and_exit(c); 320 } 321 322 return ret; 323 } 324 325 static uint64_t view_pv_sync_read(ITCStorageCell *c) 326 { 327 return view_pv_common_read(c, true); 328 } 329 330 static uint64_t view_pv_try_read(ITCStorageCell *c) 331 { 332 return view_pv_common_read(c, false); 333 } 334 335 static inline void view_pv_common_write(ITCStorageCell *c) 336 { 337 if (c->tag.FIFO) { 338 return; 339 } 340 341 if (c->data[0] < ITC_CELL_PV_MAX_VAL) { 342 c->data[0]++; 343 } 344 345 if (c->blocked_threads) { 346 wake_blocked_threads(c); 347 } 348 } 349 350 static void view_pv_sync_write(ITCStorageCell *c) 351 { 352 view_pv_common_write(c); 353 } 354 355 static void view_pv_try_write(ITCStorageCell *c) 356 { 357 view_pv_common_write(c); 358 } 359 360 static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size) 361 { 362 MIPSITUState *s = (MIPSITUState *)opaque; 363 ITCStorageCell *cell = get_cell(s, addr); 364 ITCView view = get_itc_view(addr); 365 uint64_t ret = -1; 366 367 switch (view) { 368 case ITCVIEW_BYPASS: 369 ret = view_bypass_read(cell); 370 break; 371 case ITCVIEW_CONTROL: 372 ret = view_control_read(cell); 373 break; 374 case ITCVIEW_EF_SYNC: 375 ret = view_ef_sync_read(cell); 376 break; 377 case ITCVIEW_EF_TRY: 378 ret = view_ef_try_read(cell); 379 break; 380 case ITCVIEW_PV_SYNC: 381 ret = view_pv_sync_read(cell); 382 break; 383 case ITCVIEW_PV_TRY: 384 ret = view_pv_try_read(cell); 385 break; 386 default: 387 qemu_log_mask(LOG_GUEST_ERROR, 388 "itc_storage_read: Bad ITC View %d\n", (int)view); 389 break; 390 } 391 392 return ret; 393 } 394 395 static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data, 396 unsigned size) 397 { 398 MIPSITUState *s = (MIPSITUState *)opaque; 399 ITCStorageCell *cell = get_cell(s, addr); 400 ITCView view = get_itc_view(addr); 401 402 switch (view) { 403 case ITCVIEW_BYPASS: 404 view_bypass_write(cell, data); 405 break; 406 case ITCVIEW_CONTROL: 407 view_control_write(cell, data); 408 break; 409 case ITCVIEW_EF_SYNC: 410 view_ef_sync_write(cell, data); 411 break; 412 case ITCVIEW_EF_TRY: 413 view_ef_try_write(cell, data); 414 break; 415 case ITCVIEW_PV_SYNC: 416 view_pv_sync_write(cell); 417 break; 418 case ITCVIEW_PV_TRY: 419 view_pv_try_write(cell); 420 break; 421 default: 422 qemu_log_mask(LOG_GUEST_ERROR, 423 "itc_storage_write: Bad ITC View %d\n", (int)view); 424 break; 425 } 426 427 } 428 429 static const MemoryRegionOps itc_storage_ops = { 430 .read = itc_storage_read, 431 .write = itc_storage_write, 432 .endianness = DEVICE_NATIVE_ENDIAN, 433 }; 434 435 static void itc_reset_cells(MIPSITUState *s) 436 { 437 int i; 438 439 memset(s->cell, 0, get_num_cells(s) * sizeof(s->cell[0])); 440 441 for (i = 0; i < s->num_fifo; i++) { 442 s->cell[i].tag.E = 1; 443 s->cell[i].tag.FIFO = 1; 444 s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT; 445 } 446 } 447 448 static void mips_itu_init(Object *obj) 449 { 450 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 451 MIPSITUState *s = MIPS_ITU(obj); 452 453 memory_region_init_io(&s->storage_io, OBJECT(s), &itc_storage_ops, s, 454 "mips-itc-storage", ITC_STORAGE_ADDRSPACE_SZ); 455 sysbus_init_mmio(sbd, &s->storage_io); 456 457 memory_region_init_io(&s->tag_io, OBJECT(s), &itc_tag_ops, s, 458 "mips-itc-tag", ITC_TAG_ADDRSPACE_SZ); 459 } 460 461 static void mips_itu_realize(DeviceState *dev, Error **errp) 462 { 463 MIPSITUState *s = MIPS_ITU(dev); 464 465 if (s->num_fifo > ITC_FIFO_NUM_MAX) { 466 error_setg(errp, "Exceed maximum number of FIFO cells: %d", 467 s->num_fifo); 468 return; 469 } 470 if (s->num_semaphores > ITC_SEMAPH_NUM_MAX) { 471 error_setg(errp, "Exceed maximum number of Semaphore cells: %d", 472 s->num_semaphores); 473 return; 474 } 475 476 s->cell = g_new(ITCStorageCell, get_num_cells(s)); 477 } 478 479 static void mips_itu_reset(DeviceState *dev) 480 { 481 MIPSITUState *s = MIPS_ITU(dev); 482 483 s->ITCAddressMap[0] = 0; 484 s->ITCAddressMap[1] = 485 ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | 486 (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); 487 itc_reconfigure(s); 488 489 itc_reset_cells(s); 490 } 491 492 static Property mips_itu_properties[] = { 493 DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo, 494 ITC_FIFO_NUM_MAX), 495 DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores, 496 ITC_SEMAPH_NUM_MAX), 497 DEFINE_PROP_END_OF_LIST(), 498 }; 499 500 static void mips_itu_class_init(ObjectClass *klass, void *data) 501 { 502 DeviceClass *dc = DEVICE_CLASS(klass); 503 504 dc->props = mips_itu_properties; 505 dc->realize = mips_itu_realize; 506 dc->reset = mips_itu_reset; 507 } 508 509 static const TypeInfo mips_itu_info = { 510 .name = TYPE_MIPS_ITU, 511 .parent = TYPE_SYS_BUS_DEVICE, 512 .instance_size = sizeof(MIPSITUState), 513 .instance_init = mips_itu_init, 514 .class_init = mips_itu_class_init, 515 }; 516 517 static void mips_itu_register_types(void) 518 { 519 type_register_static(&mips_itu_info); 520 } 521 522 type_init(mips_itu_register_types) 523