1 /* 2 * Inter-Thread Communication Unit emulation. 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/log.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "exec/exec-all.h" 26 #include "hw/misc/mips_itu.h" 27 28 #define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8) 29 /* Initialize as 4kB area to fit all 32 cells with default 128B grain. 30 Storage may be resized by the software. */ 31 #define ITC_STORAGE_ADDRSPACE_SZ 0x1000 32 33 #define ITC_FIFO_NUM_MAX 16 34 #define ITC_SEMAPH_NUM_MAX 16 35 #define ITC_AM1_NUMENTRIES_OFS 20 36 37 #define ITC_CELL_PV_MAX_VAL 0xFFFF 38 39 #define ITC_CELL_TAG_FIFO_DEPTH 28 40 #define ITC_CELL_TAG_FIFO_PTR 18 41 #define ITC_CELL_TAG_FIFO 17 42 #define ITC_CELL_TAG_T 16 43 #define ITC_CELL_TAG_F 1 44 #define ITC_CELL_TAG_E 0 45 46 #define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL 47 #define ITC_AM0_EN_MASK 0x1 48 49 #define ITC_AM1_ADDR_MASK_MASK 0x1FC00 50 #define ITC_AM1_ENTRY_GRAIN_MASK 0x7 51 52 typedef enum ITCView { 53 ITCVIEW_BYPASS = 0, 54 ITCVIEW_CONTROL = 1, 55 ITCVIEW_EF_SYNC = 2, 56 ITCVIEW_EF_TRY = 3, 57 ITCVIEW_PV_SYNC = 4, 58 ITCVIEW_PV_TRY = 5, 59 ITCVIEW_PV_ICR0 = 15, 60 } ITCView; 61 62 #define ITC_ICR0_CELL_NUM 16 63 #define ITC_ICR0_BLK_GRAIN 8 64 #define ITC_ICR0_BLK_GRAIN_MASK 0x7 65 #define ITC_ICR0_ERR_AXI 2 66 #define ITC_ICR0_ERR_PARITY 1 67 #define ITC_ICR0_ERR_EXEC 0 68 69 MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu) 70 { 71 return &itu->tag_io; 72 } 73 74 static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size) 75 { 76 MIPSITUState *tag = (MIPSITUState *)opaque; 77 uint64_t index = addr >> 3; 78 79 if (index >= ITC_ADDRESSMAP_NUM) { 80 qemu_log_mask(LOG_GUEST_ERROR, "Read 0x%" PRIx64 "\n", addr); 81 return 0; 82 } 83 84 return tag->ITCAddressMap[index]; 85 } 86 87 void itc_reconfigure(MIPSITUState *tag) 88 { 89 uint64_t *am = &tag->ITCAddressMap[0]; 90 MemoryRegion *mr = &tag->storage_io; 91 hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK; 92 uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); 93 bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0; 94 95 if (tag->saar_present) { 96 address = ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4; 97 size = 1 << ((*(uint64_t *) tag->saar >> 1) & 0x1f); 98 is_enabled = *(uint64_t *) tag->saar & 1; 99 } 100 101 memory_region_transaction_begin(); 102 if (!(size & (size - 1))) { 103 memory_region_set_size(mr, size); 104 } 105 memory_region_set_address(mr, address); 106 memory_region_set_enabled(mr, is_enabled); 107 memory_region_transaction_commit(); 108 } 109 110 static void itc_tag_write(void *opaque, hwaddr addr, 111 uint64_t data, unsigned size) 112 { 113 MIPSITUState *tag = (MIPSITUState *)opaque; 114 uint64_t *am = &tag->ITCAddressMap[0]; 115 uint64_t am_old, mask; 116 uint64_t index = addr >> 3; 117 118 switch (index) { 119 case 0: 120 mask = ITC_AM0_BASE_ADDRESS_MASK | ITC_AM0_EN_MASK; 121 break; 122 case 1: 123 mask = ITC_AM1_ADDR_MASK_MASK | ITC_AM1_ENTRY_GRAIN_MASK; 124 break; 125 default: 126 qemu_log_mask(LOG_GUEST_ERROR, "Bad write 0x%" PRIx64 "\n", addr); 127 return; 128 } 129 130 am_old = am[index]; 131 am[index] = (data & mask) | (am_old & ~mask); 132 if (am_old != am[index]) { 133 itc_reconfigure(tag); 134 } 135 } 136 137 static const MemoryRegionOps itc_tag_ops = { 138 .read = itc_tag_read, 139 .write = itc_tag_write, 140 .impl = { 141 .max_access_size = 8, 142 }, 143 .endianness = DEVICE_NATIVE_ENDIAN, 144 }; 145 146 static inline uint32_t get_num_cells(MIPSITUState *s) 147 { 148 return s->num_fifo + s->num_semaphores; 149 } 150 151 static inline ITCView get_itc_view(hwaddr addr) 152 { 153 return (addr >> 3) & 0xf; 154 } 155 156 static inline int get_cell_stride_shift(const MIPSITUState *s) 157 { 158 /* Minimum interval (for EntryGain = 0) is 128 B */ 159 if (s->saar_present) { 160 return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) & 161 ITC_ICR0_BLK_GRAIN_MASK); 162 } else { 163 return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); 164 } 165 } 166 167 static inline ITCStorageCell *get_cell(MIPSITUState *s, 168 hwaddr addr) 169 { 170 uint32_t cell_idx = addr >> get_cell_stride_shift(s); 171 uint32_t num_cells = get_num_cells(s); 172 173 if (cell_idx >= num_cells) { 174 cell_idx = num_cells - 1; 175 } 176 177 return &s->cell[cell_idx]; 178 } 179 180 static void wake_blocked_threads(ITCStorageCell *c) 181 { 182 CPUState *cs; 183 CPU_FOREACH(cs) { 184 if (cs->halted && (c->blocked_threads & (1ULL << cs->cpu_index))) { 185 cpu_interrupt(cs, CPU_INTERRUPT_WAKE); 186 } 187 } 188 c->blocked_threads = 0; 189 } 190 191 static void QEMU_NORETURN block_thread_and_exit(ITCStorageCell *c) 192 { 193 c->blocked_threads |= 1ULL << current_cpu->cpu_index; 194 current_cpu->halted = 1; 195 current_cpu->exception_index = EXCP_HLT; 196 cpu_loop_exit_restore(current_cpu, current_cpu->mem_io_pc); 197 } 198 199 /* ITC Bypass View */ 200 201 static inline uint64_t view_bypass_read(ITCStorageCell *c) 202 { 203 if (c->tag.FIFO) { 204 return c->data[c->fifo_out]; 205 } else { 206 return c->data[0]; 207 } 208 } 209 210 static inline void view_bypass_write(ITCStorageCell *c, uint64_t val) 211 { 212 if (c->tag.FIFO && (c->tag.FIFOPtr > 0)) { 213 int idx = (c->fifo_out + c->tag.FIFOPtr - 1) % ITC_CELL_DEPTH; 214 c->data[idx] = val; 215 } 216 217 /* ignore a write to the semaphore cell */ 218 } 219 220 /* ITC Control View */ 221 222 static inline uint64_t view_control_read(ITCStorageCell *c) 223 { 224 return ((uint64_t)c->tag.FIFODepth << ITC_CELL_TAG_FIFO_DEPTH) | 225 (c->tag.FIFOPtr << ITC_CELL_TAG_FIFO_PTR) | 226 (c->tag.FIFO << ITC_CELL_TAG_FIFO) | 227 (c->tag.T << ITC_CELL_TAG_T) | 228 (c->tag.E << ITC_CELL_TAG_E) | 229 (c->tag.F << ITC_CELL_TAG_F); 230 } 231 232 static inline void view_control_write(ITCStorageCell *c, uint64_t val) 233 { 234 c->tag.T = (val >> ITC_CELL_TAG_T) & 1; 235 c->tag.E = (val >> ITC_CELL_TAG_E) & 1; 236 c->tag.F = (val >> ITC_CELL_TAG_F) & 1; 237 238 if (c->tag.E) { 239 c->tag.FIFOPtr = 0; 240 } 241 } 242 243 /* ITC Empty/Full View */ 244 245 static uint64_t view_ef_common_read(ITCStorageCell *c, bool blocking) 246 { 247 uint64_t ret = 0; 248 249 if (!c->tag.FIFO) { 250 return 0; 251 } 252 253 c->tag.F = 0; 254 255 if (blocking && c->tag.E) { 256 block_thread_and_exit(c); 257 } 258 259 if (c->blocked_threads) { 260 wake_blocked_threads(c); 261 } 262 263 if (c->tag.FIFOPtr > 0) { 264 ret = c->data[c->fifo_out]; 265 c->fifo_out = (c->fifo_out + 1) % ITC_CELL_DEPTH; 266 c->tag.FIFOPtr--; 267 } 268 269 if (c->tag.FIFOPtr == 0) { 270 c->tag.E = 1; 271 } 272 273 return ret; 274 } 275 276 static uint64_t view_ef_sync_read(ITCStorageCell *c) 277 { 278 return view_ef_common_read(c, true); 279 } 280 281 static uint64_t view_ef_try_read(ITCStorageCell *c) 282 { 283 return view_ef_common_read(c, false); 284 } 285 286 static inline void view_ef_common_write(ITCStorageCell *c, uint64_t val, 287 bool blocking) 288 { 289 if (!c->tag.FIFO) { 290 return; 291 } 292 293 c->tag.E = 0; 294 295 if (blocking && c->tag.F) { 296 block_thread_and_exit(c); 297 } 298 299 if (c->blocked_threads) { 300 wake_blocked_threads(c); 301 } 302 303 if (c->tag.FIFOPtr < ITC_CELL_DEPTH) { 304 int idx = (c->fifo_out + c->tag.FIFOPtr) % ITC_CELL_DEPTH; 305 c->data[idx] = val; 306 c->tag.FIFOPtr++; 307 } 308 309 if (c->tag.FIFOPtr == ITC_CELL_DEPTH) { 310 c->tag.F = 1; 311 } 312 } 313 314 static void view_ef_sync_write(ITCStorageCell *c, uint64_t val) 315 { 316 view_ef_common_write(c, val, true); 317 } 318 319 static void view_ef_try_write(ITCStorageCell *c, uint64_t val) 320 { 321 view_ef_common_write(c, val, false); 322 } 323 324 /* ITC P/V View */ 325 326 static uint64_t view_pv_common_read(ITCStorageCell *c, bool blocking) 327 { 328 uint64_t ret = c->data[0]; 329 330 if (c->tag.FIFO) { 331 return 0; 332 } 333 334 if (c->data[0] > 0) { 335 c->data[0]--; 336 } else if (blocking) { 337 block_thread_and_exit(c); 338 } 339 340 return ret; 341 } 342 343 static uint64_t view_pv_sync_read(ITCStorageCell *c) 344 { 345 return view_pv_common_read(c, true); 346 } 347 348 static uint64_t view_pv_try_read(ITCStorageCell *c) 349 { 350 return view_pv_common_read(c, false); 351 } 352 353 static inline void view_pv_common_write(ITCStorageCell *c) 354 { 355 if (c->tag.FIFO) { 356 return; 357 } 358 359 if (c->data[0] < ITC_CELL_PV_MAX_VAL) { 360 c->data[0]++; 361 } 362 363 if (c->blocked_threads) { 364 wake_blocked_threads(c); 365 } 366 } 367 368 static void view_pv_sync_write(ITCStorageCell *c) 369 { 370 view_pv_common_write(c); 371 } 372 373 static void view_pv_try_write(ITCStorageCell *c) 374 { 375 view_pv_common_write(c); 376 } 377 378 static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size) 379 { 380 MIPSITUState *s = (MIPSITUState *)opaque; 381 ITCStorageCell *cell = get_cell(s, addr); 382 ITCView view = get_itc_view(addr); 383 uint64_t ret = -1; 384 385 switch (view) { 386 case ITCVIEW_BYPASS: 387 ret = view_bypass_read(cell); 388 break; 389 case ITCVIEW_CONTROL: 390 ret = view_control_read(cell); 391 break; 392 case ITCVIEW_EF_SYNC: 393 ret = view_ef_sync_read(cell); 394 break; 395 case ITCVIEW_EF_TRY: 396 ret = view_ef_try_read(cell); 397 break; 398 case ITCVIEW_PV_SYNC: 399 ret = view_pv_sync_read(cell); 400 break; 401 case ITCVIEW_PV_TRY: 402 ret = view_pv_try_read(cell); 403 break; 404 case ITCVIEW_PV_ICR0: 405 ret = s->icr0; 406 break; 407 default: 408 qemu_log_mask(LOG_GUEST_ERROR, 409 "itc_storage_read: Bad ITC View %d\n", (int)view); 410 break; 411 } 412 413 return ret; 414 } 415 416 static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data, 417 unsigned size) 418 { 419 MIPSITUState *s = (MIPSITUState *)opaque; 420 ITCStorageCell *cell = get_cell(s, addr); 421 ITCView view = get_itc_view(addr); 422 423 switch (view) { 424 case ITCVIEW_BYPASS: 425 view_bypass_write(cell, data); 426 break; 427 case ITCVIEW_CONTROL: 428 view_control_write(cell, data); 429 break; 430 case ITCVIEW_EF_SYNC: 431 view_ef_sync_write(cell, data); 432 break; 433 case ITCVIEW_EF_TRY: 434 view_ef_try_write(cell, data); 435 break; 436 case ITCVIEW_PV_SYNC: 437 view_pv_sync_write(cell); 438 break; 439 case ITCVIEW_PV_TRY: 440 view_pv_try_write(cell); 441 break; 442 case ITCVIEW_PV_ICR0: 443 if (data & 0x7) { 444 /* clear ERROR bits */ 445 s->icr0 &= ~(data & 0x7); 446 } 447 /* set BLK_GRAIN */ 448 s->icr0 &= ~0x700; 449 s->icr0 |= data & 0x700; 450 break; 451 default: 452 qemu_log_mask(LOG_GUEST_ERROR, 453 "itc_storage_write: Bad ITC View %d\n", (int)view); 454 break; 455 } 456 457 } 458 459 static const MemoryRegionOps itc_storage_ops = { 460 .read = itc_storage_read, 461 .write = itc_storage_write, 462 .endianness = DEVICE_NATIVE_ENDIAN, 463 }; 464 465 static void itc_reset_cells(MIPSITUState *s) 466 { 467 int i; 468 469 memset(s->cell, 0, get_num_cells(s) * sizeof(s->cell[0])); 470 471 for (i = 0; i < s->num_fifo; i++) { 472 s->cell[i].tag.E = 1; 473 s->cell[i].tag.FIFO = 1; 474 s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT; 475 } 476 } 477 478 static void mips_itu_init(Object *obj) 479 { 480 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 481 MIPSITUState *s = MIPS_ITU(obj); 482 483 memory_region_init_io(&s->storage_io, OBJECT(s), &itc_storage_ops, s, 484 "mips-itc-storage", ITC_STORAGE_ADDRSPACE_SZ); 485 sysbus_init_mmio(sbd, &s->storage_io); 486 487 memory_region_init_io(&s->tag_io, OBJECT(s), &itc_tag_ops, s, 488 "mips-itc-tag", ITC_TAG_ADDRSPACE_SZ); 489 } 490 491 static void mips_itu_realize(DeviceState *dev, Error **errp) 492 { 493 MIPSITUState *s = MIPS_ITU(dev); 494 495 if (s->num_fifo > ITC_FIFO_NUM_MAX) { 496 error_setg(errp, "Exceed maximum number of FIFO cells: %d", 497 s->num_fifo); 498 return; 499 } 500 if (s->num_semaphores > ITC_SEMAPH_NUM_MAX) { 501 error_setg(errp, "Exceed maximum number of Semaphore cells: %d", 502 s->num_semaphores); 503 return; 504 } 505 506 s->cell = g_new(ITCStorageCell, get_num_cells(s)); 507 } 508 509 static void mips_itu_reset(DeviceState *dev) 510 { 511 MIPSITUState *s = MIPS_ITU(dev); 512 513 if (s->saar_present) { 514 *(uint64_t *) s->saar = 0x11 << 1; 515 s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM; 516 } else { 517 s->ITCAddressMap[0] = 0; 518 s->ITCAddressMap[1] = 519 ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | 520 (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); 521 } 522 itc_reconfigure(s); 523 524 itc_reset_cells(s); 525 } 526 527 static Property mips_itu_properties[] = { 528 DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo, 529 ITC_FIFO_NUM_MAX), 530 DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores, 531 ITC_SEMAPH_NUM_MAX), 532 DEFINE_PROP_BOOL("saar-present", MIPSITUState, saar_present, false), 533 DEFINE_PROP_END_OF_LIST(), 534 }; 535 536 static void mips_itu_class_init(ObjectClass *klass, void *data) 537 { 538 DeviceClass *dc = DEVICE_CLASS(klass); 539 540 dc->props = mips_itu_properties; 541 dc->realize = mips_itu_realize; 542 dc->reset = mips_itu_reset; 543 } 544 545 static const TypeInfo mips_itu_info = { 546 .name = TYPE_MIPS_ITU, 547 .parent = TYPE_SYS_BUS_DEVICE, 548 .instance_size = sizeof(MIPSITUState), 549 .instance_init = mips_itu_init, 550 .class_init = mips_itu_class_init, 551 }; 552 553 static void mips_itu_register_types(void) 554 { 555 type_register_static(&mips_itu_info); 556 } 557 558 type_init(mips_itu_register_types) 559