1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 7 * Authors: Sanjay Lal <sanjayl@kymasys.com> 8 * 9 * Copyright (C) 2015 Imagination Technologies 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "hw/sysbus.h" 16 #include "migration/vmstate.h" 17 #include "sysemu/sysemu.h" 18 #include "hw/misc/mips_cmgcr.h" 19 #include "hw/misc/mips_cpc.h" 20 #include "hw/qdev-properties.h" 21 #include "hw/intc/mips_gic.h" 22 23 static inline bool is_cpc_connected(MIPSGCRState *s) 24 { 25 return s->cpc_mr != NULL; 26 } 27 28 static inline bool is_gic_connected(MIPSGCRState *s) 29 { 30 return s->gic_mr != NULL; 31 } 32 33 static inline void update_gcr_base(MIPSGCRState *gcr, uint64_t val) 34 { 35 CPUState *cpu; 36 MIPSCPU *mips_cpu; 37 38 gcr->gcr_base = val & GCR_BASE_GCRBASE_MSK; 39 memory_region_set_address(&gcr->iomem, gcr->gcr_base); 40 41 CPU_FOREACH(cpu) { 42 mips_cpu = MIPS_CPU(cpu); 43 mips_cpu->env.CP0_CMGCRBase = gcr->gcr_base >> 4; 44 } 45 } 46 47 static inline void update_cpc_base(MIPSGCRState *gcr, uint64_t val) 48 { 49 if (is_cpc_connected(gcr)) { 50 gcr->cpc_base = val & GCR_CPC_BASE_MSK; 51 memory_region_transaction_begin(); 52 memory_region_set_address(gcr->cpc_mr, 53 gcr->cpc_base & GCR_CPC_BASE_CPCBASE_MSK); 54 memory_region_set_enabled(gcr->cpc_mr, 55 gcr->cpc_base & GCR_CPC_BASE_CPCEN_MSK); 56 memory_region_transaction_commit(); 57 } 58 } 59 60 static inline void update_gic_base(MIPSGCRState *gcr, uint64_t val) 61 { 62 if (is_gic_connected(gcr)) { 63 gcr->gic_base = val & GCR_GIC_BASE_MSK; 64 memory_region_transaction_begin(); 65 memory_region_set_address(gcr->gic_mr, 66 gcr->gic_base & GCR_GIC_BASE_GICBASE_MSK); 67 memory_region_set_enabled(gcr->gic_mr, 68 gcr->gic_base & GCR_GIC_BASE_GICEN_MSK); 69 memory_region_transaction_commit(); 70 } 71 } 72 73 /* Read GCR registers */ 74 static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size) 75 { 76 MIPSGCRState *gcr = (MIPSGCRState *) opaque; 77 MIPSGCRVPState *current_vps = &gcr->vps[current_cpu->cpu_index]; 78 MIPSGCRVPState *other_vps = &gcr->vps[current_vps->other]; 79 80 switch (addr) { 81 /* Global Control Block Register */ 82 case GCR_CONFIG_OFS: 83 /* Set PCORES to 0 */ 84 return 0; 85 case GCR_BASE_OFS: 86 return gcr->gcr_base; 87 case GCR_REV_OFS: 88 return gcr->gcr_rev; 89 case GCR_GIC_BASE_OFS: 90 return gcr->gic_base; 91 case GCR_CPC_BASE_OFS: 92 return gcr->cpc_base; 93 case GCR_GIC_STATUS_OFS: 94 return is_gic_connected(gcr); 95 case GCR_CPC_STATUS_OFS: 96 return is_cpc_connected(gcr); 97 case GCR_L2_CONFIG_OFS: 98 /* L2 BYPASS */ 99 return GCR_L2_CONFIG_BYPASS_MSK; 100 /* Core-Local and Core-Other Control Blocks */ 101 case MIPS_CLCB_OFS + GCR_CL_CONFIG_OFS: 102 case MIPS_COCB_OFS + GCR_CL_CONFIG_OFS: 103 /* Set PVP to # of VPs - 1 */ 104 return gcr->num_vps - 1; 105 case MIPS_CLCB_OFS + GCR_CL_RESETBASE_OFS: 106 return current_vps->reset_base; 107 case MIPS_COCB_OFS + GCR_CL_RESETBASE_OFS: 108 return other_vps->reset_base; 109 case MIPS_CLCB_OFS + GCR_CL_OTHER_OFS: 110 return current_vps->other; 111 case MIPS_COCB_OFS + GCR_CL_OTHER_OFS: 112 return other_vps->other; 113 default: 114 qemu_log_mask(LOG_UNIMP, "Read %d bytes at GCR offset 0x%" HWADDR_PRIx 115 "\n", size, addr); 116 return 0; 117 } 118 return 0; 119 } 120 121 static inline target_ulong get_exception_base(MIPSGCRVPState *vps) 122 { 123 /* TODO: BEV_BASE and SELECT_BEV */ 124 return (int32_t)(vps->reset_base & GCR_CL_RESET_BASE_RESETBASE_MSK); 125 } 126 127 /* Write GCR registers */ 128 static void gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) 129 { 130 MIPSGCRState *gcr = (MIPSGCRState *)opaque; 131 MIPSGCRVPState *current_vps = &gcr->vps[current_cpu->cpu_index]; 132 MIPSGCRVPState *other_vps = &gcr->vps[current_vps->other]; 133 134 switch (addr) { 135 case GCR_BASE_OFS: 136 update_gcr_base(gcr, data); 137 break; 138 case GCR_GIC_BASE_OFS: 139 update_gic_base(gcr, data); 140 break; 141 case GCR_CPC_BASE_OFS: 142 update_cpc_base(gcr, data); 143 break; 144 case MIPS_CLCB_OFS + GCR_CL_RESETBASE_OFS: 145 current_vps->reset_base = data & GCR_CL_RESET_BASE_MSK; 146 cpu_set_exception_base(current_cpu->cpu_index, 147 get_exception_base(current_vps)); 148 break; 149 case MIPS_COCB_OFS + GCR_CL_RESETBASE_OFS: 150 other_vps->reset_base = data & GCR_CL_RESET_BASE_MSK; 151 cpu_set_exception_base(current_vps->other, 152 get_exception_base(other_vps)); 153 break; 154 case MIPS_CLCB_OFS + GCR_CL_OTHER_OFS: 155 if ((data & GCR_CL_OTHER_MSK) < gcr->num_vps) { 156 current_vps->other = data & GCR_CL_OTHER_MSK; 157 } 158 break; 159 case MIPS_COCB_OFS + GCR_CL_OTHER_OFS: 160 if ((data & GCR_CL_OTHER_MSK) < gcr->num_vps) { 161 other_vps->other = data & GCR_CL_OTHER_MSK; 162 } 163 break; 164 default: 165 qemu_log_mask(LOG_UNIMP, "Write %d bytes at GCR offset 0x%" HWADDR_PRIx 166 " 0x%" PRIx64 "\n", size, addr, data); 167 break; 168 } 169 } 170 171 static const MemoryRegionOps gcr_ops = { 172 .read = gcr_read, 173 .write = gcr_write, 174 .endianness = DEVICE_NATIVE_ENDIAN, 175 .impl = { 176 .max_access_size = 8, 177 }, 178 }; 179 180 static void mips_gcr_init(Object *obj) 181 { 182 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 183 MIPSGCRState *s = MIPS_GCR(obj); 184 185 memory_region_init_io(&s->iomem, OBJECT(s), &gcr_ops, s, 186 "mips-gcr", GCR_ADDRSPACE_SZ); 187 sysbus_init_mmio(sbd, &s->iomem); 188 } 189 190 static void mips_gcr_reset(DeviceState *dev) 191 { 192 MIPSGCRState *s = MIPS_GCR(dev); 193 int i; 194 195 update_gic_base(s, 0); 196 update_cpc_base(s, 0); 197 198 for (i = 0; i < s->num_vps; i++) { 199 s->vps[i].other = 0; 200 s->vps[i].reset_base = 0xBFC00000 & GCR_CL_RESET_BASE_MSK; 201 cpu_set_exception_base(i, get_exception_base(&s->vps[i])); 202 } 203 } 204 205 static const VMStateDescription vmstate_mips_gcr = { 206 .name = "mips-gcr", 207 .version_id = 0, 208 .minimum_version_id = 0, 209 .fields = (VMStateField[]) { 210 VMSTATE_UINT64(cpc_base, MIPSGCRState), 211 VMSTATE_END_OF_LIST() 212 }, 213 }; 214 215 static Property mips_gcr_properties[] = { 216 DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1), 217 DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800), 218 DEFINE_PROP_UINT64("gcr-base", MIPSGCRState, gcr_base, GCR_BASE_ADDR), 219 DEFINE_PROP_LINK("gic", MIPSGCRState, gic_mr, TYPE_MEMORY_REGION, 220 MemoryRegion *), 221 DEFINE_PROP_LINK("cpc", MIPSGCRState, cpc_mr, TYPE_MEMORY_REGION, 222 MemoryRegion *), 223 DEFINE_PROP_END_OF_LIST(), 224 }; 225 226 static void mips_gcr_realize(DeviceState *dev, Error **errp) 227 { 228 MIPSGCRState *s = MIPS_GCR(dev); 229 230 /* Create local set of registers for each VP */ 231 s->vps = g_new(MIPSGCRVPState, s->num_vps); 232 } 233 234 static void mips_gcr_class_init(ObjectClass *klass, void *data) 235 { 236 DeviceClass *dc = DEVICE_CLASS(klass); 237 dc->props = mips_gcr_properties; 238 dc->vmsd = &vmstate_mips_gcr; 239 dc->reset = mips_gcr_reset; 240 dc->realize = mips_gcr_realize; 241 } 242 243 static const TypeInfo mips_gcr_info = { 244 .name = TYPE_MIPS_GCR, 245 .parent = TYPE_SYS_BUS_DEVICE, 246 .instance_size = sizeof(MIPSGCRState), 247 .instance_init = mips_gcr_init, 248 .class_init = mips_gcr_class_init, 249 }; 250 251 static void mips_gcr_register_types(void) 252 { 253 type_register_static(&mips_gcr_info); 254 } 255 256 type_init(mips_gcr_register_types) 257