1 /* 2 * Microchip PolarFire SoC SYSREG module emulation 3 * 4 * Copyright (c) 2020 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 or 12 * (at your option) version 3 of the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qemu/bitops.h" 25 #include "qemu/log.h" 26 #include "qapi/error.h" 27 #include "hw/irq.h" 28 #include "hw/sysbus.h" 29 #include "hw/misc/mchp_pfsoc_sysreg.h" 30 #include "system/runstate.h" 31 32 #define MSS_RESET_CR 0x18 33 #define ENVM_CR 0xb8 34 #define MESSAGE_INT 0x118c 35 36 static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset, 37 unsigned size) 38 { 39 uint32_t val = 0; 40 41 switch (offset) { 42 case ENVM_CR: 43 /* Indicate the eNVM is running at the configured divider rate */ 44 val = BIT(6); 45 break; 46 default: 47 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " 48 "(size %d, offset 0x%" HWADDR_PRIx ")\n", 49 __func__, size, offset); 50 break; 51 } 52 53 return val; 54 } 55 56 static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset, 57 uint64_t value, unsigned size) 58 { 59 MchpPfSoCSysregState *s = opaque; 60 switch (offset) { 61 case MSS_RESET_CR: 62 if (value == 0xdead) { 63 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 64 } 65 break; 66 case MESSAGE_INT: 67 qemu_irq_lower(s->irq); 68 break; 69 default: 70 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " 71 "(size %d, value 0x%" PRIx64 72 ", offset 0x%" HWADDR_PRIx ")\n", 73 __func__, size, value, offset); 74 } 75 } 76 77 static const MemoryRegionOps mchp_pfsoc_sysreg_ops = { 78 .read = mchp_pfsoc_sysreg_read, 79 .write = mchp_pfsoc_sysreg_write, 80 .endianness = DEVICE_LITTLE_ENDIAN, 81 }; 82 83 static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp) 84 { 85 MchpPfSoCSysregState *s = MCHP_PFSOC_SYSREG(dev); 86 87 memory_region_init_io(&s->sysreg, OBJECT(dev), 88 &mchp_pfsoc_sysreg_ops, s, 89 "mchp.pfsoc.sysreg", 90 MCHP_PFSOC_SYSREG_REG_SIZE); 91 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg); 92 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); 93 } 94 95 static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, const void *data) 96 { 97 DeviceClass *dc = DEVICE_CLASS(klass); 98 99 dc->desc = "Microchip PolarFire SoC SYSREG module"; 100 dc->realize = mchp_pfsoc_sysreg_realize; 101 } 102 103 static const TypeInfo mchp_pfsoc_sysreg_info = { 104 .name = TYPE_MCHP_PFSOC_SYSREG, 105 .parent = TYPE_SYS_BUS_DEVICE, 106 .instance_size = sizeof(MchpPfSoCSysregState), 107 .class_init = mchp_pfsoc_sysreg_class_init, 108 }; 109 110 static void mchp_pfsoc_sysreg_register_types(void) 111 { 112 type_register_static(&mchp_pfsoc_sysreg_info); 113 } 114 115 type_init(mchp_pfsoc_sysreg_register_types) 116