1 /* 2 * QEMU PowerMac CUDA device support 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "hw/hw.h" 26 #include "hw/ppc/mac.h" 27 #include "hw/input/adb.h" 28 #include "qemu/timer.h" 29 #include "sysemu/sysemu.h" 30 31 /* XXX: implement all timer modes */ 32 33 /* debug CUDA */ 34 //#define DEBUG_CUDA 35 36 /* debug CUDA packets */ 37 //#define DEBUG_CUDA_PACKET 38 39 #ifdef DEBUG_CUDA 40 #define CUDA_DPRINTF(fmt, ...) \ 41 do { printf("CUDA: " fmt , ## __VA_ARGS__); } while (0) 42 #else 43 #define CUDA_DPRINTF(fmt, ...) 44 #endif 45 46 /* Bits in B data register: all active low */ 47 #define TREQ 0x08 /* Transfer request (input) */ 48 #define TACK 0x10 /* Transfer acknowledge (output) */ 49 #define TIP 0x20 /* Transfer in progress (output) */ 50 51 /* Bits in ACR */ 52 #define SR_CTRL 0x1c /* Shift register control bits */ 53 #define SR_EXT 0x0c /* Shift on external clock */ 54 #define SR_OUT 0x10 /* Shift out if 1 */ 55 56 /* Bits in IFR and IER */ 57 #define IER_SET 0x80 /* set bits in IER */ 58 #define IER_CLR 0 /* clear bits in IER */ 59 #define SR_INT 0x04 /* Shift register full/empty */ 60 #define SR_DATA_INT 0x08 61 #define SR_CLOCK_INT 0x10 62 #define T1_INT 0x40 /* Timer 1 interrupt */ 63 #define T2_INT 0x20 /* Timer 2 interrupt */ 64 65 /* Bits in ACR */ 66 #define T1MODE 0xc0 /* Timer 1 mode */ 67 #define T1MODE_CONT 0x40 /* continuous interrupts */ 68 69 /* commands (1st byte) */ 70 #define ADB_PACKET 0 71 #define CUDA_PACKET 1 72 #define ERROR_PACKET 2 73 #define TIMER_PACKET 3 74 #define POWER_PACKET 4 75 #define MACIIC_PACKET 5 76 #define PMU_PACKET 6 77 78 79 /* CUDA commands (2nd byte) */ 80 #define CUDA_WARM_START 0x0 81 #define CUDA_AUTOPOLL 0x1 82 #define CUDA_GET_6805_ADDR 0x2 83 #define CUDA_GET_TIME 0x3 84 #define CUDA_GET_PRAM 0x7 85 #define CUDA_SET_6805_ADDR 0x8 86 #define CUDA_SET_TIME 0x9 87 #define CUDA_POWERDOWN 0xa 88 #define CUDA_POWERUP_TIME 0xb 89 #define CUDA_SET_PRAM 0xc 90 #define CUDA_MS_RESET 0xd 91 #define CUDA_SEND_DFAC 0xe 92 #define CUDA_BATTERY_SWAP_SENSE 0x10 93 #define CUDA_RESET_SYSTEM 0x11 94 #define CUDA_SET_IPL 0x12 95 #define CUDA_FILE_SERVER_FLAG 0x13 96 #define CUDA_SET_AUTO_RATE 0x14 97 #define CUDA_GET_AUTO_RATE 0x16 98 #define CUDA_SET_DEVICE_LIST 0x19 99 #define CUDA_GET_DEVICE_LIST 0x1a 100 #define CUDA_SET_ONE_SECOND_MODE 0x1b 101 #define CUDA_SET_POWER_MESSAGES 0x21 102 #define CUDA_GET_SET_IIC 0x22 103 #define CUDA_WAKEUP 0x23 104 #define CUDA_TIMER_TICKLE 0x24 105 #define CUDA_COMBINED_FORMAT_IIC 0x25 106 107 #define CUDA_TIMER_FREQ (4700000 / 6) 108 #define CUDA_ADB_POLL_FREQ 50 109 110 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */ 111 #define RTC_OFFSET 2082844800 112 113 /* CUDA registers */ 114 #define CUDA_REG_B 0x00 115 #define CUDA_REG_A 0x01 116 #define CUDA_REG_DIRB 0x02 117 #define CUDA_REG_DIRA 0x03 118 #define CUDA_REG_T1CL 0x04 119 #define CUDA_REG_T1CH 0x05 120 #define CUDA_REG_T1LL 0x06 121 #define CUDA_REG_T1LH 0x07 122 #define CUDA_REG_T2CL 0x08 123 #define CUDA_REG_T2CH 0x09 124 #define CUDA_REG_SR 0x0a 125 #define CUDA_REG_ACR 0x0b 126 #define CUDA_REG_PCR 0x0c 127 #define CUDA_REG_IFR 0x0d 128 #define CUDA_REG_IER 0x0e 129 #define CUDA_REG_ANH 0x0f 130 131 static void cuda_update(CUDAState *s); 132 static void cuda_receive_packet_from_host(CUDAState *s, 133 const uint8_t *data, int len); 134 static void cuda_timer_update(CUDAState *s, CUDATimer *ti, 135 int64_t current_time); 136 137 static void cuda_update_irq(CUDAState *s) 138 { 139 if (s->ifr & s->ier & (SR_INT | T1_INT | T2_INT)) { 140 qemu_irq_raise(s->irq); 141 } else { 142 qemu_irq_lower(s->irq); 143 } 144 } 145 146 static uint64_t get_tb(uint64_t time, uint64_t freq) 147 { 148 return muldiv64(time, freq, get_ticks_per_sec()); 149 } 150 151 static unsigned int get_counter(CUDATimer *ti) 152 { 153 int64_t d; 154 unsigned int counter; 155 uint64_t tb_diff; 156 uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 157 158 /* Reverse of the tb calculation algorithm that Mac OS X uses on bootup. */ 159 tb_diff = get_tb(current_time, ti->frequency) - ti->load_time; 160 d = (tb_diff * 0xBF401675E5DULL) / (ti->frequency << 24); 161 162 if (ti->index == 0) { 163 /* the timer goes down from latch to -1 (period of latch + 2) */ 164 if (d <= (ti->counter_value + 1)) { 165 counter = (ti->counter_value - d) & 0xffff; 166 } else { 167 counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); 168 counter = (ti->latch - counter) & 0xffff; 169 } 170 } else { 171 counter = (ti->counter_value - d) & 0xffff; 172 } 173 return counter; 174 } 175 176 static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) 177 { 178 CUDA_DPRINTF("T%d.counter=%d\n", 1 + ti->index, val); 179 ti->load_time = get_tb(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 180 s->frequency); 181 ti->counter_value = val; 182 cuda_timer_update(s, ti, ti->load_time); 183 } 184 185 static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time) 186 { 187 int64_t d, next_time; 188 unsigned int counter; 189 190 /* current counter value */ 191 d = muldiv64(current_time - s->load_time, 192 CUDA_TIMER_FREQ, get_ticks_per_sec()); 193 /* the timer goes down from latch to -1 (period of latch + 2) */ 194 if (d <= (s->counter_value + 1)) { 195 counter = (s->counter_value - d) & 0xffff; 196 } else { 197 counter = (d - (s->counter_value + 1)) % (s->latch + 2); 198 counter = (s->latch - counter) & 0xffff; 199 } 200 201 /* Note: we consider the irq is raised on 0 */ 202 if (counter == 0xffff) { 203 next_time = d + s->latch + 1; 204 } else if (counter == 0) { 205 next_time = d + s->latch + 2; 206 } else { 207 next_time = d + counter; 208 } 209 CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n", 210 s->latch, d, next_time - d); 211 next_time = muldiv64(next_time, get_ticks_per_sec(), CUDA_TIMER_FREQ) + 212 s->load_time; 213 if (next_time <= current_time) 214 next_time = current_time + 1; 215 return next_time; 216 } 217 218 static void cuda_timer_update(CUDAState *s, CUDATimer *ti, 219 int64_t current_time) 220 { 221 if (!ti->timer) 222 return; 223 if (ti->index == 0 && (s->acr & T1MODE) != T1MODE_CONT) { 224 timer_del(ti->timer); 225 } else { 226 ti->next_irq_time = get_next_irq_time(ti, current_time); 227 timer_mod(ti->timer, ti->next_irq_time); 228 } 229 } 230 231 static void cuda_timer1(void *opaque) 232 { 233 CUDAState *s = opaque; 234 CUDATimer *ti = &s->timers[0]; 235 236 cuda_timer_update(s, ti, ti->next_irq_time); 237 s->ifr |= T1_INT; 238 cuda_update_irq(s); 239 } 240 241 static void cuda_timer2(void *opaque) 242 { 243 CUDAState *s = opaque; 244 CUDATimer *ti = &s->timers[1]; 245 246 cuda_timer_update(s, ti, ti->next_irq_time); 247 s->ifr |= T2_INT; 248 cuda_update_irq(s); 249 } 250 251 static uint32_t cuda_readb(void *opaque, hwaddr addr) 252 { 253 CUDAState *s = opaque; 254 uint32_t val; 255 256 addr = (addr >> 9) & 0xf; 257 switch(addr) { 258 case CUDA_REG_B: 259 val = s->b; 260 break; 261 case CUDA_REG_A: 262 val = s->a; 263 break; 264 case CUDA_REG_DIRB: 265 val = s->dirb; 266 break; 267 case CUDA_REG_DIRA: 268 val = s->dira; 269 break; 270 case CUDA_REG_T1CL: 271 val = get_counter(&s->timers[0]) & 0xff; 272 s->ifr &= ~T1_INT; 273 cuda_update_irq(s); 274 break; 275 case CUDA_REG_T1CH: 276 val = get_counter(&s->timers[0]) >> 8; 277 cuda_update_irq(s); 278 break; 279 case CUDA_REG_T1LL: 280 val = s->timers[0].latch & 0xff; 281 break; 282 case CUDA_REG_T1LH: 283 /* XXX: check this */ 284 val = (s->timers[0].latch >> 8) & 0xff; 285 break; 286 case CUDA_REG_T2CL: 287 val = get_counter(&s->timers[1]) & 0xff; 288 s->ifr &= ~T2_INT; 289 cuda_update_irq(s); 290 break; 291 case CUDA_REG_T2CH: 292 val = get_counter(&s->timers[1]) >> 8; 293 break; 294 case CUDA_REG_SR: 295 val = s->sr; 296 s->ifr &= ~(SR_INT | SR_CLOCK_INT | SR_DATA_INT); 297 cuda_update_irq(s); 298 break; 299 case CUDA_REG_ACR: 300 val = s->acr; 301 break; 302 case CUDA_REG_PCR: 303 val = s->pcr; 304 break; 305 case CUDA_REG_IFR: 306 val = s->ifr; 307 if (s->ifr & s->ier) { 308 val |= 0x80; 309 } 310 break; 311 case CUDA_REG_IER: 312 val = s->ier | 0x80; 313 break; 314 default: 315 case CUDA_REG_ANH: 316 val = s->anh; 317 break; 318 } 319 if (addr != CUDA_REG_IFR || val != 0) { 320 CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr, val); 321 } 322 323 return val; 324 } 325 326 static void cuda_writeb(void *opaque, hwaddr addr, uint32_t val) 327 { 328 CUDAState *s = opaque; 329 330 addr = (addr >> 9) & 0xf; 331 CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr, val); 332 333 switch(addr) { 334 case CUDA_REG_B: 335 s->b = val; 336 cuda_update(s); 337 break; 338 case CUDA_REG_A: 339 s->a = val; 340 break; 341 case CUDA_REG_DIRB: 342 s->dirb = val; 343 break; 344 case CUDA_REG_DIRA: 345 s->dira = val; 346 break; 347 case CUDA_REG_T1CL: 348 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; 349 cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 350 break; 351 case CUDA_REG_T1CH: 352 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); 353 s->ifr &= ~T1_INT; 354 set_counter(s, &s->timers[0], s->timers[0].latch); 355 break; 356 case CUDA_REG_T1LL: 357 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; 358 cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 359 break; 360 case CUDA_REG_T1LH: 361 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); 362 s->ifr &= ~T1_INT; 363 cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 364 break; 365 case CUDA_REG_T2CL: 366 s->timers[1].latch = (s->timers[1].latch & 0xff00) | val; 367 break; 368 case CUDA_REG_T2CH: 369 /* To ensure T2 generates an interrupt on zero crossing with the 370 common timer code, write the value directly from the latch to 371 the counter */ 372 s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8); 373 s->ifr &= ~T2_INT; 374 set_counter(s, &s->timers[1], s->timers[1].latch); 375 break; 376 case CUDA_REG_SR: 377 s->sr = val; 378 break; 379 case CUDA_REG_ACR: 380 s->acr = val; 381 cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 382 cuda_update(s); 383 break; 384 case CUDA_REG_PCR: 385 s->pcr = val; 386 break; 387 case CUDA_REG_IFR: 388 /* reset bits */ 389 s->ifr &= ~val; 390 cuda_update_irq(s); 391 break; 392 case CUDA_REG_IER: 393 if (val & IER_SET) { 394 /* set bits */ 395 s->ier |= val & 0x7f; 396 } else { 397 /* reset bits */ 398 s->ier &= ~val; 399 } 400 cuda_update_irq(s); 401 break; 402 default: 403 case CUDA_REG_ANH: 404 s->anh = val; 405 break; 406 } 407 } 408 409 /* NOTE: TIP and TREQ are negated */ 410 static void cuda_update(CUDAState *s) 411 { 412 int packet_received, len; 413 414 packet_received = 0; 415 if (!(s->b & TIP)) { 416 /* transfer requested from host */ 417 418 if (s->acr & SR_OUT) { 419 /* data output */ 420 if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { 421 if (s->data_out_index < sizeof(s->data_out)) { 422 CUDA_DPRINTF("send: %02x\n", s->sr); 423 s->data_out[s->data_out_index++] = s->sr; 424 s->ifr |= SR_INT; 425 cuda_update_irq(s); 426 } 427 } 428 } else { 429 if (s->data_in_index < s->data_in_size) { 430 /* data input */ 431 if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { 432 s->sr = s->data_in[s->data_in_index++]; 433 CUDA_DPRINTF("recv: %02x\n", s->sr); 434 /* indicate end of transfer */ 435 if (s->data_in_index >= s->data_in_size) { 436 s->b = (s->b | TREQ); 437 } 438 s->ifr |= SR_INT; 439 cuda_update_irq(s); 440 } 441 } 442 } 443 } else { 444 /* no transfer requested: handle sync case */ 445 if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) { 446 /* update TREQ state each time TACK change state */ 447 if (s->b & TACK) 448 s->b = (s->b | TREQ); 449 else 450 s->b = (s->b & ~TREQ); 451 s->ifr |= SR_INT; 452 cuda_update_irq(s); 453 } else { 454 if (!(s->last_b & TIP)) { 455 /* handle end of host to cuda transfer */ 456 packet_received = (s->data_out_index > 0); 457 /* always an IRQ at the end of transfer */ 458 s->ifr |= SR_INT; 459 cuda_update_irq(s); 460 } 461 /* signal if there is data to read */ 462 if (s->data_in_index < s->data_in_size) { 463 s->b = (s->b & ~TREQ); 464 } 465 } 466 } 467 468 s->last_acr = s->acr; 469 s->last_b = s->b; 470 471 /* NOTE: cuda_receive_packet_from_host() can call cuda_update() 472 recursively */ 473 if (packet_received) { 474 len = s->data_out_index; 475 s->data_out_index = 0; 476 cuda_receive_packet_from_host(s, s->data_out, len); 477 } 478 } 479 480 static void cuda_send_packet_to_host(CUDAState *s, 481 const uint8_t *data, int len) 482 { 483 #ifdef DEBUG_CUDA_PACKET 484 { 485 int i; 486 printf("cuda_send_packet_to_host:\n"); 487 for(i = 0; i < len; i++) 488 printf(" %02x", data[i]); 489 printf("\n"); 490 } 491 #endif 492 memcpy(s->data_in, data, len); 493 s->data_in_size = len; 494 s->data_in_index = 0; 495 cuda_update(s); 496 s->ifr |= SR_INT; 497 cuda_update_irq(s); 498 } 499 500 static void cuda_adb_poll(void *opaque) 501 { 502 CUDAState *s = opaque; 503 uint8_t obuf[ADB_MAX_OUT_LEN + 2]; 504 int olen; 505 506 olen = adb_poll(&s->adb_bus, obuf + 2); 507 if (olen > 0) { 508 obuf[0] = ADB_PACKET; 509 obuf[1] = 0x40; /* polled data */ 510 cuda_send_packet_to_host(s, obuf, olen + 2); 511 } 512 timer_mod(s->adb_poll_timer, 513 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 514 (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ)); 515 } 516 517 static void cuda_receive_packet(CUDAState *s, 518 const uint8_t *data, int len) 519 { 520 uint8_t obuf[16] = { CUDA_PACKET, 0, data[0] }; 521 int autopoll; 522 uint32_t ti; 523 524 switch(data[0]) { 525 case CUDA_AUTOPOLL: 526 autopoll = (data[1] != 0); 527 if (autopoll != s->autopoll) { 528 s->autopoll = autopoll; 529 if (autopoll) { 530 timer_mod(s->adb_poll_timer, 531 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 532 (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ)); 533 } else { 534 timer_del(s->adb_poll_timer); 535 } 536 } 537 cuda_send_packet_to_host(s, obuf, 3); 538 break; 539 case CUDA_GET_6805_ADDR: 540 cuda_send_packet_to_host(s, obuf, 3); 541 break; 542 case CUDA_SET_TIME: 543 ti = (((uint32_t)data[1]) << 24) + (((uint32_t)data[2]) << 16) + (((uint32_t)data[3]) << 8) + data[4]; 544 s->tick_offset = ti - (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / get_ticks_per_sec()); 545 cuda_send_packet_to_host(s, obuf, 3); 546 break; 547 case CUDA_GET_TIME: 548 ti = s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / get_ticks_per_sec()); 549 obuf[3] = ti >> 24; 550 obuf[4] = ti >> 16; 551 obuf[5] = ti >> 8; 552 obuf[6] = ti; 553 cuda_send_packet_to_host(s, obuf, 7); 554 break; 555 case CUDA_FILE_SERVER_FLAG: 556 case CUDA_SET_DEVICE_LIST: 557 case CUDA_SET_AUTO_RATE: 558 case CUDA_SET_POWER_MESSAGES: 559 cuda_send_packet_to_host(s, obuf, 3); 560 break; 561 case CUDA_POWERDOWN: 562 cuda_send_packet_to_host(s, obuf, 3); 563 qemu_system_shutdown_request(); 564 break; 565 case CUDA_RESET_SYSTEM: 566 cuda_send_packet_to_host(s, obuf, 3); 567 qemu_system_reset_request(); 568 break; 569 case CUDA_COMBINED_FORMAT_IIC: 570 obuf[0] = ERROR_PACKET; 571 obuf[1] = 0x5; 572 obuf[2] = CUDA_PACKET; 573 obuf[3] = data[0]; 574 cuda_send_packet_to_host(s, obuf, 4); 575 break; 576 case CUDA_GET_SET_IIC: 577 if (len == 4) { 578 cuda_send_packet_to_host(s, obuf, 3); 579 } else { 580 obuf[0] = ERROR_PACKET; 581 obuf[1] = 0x2; 582 obuf[2] = CUDA_PACKET; 583 obuf[3] = data[0]; 584 cuda_send_packet_to_host(s, obuf, 4); 585 } 586 break; 587 default: 588 break; 589 } 590 } 591 592 static void cuda_receive_packet_from_host(CUDAState *s, 593 const uint8_t *data, int len) 594 { 595 #ifdef DEBUG_CUDA_PACKET 596 { 597 int i; 598 printf("cuda_receive_packet_from_host:\n"); 599 for(i = 0; i < len; i++) 600 printf(" %02x", data[i]); 601 printf("\n"); 602 } 603 #endif 604 switch(data[0]) { 605 case ADB_PACKET: 606 { 607 uint8_t obuf[ADB_MAX_OUT_LEN + 3]; 608 int olen; 609 olen = adb_request(&s->adb_bus, obuf + 2, data + 1, len - 1); 610 if (olen > 0) { 611 obuf[0] = ADB_PACKET; 612 obuf[1] = 0x00; 613 cuda_send_packet_to_host(s, obuf, olen + 2); 614 } else { 615 /* error */ 616 obuf[0] = ADB_PACKET; 617 obuf[1] = -olen; 618 obuf[2] = data[1]; 619 olen = 0; 620 cuda_send_packet_to_host(s, obuf, olen + 3); 621 } 622 } 623 break; 624 case CUDA_PACKET: 625 cuda_receive_packet(s, data + 1, len - 1); 626 break; 627 } 628 } 629 630 static void cuda_writew (void *opaque, hwaddr addr, uint32_t value) 631 { 632 } 633 634 static void cuda_writel (void *opaque, hwaddr addr, uint32_t value) 635 { 636 } 637 638 static uint32_t cuda_readw (void *opaque, hwaddr addr) 639 { 640 return 0; 641 } 642 643 static uint32_t cuda_readl (void *opaque, hwaddr addr) 644 { 645 return 0; 646 } 647 648 static const MemoryRegionOps cuda_ops = { 649 .old_mmio = { 650 .write = { 651 cuda_writeb, 652 cuda_writew, 653 cuda_writel, 654 }, 655 .read = { 656 cuda_readb, 657 cuda_readw, 658 cuda_readl, 659 }, 660 }, 661 .endianness = DEVICE_NATIVE_ENDIAN, 662 }; 663 664 static bool cuda_timer_exist(void *opaque, int version_id) 665 { 666 CUDATimer *s = opaque; 667 668 return s->timer != NULL; 669 } 670 671 static const VMStateDescription vmstate_cuda_timer = { 672 .name = "cuda_timer", 673 .version_id = 0, 674 .minimum_version_id = 0, 675 .fields = (VMStateField[]) { 676 VMSTATE_UINT16(latch, CUDATimer), 677 VMSTATE_UINT16(counter_value, CUDATimer), 678 VMSTATE_INT64(load_time, CUDATimer), 679 VMSTATE_INT64(next_irq_time, CUDATimer), 680 VMSTATE_TIMER_PTR_TEST(timer, CUDATimer, cuda_timer_exist), 681 VMSTATE_END_OF_LIST() 682 } 683 }; 684 685 static const VMStateDescription vmstate_cuda = { 686 .name = "cuda", 687 .version_id = 2, 688 .minimum_version_id = 2, 689 .fields = (VMStateField[]) { 690 VMSTATE_UINT8(a, CUDAState), 691 VMSTATE_UINT8(b, CUDAState), 692 VMSTATE_UINT8(dira, CUDAState), 693 VMSTATE_UINT8(dirb, CUDAState), 694 VMSTATE_UINT8(sr, CUDAState), 695 VMSTATE_UINT8(acr, CUDAState), 696 VMSTATE_UINT8(pcr, CUDAState), 697 VMSTATE_UINT8(ifr, CUDAState), 698 VMSTATE_UINT8(ier, CUDAState), 699 VMSTATE_UINT8(anh, CUDAState), 700 VMSTATE_INT32(data_in_size, CUDAState), 701 VMSTATE_INT32(data_in_index, CUDAState), 702 VMSTATE_INT32(data_out_index, CUDAState), 703 VMSTATE_UINT8(autopoll, CUDAState), 704 VMSTATE_BUFFER(data_in, CUDAState), 705 VMSTATE_BUFFER(data_out, CUDAState), 706 VMSTATE_UINT32(tick_offset, CUDAState), 707 VMSTATE_STRUCT_ARRAY(timers, CUDAState, 2, 1, 708 vmstate_cuda_timer, CUDATimer), 709 VMSTATE_TIMER_PTR(adb_poll_timer, CUDAState), 710 VMSTATE_END_OF_LIST() 711 } 712 }; 713 714 static void cuda_reset(DeviceState *dev) 715 { 716 CUDAState *s = CUDA(dev); 717 718 s->b = 0; 719 s->a = 0; 720 s->dirb = 0; 721 s->dira = 0; 722 s->sr = 0; 723 s->acr = 0; 724 s->pcr = 0; 725 s->ifr = 0; 726 s->ier = 0; 727 // s->ier = T1_INT | SR_INT; 728 s->anh = 0; 729 s->data_in_size = 0; 730 s->data_in_index = 0; 731 s->data_out_index = 0; 732 s->autopoll = 0; 733 734 s->timers[0].latch = 0xffff; 735 set_counter(s, &s->timers[0], 0xffff); 736 737 s->timers[1].latch = 0xffff; 738 } 739 740 static void cuda_realizefn(DeviceState *dev, Error **errp) 741 { 742 CUDAState *s = CUDA(dev); 743 struct tm tm; 744 745 s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer1, s); 746 s->timers[0].frequency = s->frequency; 747 s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer2, s); 748 s->timers[1].frequency = (SCALE_US * 6000) / 4700; 749 750 qemu_get_timedate(&tm, 0); 751 s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; 752 753 s->adb_poll_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_adb_poll, s); 754 } 755 756 static void cuda_initfn(Object *obj) 757 { 758 SysBusDevice *d = SYS_BUS_DEVICE(obj); 759 CUDAState *s = CUDA(obj); 760 int i; 761 762 memory_region_init_io(&s->mem, obj, &cuda_ops, s, "cuda", 0x2000); 763 sysbus_init_mmio(d, &s->mem); 764 sysbus_init_irq(d, &s->irq); 765 766 for (i = 0; i < ARRAY_SIZE(s->timers); i++) { 767 s->timers[i].index = i; 768 } 769 770 qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, 771 DEVICE(obj), "adb.0"); 772 } 773 774 static Property cuda_properties[] = { 775 DEFINE_PROP_UINT64("frequency", CUDAState, frequency, 0), 776 DEFINE_PROP_END_OF_LIST() 777 }; 778 779 static void cuda_class_init(ObjectClass *oc, void *data) 780 { 781 DeviceClass *dc = DEVICE_CLASS(oc); 782 783 dc->realize = cuda_realizefn; 784 dc->reset = cuda_reset; 785 dc->vmsd = &vmstate_cuda; 786 dc->props = cuda_properties; 787 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 788 } 789 790 static const TypeInfo cuda_type_info = { 791 .name = TYPE_CUDA, 792 .parent = TYPE_SYS_BUS_DEVICE, 793 .instance_size = sizeof(CUDAState), 794 .instance_init = cuda_initfn, 795 .class_init = cuda_class_init, 796 }; 797 798 static void cuda_register_types(void) 799 { 800 type_register_static(&cuda_type_info); 801 } 802 803 type_init(cuda_register_types) 804