1 /* 2 * QEMU m68k Macintosh VIA device support 3 * 4 * Copyright (c) 2011-2018 Laurent Vivier 5 * Copyright (c) 2018 Mark Cave-Ayland 6 * 7 * Some parts from hw/misc/macio/cuda.c 8 * 9 * Copyright (c) 2004-2007 Fabrice Bellard 10 * Copyright (c) 2007 Jocelyn Mayer 11 * 12 * some parts from linux-2.6.29, arch/m68k/include/asm/mac_via.h 13 * 14 * This work is licensed under the terms of the GNU GPL, version 2 or later. 15 * See the COPYING file in the top-level directory. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "migration/vmstate.h" 20 #include "hw/sysbus.h" 21 #include "hw/irq.h" 22 #include "qemu/timer.h" 23 #include "hw/misc/mac_via.h" 24 #include "hw/misc/mos6522.h" 25 #include "hw/input/adb.h" 26 #include "sysemu/runstate.h" 27 #include "qapi/error.h" 28 #include "qemu/cutils.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/qdev-properties-system.h" 31 #include "sysemu/block-backend.h" 32 #include "sysemu/rtc.h" 33 #include "trace.h" 34 #include "qemu/log.h" 35 36 /* 37 * VIAs: There are two in every machine 38 */ 39 40 /* 41 * Not all of these are true post MacII I think. 42 * CSA: probably the ones CHRP marks as 'unused' change purposes 43 * when the IWM becomes the SWIM. 44 * http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html 45 * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf 46 * 47 * also, http://developer.apple.com/technotes/hw/hw_09.html claims the 48 * following changes for IIfx: 49 * VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP. 50 * Also, "All of the functionality of VIA2 has been moved to other chips". 51 */ 52 53 #define VIA1A_vSccWrReq 0x80 /* 54 * SCC write. (input) 55 * [CHRP] SCC WREQ: Reflects the state of the 56 * Wait/Request pins from the SCC. 57 * [Macintosh Family Hardware] 58 * as CHRP on SE/30,II,IIx,IIcx,IIci. 59 * on IIfx, "0 means an active request" 60 */ 61 #define VIA1A_vRev8 0x40 /* 62 * Revision 8 board ??? 63 * [CHRP] En WaitReqB: Lets the WaitReq_L 64 * signal from port B of the SCC appear on 65 * the PA7 input pin. Output. 66 * [Macintosh Family] On the SE/30, this 67 * is the bit to flip screen buffers. 68 * 0=alternate, 1=main. 69 * on II,IIx,IIcx,IIci,IIfx this is a bit 70 * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx 71 */ 72 #define VIA1A_vHeadSel 0x20 /* 73 * Head select for IWM. 74 * [CHRP] unused. 75 * [Macintosh Family] "Floppy disk 76 * state-control line SEL" on all but IIfx 77 */ 78 #define VIA1A_vOverlay 0x10 /* 79 * [Macintosh Family] On SE/30,II,IIx,IIcx 80 * this bit enables the "Overlay" address 81 * map in the address decoders as it is on 82 * reset for mapping the ROM over the reset 83 * vector. 1=use overlay map. 84 * On the IIci,IIfx it is another bit of the 85 * CPU ID: 0=normal IIci, 1=IIci with parity 86 * feature or IIfx. 87 * [CHRP] En WaitReqA: Lets the WaitReq_L 88 * signal from port A of the SCC appear 89 * on the PA7 input pin (CHRP). Output. 90 * [MkLinux] "Drive Select" 91 * (with 0x20 being 'disk head select') 92 */ 93 #define VIA1A_vSync 0x08 /* 94 * [CHRP] Sync Modem: modem clock select: 95 * 1: select the external serial clock to 96 * drive the SCC's /RTxCA pin. 97 * 0: Select the 3.6864MHz clock to drive 98 * the SCC cell. 99 * [Macintosh Family] Correct on all but IIfx 100 */ 101 102 /* 103 * Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control 104 * on Macs which had the PWM sound hardware. Reserved on newer models. 105 * On IIci,IIfx, bits 1-2 are the rest of the CPU ID: 106 * bit 2: 1=IIci, 0=IIfx 107 * bit 1: 1 on both IIci and IIfx. 108 * MkLinux sez bit 0 is 'burnin flag' in this case. 109 * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as 110 * inputs, these bits will read 0. 111 */ 112 #define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */ 113 #define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */ 114 #define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */ 115 #define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */ 116 #define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */ 117 118 /* 119 * Info on VIA1B is from Macintosh Family Hardware & MkLinux. 120 * CHRP offers no info. 121 */ 122 #define VIA1B_vSound 0x80 /* 123 * Sound enable (for compatibility with 124 * PWM hardware) 0=enabled. 125 * Also, on IIci w/parity, shows parity error 126 * 0=error, 1=OK. 127 */ 128 #define VIA1B_vMystery 0x40 /* 129 * On IIci, parity enable. 0=enabled,1=disabled 130 * On SE/30, vertical sync interrupt enable. 131 * 0=enabled. This vSync interrupt shows up 132 * as a slot $E interrupt. 133 * On Quadra 800 this bit toggles A/UX mode which 134 * configures the glue logic to deliver some IRQs 135 * at different levels compared to a classic 136 * Mac. 137 */ 138 #define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */ 139 #define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */ 140 #define VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/ 141 #define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */ 142 #define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */ 143 #define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */ 144 145 /* 146 * VIA2 A register is the interrupt lines raised off the nubus 147 * slots. 148 * The below info is from 'Macintosh Family Hardware.' 149 * MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.' 150 * It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and 151 * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike. 152 * Perhaps OSS uses vRAM1 and vRAM2 for ADB. 153 */ 154 155 #define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */ 156 #define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */ 157 #define VIA2A_vIRQE 0x20 /* IRQ from slot $E */ 158 #define VIA2A_vIRQD 0x10 /* IRQ from slot $D */ 159 #define VIA2A_vIRQC 0x08 /* IRQ from slot $C */ 160 #define VIA2A_vIRQB 0x04 /* IRQ from slot $B */ 161 #define VIA2A_vIRQA 0x02 /* IRQ from slot $A */ 162 #define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */ 163 164 /* 165 * RAM size bits decoded as follows: 166 * bit1 bit0 size of ICs in bank A 167 * 0 0 256 kbit 168 * 0 1 1 Mbit 169 * 1 0 4 Mbit 170 * 1 1 16 Mbit 171 */ 172 173 /* 174 * Register B has the fun stuff in it 175 */ 176 177 #define VIA2B_vVBL 0x80 /* 178 * VBL output to VIA1 (60.15Hz) driven by 179 * timer T1. 180 * on IIci, parity test: 0=test mode. 181 * [MkLinux] RBV_PARODD: 1=odd,0=even. 182 */ 183 #define VIA2B_vSndJck 0x40 /* 184 * External sound jack status. 185 * 0=plug is inserted. On SE/30, always 0 186 */ 187 #define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */ 188 #define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */ 189 #define VIA2B_vMode32 0x08 /* 190 * 24/32bit switch - doubles as cache flush 191 * on II, AMU/PMMU control. 192 * if AMU, 0=24bit to 32bit translation 193 * if PMMU, 1=PMMU is accessing page table. 194 * on SE/30 tied low. 195 * on IIx,IIcx,IIfx, unused. 196 * on IIci/RBV, cache control. 0=flush cache. 197 */ 198 #define VIA2B_vPower 0x04 /* 199 * Power off, 0=shut off power. 200 * on SE/30 this signal sent to PDS card. 201 */ 202 #define VIA2B_vBusLk 0x02 /* 203 * Lock NuBus transactions, 0=locked. 204 * on SE/30 sent to PDS card. 205 */ 206 #define VIA2B_vCDis 0x01 /* 207 * Cache control. On IIci, 1=disable cache card 208 * on others, 0=disable processor's instruction 209 * and data caches. 210 */ 211 212 /* interrupt flags */ 213 214 #define IRQ_SET 0x80 215 216 /* common */ 217 218 #define VIA_IRQ_TIMER1 0x40 219 #define VIA_IRQ_TIMER2 0x20 220 221 /* 222 * Apple sez: http://developer.apple.com/technotes/ov/ov_04.html 223 * Another example of a valid function that has no ROM support is the use 224 * of the alternate video page for page-flipping animation. Since there 225 * is no ROM call to flip pages, it is necessary to go play with the 226 * right bit in the VIA chip (6522 Versatile Interface Adapter). 227 * [CSA: don't know which one this is, but it's one of 'em!] 228 */ 229 230 /* 231 * 6522 registers - see databook. 232 * CSA: Assignments for VIA1 confirmed from CHRP spec. 233 */ 234 235 /* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */ 236 /* Note: 15 VIA regs, 8 RBV regs */ 237 238 #define vBufB 0x0000 /* [VIA/RBV] Register B */ 239 #define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */ 240 #define vDirB 0x0400 /* [VIA only] Data Direction Register B. */ 241 #define vDirA 0x0600 /* [VIA only] Data Direction Register A. */ 242 #define vT1CL 0x0800 /* [VIA only] Timer one counter low. */ 243 #define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */ 244 #define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */ 245 #define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */ 246 #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ 247 #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ 248 #define vSR 0x1400 /* [VIA only] Shift register. */ 249 #define vACR 0x1600 /* [VIA only] Auxilary control register. */ 250 #define vPCR 0x1800 /* [VIA only] Peripheral control register. */ 251 /* 252 * CHRP sez never ever to *write* this. 253 * Mac family says never to *change* this. 254 * In fact we need to initialize it once at start. 255 */ 256 #define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */ 257 #define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */ 258 #define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */ 259 260 /* from linux 2.6 drivers/macintosh/via-macii.c */ 261 262 /* Bits in ACR */ 263 264 #define VIA1ACR_vShiftCtrl 0x1c /* Shift register control bits */ 265 #define VIA1ACR_vShiftExtClk 0x0c /* Shift on external clock */ 266 #define VIA1ACR_vShiftOut 0x10 /* Shift out if 1 */ 267 268 /* 269 * Apple Macintosh Family Hardware Refenece 270 * Table 19-10 ADB transaction states 271 */ 272 273 #define ADB_STATE_NEW 0 274 #define ADB_STATE_EVEN 1 275 #define ADB_STATE_ODD 2 276 #define ADB_STATE_IDLE 3 277 278 #define VIA1B_vADB_StateMask (VIA1B_vADBS1 | VIA1B_vADBS2) 279 #define VIA1B_vADB_StateShift 4 280 281 #define VIA_TIMER_FREQ (783360) 282 #define VIA_ADB_POLL_FREQ 50 /* XXX: not real */ 283 284 /* 285 * Guide to the Macintosh Family Hardware ch. 12 "Displays" p. 401 gives the 286 * precise 60Hz interrupt frequency as ~60.15Hz with a period of 16625.8 us 287 */ 288 #define VIA_60HZ_TIMER_PERIOD_NS 16625800 289 290 /* VIA returns time offset from Jan 1, 1904, not 1970 */ 291 #define RTC_OFFSET 2082844800 292 293 enum { 294 REG_0, 295 REG_1, 296 REG_2, 297 REG_3, 298 REG_TEST, 299 REG_WPROTECT, 300 REG_PRAM_ADDR, 301 REG_PRAM_ADDR_LAST = REG_PRAM_ADDR + 19, 302 REG_PRAM_SECT, 303 REG_PRAM_SECT_LAST = REG_PRAM_SECT + 7, 304 REG_INVALID, 305 REG_EMPTY = 0xff, 306 }; 307 308 static void via1_sixty_hz_update(MOS6522Q800VIA1State *v1s) 309 { 310 /* 60 Hz irq */ 311 v1s->next_sixty_hz = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 312 VIA_60HZ_TIMER_PERIOD_NS) / 313 VIA_60HZ_TIMER_PERIOD_NS * VIA_60HZ_TIMER_PERIOD_NS; 314 timer_mod(v1s->sixty_hz_timer, v1s->next_sixty_hz); 315 } 316 317 static void via1_one_second_update(MOS6522Q800VIA1State *v1s) 318 { 319 v1s->next_second = (qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000) / 320 1000 * 1000; 321 timer_mod(v1s->one_second_timer, v1s->next_second); 322 } 323 324 static void via1_sixty_hz(void *opaque) 325 { 326 MOS6522Q800VIA1State *v1s = opaque; 327 MOS6522State *s = MOS6522(v1s); 328 qemu_irq irq = qdev_get_gpio_in(DEVICE(s), VIA1_IRQ_60HZ_BIT); 329 330 qemu_set_irq(irq, 1); 331 332 via1_sixty_hz_update(v1s); 333 } 334 335 static void via1_one_second(void *opaque) 336 { 337 MOS6522Q800VIA1State *v1s = opaque; 338 MOS6522State *s = MOS6522(v1s); 339 qemu_irq irq = qdev_get_gpio_in(DEVICE(s), VIA1_IRQ_ONE_SECOND_BIT); 340 341 qemu_set_irq(irq, 1); 342 343 via1_one_second_update(v1s); 344 } 345 346 347 static void pram_update(MOS6522Q800VIA1State *v1s) 348 { 349 if (v1s->blk) { 350 if (blk_pwrite(v1s->blk, 0, v1s->PRAM, sizeof(v1s->PRAM), 0) < 0) { 351 qemu_log("pram_update: cannot write to file\n"); 352 } 353 } 354 } 355 356 /* 357 * RTC Commands 358 * 359 * Command byte Register addressed by the command 360 * 361 * z0000001 Seconds register 0 (lowest-order byte) 362 * z0000101 Seconds register 1 363 * z0001001 Seconds register 2 364 * z0001101 Seconds register 3 (highest-order byte) 365 * 00110001 Test register (write-only) 366 * 00110101 Write-Protect Register (write-only) 367 * z010aa01 RAM address 100aa ($10-$13) (first 20 bytes only) 368 * z1aaaa01 RAM address 0aaaa ($00-$0F) (first 20 bytes only) 369 * z0111aaa Extended memory designator and sector number 370 * 371 * For a read request, z=1, for a write z=0 372 * The letter a indicates bits whose value depend on what parameter 373 * RAM byte you want to address 374 */ 375 static int via1_rtc_compact_cmd(uint8_t value) 376 { 377 uint8_t read = value & 0x80; 378 379 value &= 0x7f; 380 381 /* the last 2 bits of a command byte must always be 0b01 ... */ 382 if ((value & 0x78) == 0x38) { 383 /* except for the extended memory designator */ 384 return read | (REG_PRAM_SECT + (value & 0x07)); 385 } 386 if ((value & 0x03) == 0x01) { 387 value >>= 2; 388 if ((value & 0x1c) == 0) { 389 /* seconds registers */ 390 return read | (REG_0 + (value & 0x03)); 391 } else if ((value == 0x0c) && !read) { 392 return REG_TEST; 393 } else if ((value == 0x0d) && !read) { 394 return REG_WPROTECT; 395 } else if ((value & 0x1c) == 0x08) { 396 /* RAM address 0x10 to 0x13 */ 397 return read | (REG_PRAM_ADDR + 0x10 + (value & 0x03)); 398 } else if ((value & 0x43) == 0x41) { 399 /* RAM address 0x00 to 0x0f */ 400 return read | (REG_PRAM_ADDR + (value & 0x0f)); 401 } 402 } 403 return REG_INVALID; 404 } 405 406 static void via1_rtc_update(MOS6522Q800VIA1State *v1s) 407 { 408 MOS6522State *s = MOS6522(v1s); 409 int cmd, sector, addr; 410 uint32_t time; 411 412 if (s->b & VIA1B_vRTCEnb) { 413 return; 414 } 415 416 if (s->dirb & VIA1B_vRTCData) { 417 /* send bits to the RTC */ 418 if (!(v1s->last_b & VIA1B_vRTCClk) && (s->b & VIA1B_vRTCClk)) { 419 v1s->data_out <<= 1; 420 v1s->data_out |= s->b & VIA1B_vRTCData; 421 v1s->data_out_cnt++; 422 } 423 trace_via1_rtc_update_data_out(v1s->data_out_cnt, v1s->data_out); 424 } else { 425 trace_via1_rtc_update_data_in(v1s->data_in_cnt, v1s->data_in); 426 /* receive bits from the RTC */ 427 if ((v1s->last_b & VIA1B_vRTCClk) && 428 !(s->b & VIA1B_vRTCClk) && 429 v1s->data_in_cnt) { 430 s->b = (s->b & ~VIA1B_vRTCData) | 431 ((v1s->data_in >> 7) & VIA1B_vRTCData); 432 v1s->data_in <<= 1; 433 v1s->data_in_cnt--; 434 } 435 return; 436 } 437 438 if (v1s->data_out_cnt != 8) { 439 return; 440 } 441 442 v1s->data_out_cnt = 0; 443 444 trace_via1_rtc_internal_status(v1s->cmd, v1s->alt, v1s->data_out); 445 /* first byte: it's a command */ 446 if (v1s->cmd == REG_EMPTY) { 447 448 cmd = via1_rtc_compact_cmd(v1s->data_out); 449 trace_via1_rtc_internal_cmd(cmd); 450 451 if (cmd == REG_INVALID) { 452 trace_via1_rtc_cmd_invalid(v1s->data_out); 453 return; 454 } 455 456 if (cmd & 0x80) { /* this is a read command */ 457 switch (cmd & 0x7f) { 458 case REG_0...REG_3: /* seconds registers */ 459 /* 460 * register 0 is lowest-order byte 461 * register 3 is highest-order byte 462 */ 463 464 time = v1s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 465 / NANOSECONDS_PER_SECOND); 466 trace_via1_rtc_internal_time(time); 467 v1s->data_in = (time >> ((cmd & 0x03) << 3)) & 0xff; 468 v1s->data_in_cnt = 8; 469 trace_via1_rtc_cmd_seconds_read((cmd & 0x7f) - REG_0, 470 v1s->data_in); 471 break; 472 case REG_PRAM_ADDR...REG_PRAM_ADDR_LAST: 473 /* PRAM address 0x00 -> 0x13 */ 474 v1s->data_in = v1s->PRAM[(cmd & 0x7f) - REG_PRAM_ADDR]; 475 v1s->data_in_cnt = 8; 476 trace_via1_rtc_cmd_pram_read((cmd & 0x7f) - REG_PRAM_ADDR, 477 v1s->data_in); 478 break; 479 case REG_PRAM_SECT...REG_PRAM_SECT_LAST: 480 /* 481 * extended memory designator and sector number 482 * the only two-byte read command 483 */ 484 trace_via1_rtc_internal_set_cmd(cmd); 485 v1s->cmd = cmd; 486 break; 487 default: 488 g_assert_not_reached(); 489 break; 490 } 491 return; 492 } 493 494 /* this is a write command, needs a parameter */ 495 if (cmd == REG_WPROTECT || !v1s->wprotect) { 496 trace_via1_rtc_internal_set_cmd(cmd); 497 v1s->cmd = cmd; 498 } else { 499 trace_via1_rtc_internal_ignore_cmd(cmd); 500 } 501 return; 502 } 503 504 /* second byte: it's a parameter */ 505 if (v1s->alt == REG_EMPTY) { 506 switch (v1s->cmd & 0x7f) { 507 case REG_0...REG_3: /* seconds register */ 508 /* FIXME */ 509 trace_via1_rtc_cmd_seconds_write(v1s->cmd - REG_0, v1s->data_out); 510 v1s->cmd = REG_EMPTY; 511 break; 512 case REG_TEST: 513 /* device control: nothing to do */ 514 trace_via1_rtc_cmd_test_write(v1s->data_out); 515 v1s->cmd = REG_EMPTY; 516 break; 517 case REG_WPROTECT: 518 /* Write Protect register */ 519 trace_via1_rtc_cmd_wprotect_write(v1s->data_out); 520 v1s->wprotect = !!(v1s->data_out & 0x80); 521 v1s->cmd = REG_EMPTY; 522 break; 523 case REG_PRAM_ADDR...REG_PRAM_ADDR_LAST: 524 /* PRAM address 0x00 -> 0x13 */ 525 trace_via1_rtc_cmd_pram_write(v1s->cmd - REG_PRAM_ADDR, 526 v1s->data_out); 527 v1s->PRAM[v1s->cmd - REG_PRAM_ADDR] = v1s->data_out; 528 pram_update(v1s); 529 v1s->cmd = REG_EMPTY; 530 break; 531 case REG_PRAM_SECT...REG_PRAM_SECT_LAST: 532 addr = (v1s->data_out >> 2) & 0x1f; 533 sector = (v1s->cmd & 0x7f) - REG_PRAM_SECT; 534 if (v1s->cmd & 0x80) { 535 /* it's a read */ 536 v1s->data_in = v1s->PRAM[sector * 32 + addr]; 537 v1s->data_in_cnt = 8; 538 trace_via1_rtc_cmd_pram_sect_read(sector, addr, 539 sector * 32 + addr, 540 v1s->data_in); 541 v1s->cmd = REG_EMPTY; 542 } else { 543 /* it's a write, we need one more parameter */ 544 trace_via1_rtc_internal_set_alt(addr, sector, addr); 545 v1s->alt = addr; 546 } 547 break; 548 default: 549 g_assert_not_reached(); 550 break; 551 } 552 return; 553 } 554 555 /* third byte: it's the data of a REG_PRAM_SECT write */ 556 g_assert(REG_PRAM_SECT <= v1s->cmd && v1s->cmd <= REG_PRAM_SECT_LAST); 557 sector = v1s->cmd - REG_PRAM_SECT; 558 v1s->PRAM[sector * 32 + v1s->alt] = v1s->data_out; 559 pram_update(v1s); 560 trace_via1_rtc_cmd_pram_sect_write(sector, v1s->alt, sector * 32 + v1s->alt, 561 v1s->data_out); 562 v1s->alt = REG_EMPTY; 563 v1s->cmd = REG_EMPTY; 564 } 565 566 static void adb_via_poll(void *opaque) 567 { 568 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 569 MOS6522State *s = MOS6522(v1s); 570 ADBBusState *adb_bus = &v1s->adb_bus; 571 uint8_t obuf[9]; 572 uint8_t *data = &s->sr; 573 int olen; 574 575 /* 576 * Setting vADBInt below indicates that an autopoll reply has been 577 * received, however we must block autopoll until the point where 578 * the entire reply has been read back to the host 579 */ 580 adb_autopoll_block(adb_bus); 581 582 if (v1s->adb_data_in_size > 0 && v1s->adb_data_in_index == 0) { 583 /* 584 * For older Linux kernels that switch to IDLE mode after sending the 585 * ADB command, detect if there is an existing response and return that 586 * as a a "fake" autopoll reply or bus timeout accordingly 587 */ 588 *data = v1s->adb_data_out[0]; 589 olen = v1s->adb_data_in_size; 590 591 s->b &= ~VIA1B_vADBInt; 592 qemu_irq_raise(v1s->adb_data_ready); 593 } else { 594 /* 595 * Otherwise poll as normal 596 */ 597 v1s->adb_data_in_index = 0; 598 v1s->adb_data_out_index = 0; 599 olen = adb_poll(adb_bus, obuf, adb_bus->autopoll_mask); 600 601 if (olen > 0) { 602 /* Autopoll response */ 603 *data = obuf[0]; 604 olen--; 605 memcpy(v1s->adb_data_in, &obuf[1], olen); 606 v1s->adb_data_in_size = olen; 607 608 s->b &= ~VIA1B_vADBInt; 609 qemu_irq_raise(v1s->adb_data_ready); 610 } else { 611 *data = v1s->adb_autopoll_cmd; 612 obuf[0] = 0xff; 613 obuf[1] = 0xff; 614 olen = 2; 615 616 memcpy(v1s->adb_data_in, obuf, olen); 617 v1s->adb_data_in_size = olen; 618 619 s->b &= ~VIA1B_vADBInt; 620 qemu_irq_raise(v1s->adb_data_ready); 621 } 622 } 623 624 trace_via1_adb_poll(*data, (s->b & VIA1B_vADBInt) ? "+" : "-", 625 adb_bus->status, v1s->adb_data_in_index, olen); 626 } 627 628 static int adb_via_send_len(uint8_t data) 629 { 630 /* Determine the send length from the given ADB command */ 631 uint8_t cmd = data & 0xc; 632 uint8_t reg = data & 0x3; 633 634 switch (cmd) { 635 case 0x8: 636 /* Listen command */ 637 switch (reg) { 638 case 2: 639 /* Register 2 is only used for the keyboard */ 640 return 3; 641 case 3: 642 /* 643 * Fortunately our devices only implement writes 644 * to register 3 which is fixed at 2 bytes 645 */ 646 return 3; 647 default: 648 qemu_log_mask(LOG_UNIMP, "ADB unknown length for register %d\n", 649 reg); 650 return 1; 651 } 652 default: 653 /* Talk, BusReset */ 654 return 1; 655 } 656 } 657 658 static void adb_via_send(MOS6522Q800VIA1State *v1s, int state, uint8_t data) 659 { 660 MOS6522State *ms = MOS6522(v1s); 661 ADBBusState *adb_bus = &v1s->adb_bus; 662 uint16_t autopoll_mask; 663 664 switch (state) { 665 case ADB_STATE_NEW: 666 /* 667 * Command byte: vADBInt tells host autopoll data already present 668 * in VIA shift register and ADB transceiver 669 */ 670 adb_autopoll_block(adb_bus); 671 672 if (adb_bus->status & ADB_STATUS_POLLREPLY) { 673 /* Tell the host the existing data is from autopoll */ 674 ms->b &= ~VIA1B_vADBInt; 675 } else { 676 ms->b |= VIA1B_vADBInt; 677 v1s->adb_data_out_index = 0; 678 v1s->adb_data_out[v1s->adb_data_out_index++] = data; 679 } 680 681 trace_via1_adb_send(" NEW", data, (ms->b & VIA1B_vADBInt) ? "+" : "-"); 682 qemu_irq_raise(v1s->adb_data_ready); 683 break; 684 685 case ADB_STATE_EVEN: 686 case ADB_STATE_ODD: 687 ms->b |= VIA1B_vADBInt; 688 v1s->adb_data_out[v1s->adb_data_out_index++] = data; 689 690 trace_via1_adb_send(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 691 data, (ms->b & VIA1B_vADBInt) ? "+" : "-"); 692 qemu_irq_raise(v1s->adb_data_ready); 693 break; 694 695 case ADB_STATE_IDLE: 696 return; 697 } 698 699 /* If the command is complete, execute it */ 700 if (v1s->adb_data_out_index == adb_via_send_len(v1s->adb_data_out[0])) { 701 v1s->adb_data_in_size = adb_request(adb_bus, v1s->adb_data_in, 702 v1s->adb_data_out, 703 v1s->adb_data_out_index); 704 v1s->adb_data_in_index = 0; 705 706 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 707 /* 708 * Bus timeout (but allow first EVEN and ODD byte to indicate 709 * timeout via vADBInt and SRQ status) 710 */ 711 v1s->adb_data_in[0] = 0xff; 712 v1s->adb_data_in[1] = 0xff; 713 v1s->adb_data_in_size = 2; 714 } 715 716 /* 717 * If last command is TALK, store it for use by autopoll and adjust 718 * the autopoll mask accordingly 719 */ 720 if ((v1s->adb_data_out[0] & 0xc) == 0xc) { 721 v1s->adb_autopoll_cmd = v1s->adb_data_out[0]; 722 723 autopoll_mask = 1 << (v1s->adb_autopoll_cmd >> 4); 724 adb_set_autopoll_mask(adb_bus, autopoll_mask); 725 } 726 } 727 } 728 729 static void adb_via_receive(MOS6522Q800VIA1State *v1s, int state, uint8_t *data) 730 { 731 MOS6522State *ms = MOS6522(v1s); 732 ADBBusState *adb_bus = &v1s->adb_bus; 733 uint16_t pending; 734 735 switch (state) { 736 case ADB_STATE_NEW: 737 ms->b |= VIA1B_vADBInt; 738 return; 739 740 case ADB_STATE_IDLE: 741 ms->b |= VIA1B_vADBInt; 742 adb_autopoll_unblock(adb_bus); 743 744 trace_via1_adb_receive("IDLE", *data, 745 (ms->b & VIA1B_vADBInt) ? "+" : "-", adb_bus->status, 746 v1s->adb_data_in_index, v1s->adb_data_in_size); 747 748 break; 749 750 case ADB_STATE_EVEN: 751 case ADB_STATE_ODD: 752 switch (v1s->adb_data_in_index) { 753 case 0: 754 /* First EVEN byte: vADBInt indicates bus timeout */ 755 *data = v1s->adb_data_in[v1s->adb_data_in_index]; 756 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 757 ms->b &= ~VIA1B_vADBInt; 758 } else { 759 ms->b |= VIA1B_vADBInt; 760 } 761 762 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 763 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 764 adb_bus->status, v1s->adb_data_in_index, 765 v1s->adb_data_in_size); 766 767 v1s->adb_data_in_index++; 768 break; 769 770 case 1: 771 /* First ODD byte: vADBInt indicates SRQ */ 772 *data = v1s->adb_data_in[v1s->adb_data_in_index]; 773 pending = adb_bus->pending & ~(1 << (v1s->adb_autopoll_cmd >> 4)); 774 if (pending) { 775 ms->b &= ~VIA1B_vADBInt; 776 } else { 777 ms->b |= VIA1B_vADBInt; 778 } 779 780 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 781 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 782 adb_bus->status, v1s->adb_data_in_index, 783 v1s->adb_data_in_size); 784 785 v1s->adb_data_in_index++; 786 break; 787 788 default: 789 /* 790 * Otherwise vADBInt indicates end of data. Note that Linux 791 * specifically checks for the sequence 0x0 0xff to confirm the 792 * end of the poll reply, so provide these extra bytes below to 793 * keep it happy 794 */ 795 if (v1s->adb_data_in_index < v1s->adb_data_in_size) { 796 /* Next data byte */ 797 *data = v1s->adb_data_in[v1s->adb_data_in_index]; 798 ms->b |= VIA1B_vADBInt; 799 } else if (v1s->adb_data_in_index == v1s->adb_data_in_size) { 800 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 801 /* Bus timeout (no more data) */ 802 *data = 0xff; 803 } else { 804 /* Return 0x0 after reply */ 805 *data = 0; 806 } 807 ms->b &= ~VIA1B_vADBInt; 808 } else { 809 /* Bus timeout (no more data) */ 810 *data = 0xff; 811 ms->b &= ~VIA1B_vADBInt; 812 adb_bus->status = 0; 813 adb_autopoll_unblock(adb_bus); 814 } 815 816 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 817 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 818 adb_bus->status, v1s->adb_data_in_index, 819 v1s->adb_data_in_size); 820 821 if (v1s->adb_data_in_index <= v1s->adb_data_in_size) { 822 v1s->adb_data_in_index++; 823 } 824 break; 825 } 826 827 qemu_irq_raise(v1s->adb_data_ready); 828 break; 829 } 830 } 831 832 static void via1_adb_update(MOS6522Q800VIA1State *v1s) 833 { 834 MOS6522State *s = MOS6522(v1s); 835 int oldstate, state; 836 837 oldstate = (v1s->last_b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; 838 state = (s->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; 839 840 if (state != oldstate) { 841 if (s->acr & VIA1ACR_vShiftOut) { 842 /* output mode */ 843 adb_via_send(v1s, state, s->sr); 844 } else { 845 /* input mode */ 846 adb_via_receive(v1s, state, &s->sr); 847 } 848 } 849 } 850 851 static void via1_auxmode_update(MOS6522Q800VIA1State *v1s) 852 { 853 MOS6522State *s = MOS6522(v1s); 854 int oldirq, irq; 855 856 oldirq = (v1s->last_b & VIA1B_vMystery) ? 1 : 0; 857 irq = (s->b & VIA1B_vMystery) ? 1 : 0; 858 859 /* Check to see if the A/UX mode bit has changed */ 860 if (irq != oldirq) { 861 trace_via1_auxmode(irq); 862 qemu_set_irq(v1s->auxmode_irq, irq); 863 } 864 } 865 866 static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size) 867 { 868 MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque); 869 MOS6522State *ms = MOS6522(s); 870 871 addr = (addr >> 9) & 0xf; 872 return mos6522_read(ms, addr, size); 873 } 874 875 static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val, 876 unsigned size) 877 { 878 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 879 MOS6522State *ms = MOS6522(v1s); 880 881 addr = (addr >> 9) & 0xf; 882 mos6522_write(ms, addr, val, size); 883 884 switch (addr) { 885 case VIA_REG_B: 886 via1_rtc_update(v1s); 887 via1_adb_update(v1s); 888 via1_auxmode_update(v1s); 889 890 v1s->last_b = ms->b; 891 break; 892 } 893 } 894 895 static const MemoryRegionOps mos6522_q800_via1_ops = { 896 .read = mos6522_q800_via1_read, 897 .write = mos6522_q800_via1_write, 898 .endianness = DEVICE_BIG_ENDIAN, 899 .valid = { 900 .min_access_size = 1, 901 .max_access_size = 4, 902 }, 903 }; 904 905 static uint64_t mos6522_q800_via2_read(void *opaque, hwaddr addr, unsigned size) 906 { 907 MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque); 908 MOS6522State *ms = MOS6522(s); 909 910 addr = (addr >> 9) & 0xf; 911 return mos6522_read(ms, addr, size); 912 } 913 914 static void mos6522_q800_via2_write(void *opaque, hwaddr addr, uint64_t val, 915 unsigned size) 916 { 917 MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque); 918 MOS6522State *ms = MOS6522(s); 919 920 addr = (addr >> 9) & 0xf; 921 mos6522_write(ms, addr, val, size); 922 } 923 924 static const MemoryRegionOps mos6522_q800_via2_ops = { 925 .read = mos6522_q800_via2_read, 926 .write = mos6522_q800_via2_write, 927 .endianness = DEVICE_BIG_ENDIAN, 928 .valid = { 929 .min_access_size = 1, 930 .max_access_size = 4, 931 }, 932 }; 933 934 static void via1_postload_update_cb(void *opaque, bool running, RunState state) 935 { 936 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 937 938 qemu_del_vm_change_state_handler(v1s->vmstate); 939 v1s->vmstate = NULL; 940 941 pram_update(v1s); 942 } 943 944 static int via1_post_load(void *opaque, int version_id) 945 { 946 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 947 948 if (v1s->blk) { 949 v1s->vmstate = qemu_add_vm_change_state_handler( 950 via1_postload_update_cb, v1s); 951 } 952 953 return 0; 954 } 955 956 /* VIA 1 */ 957 static void mos6522_q800_via1_reset(DeviceState *dev) 958 { 959 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(dev); 960 MOS6522State *ms = MOS6522(v1s); 961 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 962 ADBBusState *adb_bus = &v1s->adb_bus; 963 964 mdc->parent_reset(dev); 965 966 ms->timers[0].frequency = VIA_TIMER_FREQ; 967 ms->timers[1].frequency = VIA_TIMER_FREQ; 968 969 ms->b = VIA1B_vADB_StateMask | VIA1B_vADBInt | VIA1B_vRTCEnb; 970 971 /* ADB/RTC */ 972 adb_set_autopoll_enabled(adb_bus, true); 973 v1s->cmd = REG_EMPTY; 974 v1s->alt = REG_EMPTY; 975 } 976 977 static void mos6522_q800_via1_realize(DeviceState *dev, Error **errp) 978 { 979 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(dev); 980 ADBBusState *adb_bus = &v1s->adb_bus; 981 struct tm tm; 982 int ret; 983 984 v1s->one_second_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, via1_one_second, 985 v1s); 986 via1_one_second_update(v1s); 987 v1s->sixty_hz_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, via1_sixty_hz, 988 v1s); 989 via1_sixty_hz_update(v1s); 990 991 qemu_get_timedate(&tm, 0); 992 v1s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; 993 994 adb_register_autopoll_callback(adb_bus, adb_via_poll, v1s); 995 v1s->adb_data_ready = qdev_get_gpio_in(dev, VIA1_IRQ_ADB_READY_BIT); 996 997 if (v1s->blk) { 998 int64_t len = blk_getlength(v1s->blk); 999 if (len < 0) { 1000 error_setg_errno(errp, -len, 1001 "could not get length of backing image"); 1002 return; 1003 } 1004 ret = blk_set_perm(v1s->blk, 1005 BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, 1006 BLK_PERM_ALL, errp); 1007 if (ret < 0) { 1008 return; 1009 } 1010 1011 len = blk_pread(v1s->blk, 0, v1s->PRAM, sizeof(v1s->PRAM)); 1012 if (len != sizeof(v1s->PRAM)) { 1013 error_setg(errp, "can't read PRAM contents"); 1014 return; 1015 } 1016 } 1017 } 1018 1019 static void mos6522_q800_via1_init(Object *obj) 1020 { 1021 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(obj); 1022 SysBusDevice *sbd = SYS_BUS_DEVICE(v1s); 1023 1024 memory_region_init_io(&v1s->via_mem, obj, &mos6522_q800_via1_ops, v1s, 1025 "via1", VIA_SIZE); 1026 sysbus_init_mmio(sbd, &v1s->via_mem); 1027 1028 /* ADB */ 1029 qbus_init((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus), 1030 TYPE_ADB_BUS, DEVICE(v1s), "adb.0"); 1031 1032 /* A/UX mode */ 1033 qdev_init_gpio_out(DEVICE(obj), &v1s->auxmode_irq, 1); 1034 } 1035 1036 static const VMStateDescription vmstate_q800_via1 = { 1037 .name = "q800-via1", 1038 .version_id = 0, 1039 .minimum_version_id = 0, 1040 .post_load = via1_post_load, 1041 .fields = (VMStateField[]) { 1042 VMSTATE_STRUCT(parent_obj, MOS6522Q800VIA1State, 0, vmstate_mos6522, 1043 MOS6522State), 1044 VMSTATE_UINT8(last_b, MOS6522Q800VIA1State), 1045 /* RTC */ 1046 VMSTATE_BUFFER(PRAM, MOS6522Q800VIA1State), 1047 VMSTATE_UINT32(tick_offset, MOS6522Q800VIA1State), 1048 VMSTATE_UINT8(data_out, MOS6522Q800VIA1State), 1049 VMSTATE_INT32(data_out_cnt, MOS6522Q800VIA1State), 1050 VMSTATE_UINT8(data_in, MOS6522Q800VIA1State), 1051 VMSTATE_UINT8(data_in_cnt, MOS6522Q800VIA1State), 1052 VMSTATE_UINT8(cmd, MOS6522Q800VIA1State), 1053 VMSTATE_INT32(wprotect, MOS6522Q800VIA1State), 1054 VMSTATE_INT32(alt, MOS6522Q800VIA1State), 1055 /* ADB */ 1056 VMSTATE_INT32(adb_data_in_size, MOS6522Q800VIA1State), 1057 VMSTATE_INT32(adb_data_in_index, MOS6522Q800VIA1State), 1058 VMSTATE_INT32(adb_data_out_index, MOS6522Q800VIA1State), 1059 VMSTATE_BUFFER(adb_data_in, MOS6522Q800VIA1State), 1060 VMSTATE_BUFFER(adb_data_out, MOS6522Q800VIA1State), 1061 VMSTATE_UINT8(adb_autopoll_cmd, MOS6522Q800VIA1State), 1062 /* Timers */ 1063 VMSTATE_TIMER_PTR(one_second_timer, MOS6522Q800VIA1State), 1064 VMSTATE_INT64(next_second, MOS6522Q800VIA1State), 1065 VMSTATE_TIMER_PTR(sixty_hz_timer, MOS6522Q800VIA1State), 1066 VMSTATE_INT64(next_sixty_hz, MOS6522Q800VIA1State), 1067 VMSTATE_END_OF_LIST() 1068 } 1069 }; 1070 1071 static Property mos6522_q800_via1_properties[] = { 1072 DEFINE_PROP_DRIVE("drive", MOS6522Q800VIA1State, blk), 1073 DEFINE_PROP_END_OF_LIST(), 1074 }; 1075 1076 static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data) 1077 { 1078 DeviceClass *dc = DEVICE_CLASS(oc); 1079 1080 dc->realize = mos6522_q800_via1_realize; 1081 dc->reset = mos6522_q800_via1_reset; 1082 dc->vmsd = &vmstate_q800_via1; 1083 device_class_set_props(dc, mos6522_q800_via1_properties); 1084 } 1085 1086 static const TypeInfo mos6522_q800_via1_type_info = { 1087 .name = TYPE_MOS6522_Q800_VIA1, 1088 .parent = TYPE_MOS6522, 1089 .instance_size = sizeof(MOS6522Q800VIA1State), 1090 .instance_init = mos6522_q800_via1_init, 1091 .class_init = mos6522_q800_via1_class_init, 1092 }; 1093 1094 /* VIA 2 */ 1095 static void mos6522_q800_via2_portB_write(MOS6522State *s) 1096 { 1097 if (s->dirb & VIA2B_vPower && (s->b & VIA2B_vPower) == 0) { 1098 /* shutdown */ 1099 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 1100 } 1101 } 1102 1103 static void mos6522_q800_via2_reset(DeviceState *dev) 1104 { 1105 MOS6522State *ms = MOS6522(dev); 1106 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 1107 1108 mdc->parent_reset(dev); 1109 1110 ms->timers[0].frequency = VIA_TIMER_FREQ; 1111 ms->timers[1].frequency = VIA_TIMER_FREQ; 1112 1113 ms->dirb = 0; 1114 ms->b = 0; 1115 ms->dira = 0; 1116 ms->a = 0x7f; 1117 } 1118 1119 static void via2_nubus_irq_request(void *opaque, int n, int level) 1120 { 1121 MOS6522Q800VIA2State *v2s = opaque; 1122 MOS6522State *s = MOS6522(v2s); 1123 qemu_irq irq = qdev_get_gpio_in(DEVICE(s), VIA2_IRQ_NUBUS_BIT); 1124 1125 if (level) { 1126 /* Port A nubus IRQ inputs are active LOW */ 1127 s->a &= ~(1 << n); 1128 } else { 1129 s->a |= (1 << n); 1130 } 1131 1132 qemu_set_irq(irq, level); 1133 } 1134 1135 static void mos6522_q800_via2_init(Object *obj) 1136 { 1137 MOS6522Q800VIA2State *v2s = MOS6522_Q800_VIA2(obj); 1138 SysBusDevice *sbd = SYS_BUS_DEVICE(v2s); 1139 1140 memory_region_init_io(&v2s->via_mem, obj, &mos6522_q800_via2_ops, v2s, 1141 "via2", VIA_SIZE); 1142 sysbus_init_mmio(sbd, &v2s->via_mem); 1143 1144 qdev_init_gpio_in_named(DEVICE(obj), via2_nubus_irq_request, "nubus-irq", 1145 VIA2_NUBUS_IRQ_NB); 1146 } 1147 1148 static const VMStateDescription vmstate_q800_via2 = { 1149 .name = "q800-via2", 1150 .version_id = 0, 1151 .minimum_version_id = 0, 1152 .fields = (VMStateField[]) { 1153 VMSTATE_STRUCT(parent_obj, MOS6522Q800VIA2State, 0, vmstate_mos6522, 1154 MOS6522State), 1155 VMSTATE_END_OF_LIST() 1156 } 1157 }; 1158 1159 static void mos6522_q800_via2_class_init(ObjectClass *oc, void *data) 1160 { 1161 DeviceClass *dc = DEVICE_CLASS(oc); 1162 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); 1163 1164 dc->reset = mos6522_q800_via2_reset; 1165 dc->vmsd = &vmstate_q800_via2; 1166 mdc->portB_write = mos6522_q800_via2_portB_write; 1167 } 1168 1169 static const TypeInfo mos6522_q800_via2_type_info = { 1170 .name = TYPE_MOS6522_Q800_VIA2, 1171 .parent = TYPE_MOS6522, 1172 .instance_size = sizeof(MOS6522Q800VIA2State), 1173 .instance_init = mos6522_q800_via2_init, 1174 .class_init = mos6522_q800_via2_class_init, 1175 }; 1176 1177 static void mac_via_register_types(void) 1178 { 1179 type_register_static(&mos6522_q800_via1_type_info); 1180 type_register_static(&mos6522_q800_via2_type_info); 1181 } 1182 1183 type_init(mac_via_register_types); 1184