1 /* 2 * QEMU m68k Macintosh VIA device support 3 * 4 * Copyright (c) 2011-2018 Laurent Vivier 5 * Copyright (c) 2018 Mark Cave-Ayland 6 * 7 * Some parts from hw/misc/macio/cuda.c 8 * 9 * Copyright (c) 2004-2007 Fabrice Bellard 10 * Copyright (c) 2007 Jocelyn Mayer 11 * 12 * some parts from linux-2.6.29, arch/m68k/include/asm/mac_via.h 13 * 14 * This work is licensed under the terms of the GNU GPL, version 2 or later. 15 * See the COPYING file in the top-level directory. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu-common.h" 20 #include "migration/vmstate.h" 21 #include "hw/sysbus.h" 22 #include "hw/irq.h" 23 #include "qemu/timer.h" 24 #include "hw/misc/mac_via.h" 25 #include "hw/misc/mos6522.h" 26 #include "hw/input/adb.h" 27 #include "sysemu/runstate.h" 28 #include "qapi/error.h" 29 #include "qemu/cutils.h" 30 #include "hw/qdev-properties.h" 31 #include "hw/qdev-properties-system.h" 32 #include "sysemu/block-backend.h" 33 #include "trace.h" 34 #include "qemu/log.h" 35 36 /* 37 * VIAs: There are two in every machine, 38 */ 39 40 #define VIA_SIZE (0x2000) 41 42 /* 43 * Not all of these are true post MacII I think. 44 * CSA: probably the ones CHRP marks as 'unused' change purposes 45 * when the IWM becomes the SWIM. 46 * http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html 47 * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf 48 * 49 * also, http://developer.apple.com/technotes/hw/hw_09.html claims the 50 * following changes for IIfx: 51 * VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP. 52 * Also, "All of the functionality of VIA2 has been moved to other chips". 53 */ 54 55 #define VIA1A_vSccWrReq 0x80 /* 56 * SCC write. (input) 57 * [CHRP] SCC WREQ: Reflects the state of the 58 * Wait/Request pins from the SCC. 59 * [Macintosh Family Hardware] 60 * as CHRP on SE/30,II,IIx,IIcx,IIci. 61 * on IIfx, "0 means an active request" 62 */ 63 #define VIA1A_vRev8 0x40 /* 64 * Revision 8 board ??? 65 * [CHRP] En WaitReqB: Lets the WaitReq_L 66 * signal from port B of the SCC appear on 67 * the PA7 input pin. Output. 68 * [Macintosh Family] On the SE/30, this 69 * is the bit to flip screen buffers. 70 * 0=alternate, 1=main. 71 * on II,IIx,IIcx,IIci,IIfx this is a bit 72 * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx 73 */ 74 #define VIA1A_vHeadSel 0x20 /* 75 * Head select for IWM. 76 * [CHRP] unused. 77 * [Macintosh Family] "Floppy disk 78 * state-control line SEL" on all but IIfx 79 */ 80 #define VIA1A_vOverlay 0x10 /* 81 * [Macintosh Family] On SE/30,II,IIx,IIcx 82 * this bit enables the "Overlay" address 83 * map in the address decoders as it is on 84 * reset for mapping the ROM over the reset 85 * vector. 1=use overlay map. 86 * On the IIci,IIfx it is another bit of the 87 * CPU ID: 0=normal IIci, 1=IIci with parity 88 * feature or IIfx. 89 * [CHRP] En WaitReqA: Lets the WaitReq_L 90 * signal from port A of the SCC appear 91 * on the PA7 input pin (CHRP). Output. 92 * [MkLinux] "Drive Select" 93 * (with 0x20 being 'disk head select') 94 */ 95 #define VIA1A_vSync 0x08 /* 96 * [CHRP] Sync Modem: modem clock select: 97 * 1: select the external serial clock to 98 * drive the SCC's /RTxCA pin. 99 * 0: Select the 3.6864MHz clock to drive 100 * the SCC cell. 101 * [Macintosh Family] Correct on all but IIfx 102 */ 103 104 /* 105 * Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control 106 * on Macs which had the PWM sound hardware. Reserved on newer models. 107 * On IIci,IIfx, bits 1-2 are the rest of the CPU ID: 108 * bit 2: 1=IIci, 0=IIfx 109 * bit 1: 1 on both IIci and IIfx. 110 * MkLinux sez bit 0 is 'burnin flag' in this case. 111 * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as 112 * inputs, these bits will read 0. 113 */ 114 #define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */ 115 #define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */ 116 #define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */ 117 #define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */ 118 #define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */ 119 120 /* 121 * Info on VIA1B is from Macintosh Family Hardware & MkLinux. 122 * CHRP offers no info. 123 */ 124 #define VIA1B_vSound 0x80 /* 125 * Sound enable (for compatibility with 126 * PWM hardware) 0=enabled. 127 * Also, on IIci w/parity, shows parity error 128 * 0=error, 1=OK. 129 */ 130 #define VIA1B_vMystery 0x40 /* 131 * On IIci, parity enable. 0=enabled,1=disabled 132 * On SE/30, vertical sync interrupt enable. 133 * 0=enabled. This vSync interrupt shows up 134 * as a slot $E interrupt. 135 */ 136 #define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */ 137 #define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */ 138 #define VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/ 139 #define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */ 140 #define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */ 141 #define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */ 142 143 /* 144 * VIA2 A register is the interrupt lines raised off the nubus 145 * slots. 146 * The below info is from 'Macintosh Family Hardware.' 147 * MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.' 148 * It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and 149 * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike. 150 * Perhaps OSS uses vRAM1 and vRAM2 for ADB. 151 */ 152 153 #define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */ 154 #define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */ 155 #define VIA2A_vIRQE 0x20 /* IRQ from slot $E */ 156 #define VIA2A_vIRQD 0x10 /* IRQ from slot $D */ 157 #define VIA2A_vIRQC 0x08 /* IRQ from slot $C */ 158 #define VIA2A_vIRQB 0x04 /* IRQ from slot $B */ 159 #define VIA2A_vIRQA 0x02 /* IRQ from slot $A */ 160 #define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */ 161 162 /* 163 * RAM size bits decoded as follows: 164 * bit1 bit0 size of ICs in bank A 165 * 0 0 256 kbit 166 * 0 1 1 Mbit 167 * 1 0 4 Mbit 168 * 1 1 16 Mbit 169 */ 170 171 /* 172 * Register B has the fun stuff in it 173 */ 174 175 #define VIA2B_vVBL 0x80 /* 176 * VBL output to VIA1 (60.15Hz) driven by 177 * timer T1. 178 * on IIci, parity test: 0=test mode. 179 * [MkLinux] RBV_PARODD: 1=odd,0=even. 180 */ 181 #define VIA2B_vSndJck 0x40 /* 182 * External sound jack status. 183 * 0=plug is inserted. On SE/30, always 0 184 */ 185 #define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */ 186 #define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */ 187 #define VIA2B_vMode32 0x08 /* 188 * 24/32bit switch - doubles as cache flush 189 * on II, AMU/PMMU control. 190 * if AMU, 0=24bit to 32bit translation 191 * if PMMU, 1=PMMU is accessing page table. 192 * on SE/30 tied low. 193 * on IIx,IIcx,IIfx, unused. 194 * on IIci/RBV, cache control. 0=flush cache. 195 */ 196 #define VIA2B_vPower 0x04 /* 197 * Power off, 0=shut off power. 198 * on SE/30 this signal sent to PDS card. 199 */ 200 #define VIA2B_vBusLk 0x02 /* 201 * Lock NuBus transactions, 0=locked. 202 * on SE/30 sent to PDS card. 203 */ 204 #define VIA2B_vCDis 0x01 /* 205 * Cache control. On IIci, 1=disable cache card 206 * on others, 0=disable processor's instruction 207 * and data caches. 208 */ 209 210 /* interrupt flags */ 211 212 #define IRQ_SET 0x80 213 214 /* common */ 215 216 #define VIA_IRQ_TIMER1 0x40 217 #define VIA_IRQ_TIMER2 0x20 218 219 /* 220 * Apple sez: http://developer.apple.com/technotes/ov/ov_04.html 221 * Another example of a valid function that has no ROM support is the use 222 * of the alternate video page for page-flipping animation. Since there 223 * is no ROM call to flip pages, it is necessary to go play with the 224 * right bit in the VIA chip (6522 Versatile Interface Adapter). 225 * [CSA: don't know which one this is, but it's one of 'em!] 226 */ 227 228 /* 229 * 6522 registers - see databook. 230 * CSA: Assignments for VIA1 confirmed from CHRP spec. 231 */ 232 233 /* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */ 234 /* Note: 15 VIA regs, 8 RBV regs */ 235 236 #define vBufB 0x0000 /* [VIA/RBV] Register B */ 237 #define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */ 238 #define vDirB 0x0400 /* [VIA only] Data Direction Register B. */ 239 #define vDirA 0x0600 /* [VIA only] Data Direction Register A. */ 240 #define vT1CL 0x0800 /* [VIA only] Timer one counter low. */ 241 #define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */ 242 #define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */ 243 #define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */ 244 #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ 245 #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ 246 #define vSR 0x1400 /* [VIA only] Shift register. */ 247 #define vACR 0x1600 /* [VIA only] Auxilary control register. */ 248 #define vPCR 0x1800 /* [VIA only] Peripheral control register. */ 249 /* 250 * CHRP sez never ever to *write* this. 251 * Mac family says never to *change* this. 252 * In fact we need to initialize it once at start. 253 */ 254 #define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */ 255 #define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */ 256 #define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */ 257 258 /* from linux 2.6 drivers/macintosh/via-macii.c */ 259 260 /* Bits in ACR */ 261 262 #define VIA1ACR_vShiftCtrl 0x1c /* Shift register control bits */ 263 #define VIA1ACR_vShiftExtClk 0x0c /* Shift on external clock */ 264 #define VIA1ACR_vShiftOut 0x10 /* Shift out if 1 */ 265 266 /* 267 * Apple Macintosh Family Hardware Refenece 268 * Table 19-10 ADB transaction states 269 */ 270 271 #define ADB_STATE_NEW 0 272 #define ADB_STATE_EVEN 1 273 #define ADB_STATE_ODD 2 274 #define ADB_STATE_IDLE 3 275 276 #define VIA1B_vADB_StateMask (VIA1B_vADBS1 | VIA1B_vADBS2) 277 #define VIA1B_vADB_StateShift 4 278 279 #define VIA_TIMER_FREQ (783360) 280 #define VIA_ADB_POLL_FREQ 50 /* XXX: not real */ 281 282 /* 283 * Guide to the Macintosh Family Hardware ch. 12 "Displays" p. 401 gives the 284 * precise 60Hz interrupt frequency as ~60.15Hz with a period of 16625.8 us 285 */ 286 #define VIA_60HZ_TIMER_PERIOD_NS 16625800 287 288 /* VIA returns time offset from Jan 1, 1904, not 1970 */ 289 #define RTC_OFFSET 2082844800 290 291 enum { 292 REG_0, 293 REG_1, 294 REG_2, 295 REG_3, 296 REG_TEST, 297 REG_WPROTECT, 298 REG_PRAM_ADDR, 299 REG_PRAM_ADDR_LAST = REG_PRAM_ADDR + 19, 300 REG_PRAM_SECT, 301 REG_PRAM_SECT_LAST = REG_PRAM_SECT + 7, 302 REG_INVALID, 303 REG_EMPTY = 0xff, 304 }; 305 306 static void via1_sixty_hz_update(MOS6522Q800VIA1State *v1s) 307 { 308 /* 60 Hz irq */ 309 v1s->next_sixty_hz = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 310 VIA_60HZ_TIMER_PERIOD_NS) / 311 VIA_60HZ_TIMER_PERIOD_NS * VIA_60HZ_TIMER_PERIOD_NS; 312 timer_mod(v1s->sixty_hz_timer, v1s->next_sixty_hz); 313 } 314 315 static void via1_one_second_update(MOS6522Q800VIA1State *v1s) 316 { 317 v1s->next_second = (qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000) / 318 1000 * 1000; 319 timer_mod(v1s->one_second_timer, v1s->next_second); 320 } 321 322 static void via1_sixty_hz(void *opaque) 323 { 324 MOS6522Q800VIA1State *v1s = opaque; 325 MOS6522State *s = MOS6522(v1s); 326 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 327 328 s->ifr |= VIA1_IRQ_60HZ; 329 mdc->update_irq(s); 330 331 via1_sixty_hz_update(v1s); 332 } 333 334 static void via1_one_second(void *opaque) 335 { 336 MOS6522Q800VIA1State *v1s = opaque; 337 MOS6522State *s = MOS6522(v1s); 338 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 339 340 s->ifr |= VIA1_IRQ_ONE_SECOND; 341 mdc->update_irq(s); 342 343 via1_one_second_update(v1s); 344 } 345 346 static void via1_irq_request(void *opaque, int irq, int level) 347 { 348 MOS6522Q800VIA1State *v1s = opaque; 349 MOS6522State *s = MOS6522(v1s); 350 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 351 352 if (level) { 353 s->ifr |= 1 << irq; 354 } else { 355 s->ifr &= ~(1 << irq); 356 } 357 358 mdc->update_irq(s); 359 } 360 361 static void via2_irq_request(void *opaque, int irq, int level) 362 { 363 MOS6522Q800VIA2State *v2s = opaque; 364 MOS6522State *s = MOS6522(v2s); 365 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 366 367 if (level) { 368 s->ifr |= 1 << irq; 369 } else { 370 s->ifr &= ~(1 << irq); 371 } 372 373 mdc->update_irq(s); 374 } 375 376 377 static void pram_update(MOS6522Q800VIA1State *v1s) 378 { 379 if (v1s->blk) { 380 if (blk_pwrite(v1s->blk, 0, v1s->PRAM, sizeof(v1s->PRAM), 0) < 0) { 381 qemu_log("pram_update: cannot write to file\n"); 382 } 383 } 384 } 385 386 /* 387 * RTC Commands 388 * 389 * Command byte Register addressed by the command 390 * 391 * z0000001 Seconds register 0 (lowest-order byte) 392 * z0000101 Seconds register 1 393 * z0001001 Seconds register 2 394 * z0001101 Seconds register 3 (highest-order byte) 395 * 00110001 Test register (write-only) 396 * 00110101 Write-Protect Register (write-only) 397 * z010aa01 RAM address 100aa ($10-$13) (first 20 bytes only) 398 * z1aaaa01 RAM address 0aaaa ($00-$0F) (first 20 bytes only) 399 * z0111aaa Extended memory designator and sector number 400 * 401 * For a read request, z=1, for a write z=0 402 * The letter a indicates bits whose value depend on what parameter 403 * RAM byte you want to address 404 */ 405 static int via1_rtc_compact_cmd(uint8_t value) 406 { 407 uint8_t read = value & 0x80; 408 409 value &= 0x7f; 410 411 /* the last 2 bits of a command byte must always be 0b01 ... */ 412 if ((value & 0x78) == 0x38) { 413 /* except for the extended memory designator */ 414 return read | (REG_PRAM_SECT + (value & 0x07)); 415 } 416 if ((value & 0x03) == 0x01) { 417 value >>= 2; 418 if ((value & 0x1c) == 0) { 419 /* seconds registers */ 420 return read | (REG_0 + (value & 0x03)); 421 } else if ((value == 0x0c) && !read) { 422 return REG_TEST; 423 } else if ((value == 0x0d) && !read) { 424 return REG_WPROTECT; 425 } else if ((value & 0x1c) == 0x08) { 426 /* RAM address 0x10 to 0x13 */ 427 return read | (REG_PRAM_ADDR + 0x10 + (value & 0x03)); 428 } else if ((value & 0x43) == 0x41) { 429 /* RAM address 0x00 to 0x0f */ 430 return read | (REG_PRAM_ADDR + (value & 0x0f)); 431 } 432 } 433 return REG_INVALID; 434 } 435 436 static void via1_rtc_update(MOS6522Q800VIA1State *v1s) 437 { 438 MOS6522State *s = MOS6522(v1s); 439 int cmd, sector, addr; 440 uint32_t time; 441 442 if (s->b & VIA1B_vRTCEnb) { 443 return; 444 } 445 446 if (s->dirb & VIA1B_vRTCData) { 447 /* send bits to the RTC */ 448 if (!(v1s->last_b & VIA1B_vRTCClk) && (s->b & VIA1B_vRTCClk)) { 449 v1s->data_out <<= 1; 450 v1s->data_out |= s->b & VIA1B_vRTCData; 451 v1s->data_out_cnt++; 452 } 453 trace_via1_rtc_update_data_out(v1s->data_out_cnt, v1s->data_out); 454 } else { 455 trace_via1_rtc_update_data_in(v1s->data_in_cnt, v1s->data_in); 456 /* receive bits from the RTC */ 457 if ((v1s->last_b & VIA1B_vRTCClk) && 458 !(s->b & VIA1B_vRTCClk) && 459 v1s->data_in_cnt) { 460 s->b = (s->b & ~VIA1B_vRTCData) | 461 ((v1s->data_in >> 7) & VIA1B_vRTCData); 462 v1s->data_in <<= 1; 463 v1s->data_in_cnt--; 464 } 465 return; 466 } 467 468 if (v1s->data_out_cnt != 8) { 469 return; 470 } 471 472 v1s->data_out_cnt = 0; 473 474 trace_via1_rtc_internal_status(v1s->cmd, v1s->alt, v1s->data_out); 475 /* first byte: it's a command */ 476 if (v1s->cmd == REG_EMPTY) { 477 478 cmd = via1_rtc_compact_cmd(v1s->data_out); 479 trace_via1_rtc_internal_cmd(cmd); 480 481 if (cmd == REG_INVALID) { 482 trace_via1_rtc_cmd_invalid(v1s->data_out); 483 return; 484 } 485 486 if (cmd & 0x80) { /* this is a read command */ 487 switch (cmd & 0x7f) { 488 case REG_0...REG_3: /* seconds registers */ 489 /* 490 * register 0 is lowest-order byte 491 * register 3 is highest-order byte 492 */ 493 494 time = v1s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 495 / NANOSECONDS_PER_SECOND); 496 trace_via1_rtc_internal_time(time); 497 v1s->data_in = (time >> ((cmd & 0x03) << 3)) & 0xff; 498 v1s->data_in_cnt = 8; 499 trace_via1_rtc_cmd_seconds_read((cmd & 0x7f) - REG_0, 500 v1s->data_in); 501 break; 502 case REG_PRAM_ADDR...REG_PRAM_ADDR_LAST: 503 /* PRAM address 0x00 -> 0x13 */ 504 v1s->data_in = v1s->PRAM[(cmd & 0x7f) - REG_PRAM_ADDR]; 505 v1s->data_in_cnt = 8; 506 trace_via1_rtc_cmd_pram_read((cmd & 0x7f) - REG_PRAM_ADDR, 507 v1s->data_in); 508 break; 509 case REG_PRAM_SECT...REG_PRAM_SECT_LAST: 510 /* 511 * extended memory designator and sector number 512 * the only two-byte read command 513 */ 514 trace_via1_rtc_internal_set_cmd(cmd); 515 v1s->cmd = cmd; 516 break; 517 default: 518 g_assert_not_reached(); 519 break; 520 } 521 return; 522 } 523 524 /* this is a write command, needs a parameter */ 525 if (cmd == REG_WPROTECT || !v1s->wprotect) { 526 trace_via1_rtc_internal_set_cmd(cmd); 527 v1s->cmd = cmd; 528 } else { 529 trace_via1_rtc_internal_ignore_cmd(cmd); 530 } 531 return; 532 } 533 534 /* second byte: it's a parameter */ 535 if (v1s->alt == REG_EMPTY) { 536 switch (v1s->cmd & 0x7f) { 537 case REG_0...REG_3: /* seconds register */ 538 /* FIXME */ 539 trace_via1_rtc_cmd_seconds_write(v1s->cmd - REG_0, v1s->data_out); 540 v1s->cmd = REG_EMPTY; 541 break; 542 case REG_TEST: 543 /* device control: nothing to do */ 544 trace_via1_rtc_cmd_test_write(v1s->data_out); 545 v1s->cmd = REG_EMPTY; 546 break; 547 case REG_WPROTECT: 548 /* Write Protect register */ 549 trace_via1_rtc_cmd_wprotect_write(v1s->data_out); 550 v1s->wprotect = !!(v1s->data_out & 0x80); 551 v1s->cmd = REG_EMPTY; 552 break; 553 case REG_PRAM_ADDR...REG_PRAM_ADDR_LAST: 554 /* PRAM address 0x00 -> 0x13 */ 555 trace_via1_rtc_cmd_pram_write(v1s->cmd - REG_PRAM_ADDR, 556 v1s->data_out); 557 v1s->PRAM[v1s->cmd - REG_PRAM_ADDR] = v1s->data_out; 558 pram_update(v1s); 559 v1s->cmd = REG_EMPTY; 560 break; 561 case REG_PRAM_SECT...REG_PRAM_SECT_LAST: 562 addr = (v1s->data_out >> 2) & 0x1f; 563 sector = (v1s->cmd & 0x7f) - REG_PRAM_SECT; 564 if (v1s->cmd & 0x80) { 565 /* it's a read */ 566 v1s->data_in = v1s->PRAM[sector * 32 + addr]; 567 v1s->data_in_cnt = 8; 568 trace_via1_rtc_cmd_pram_sect_read(sector, addr, 569 sector * 32 + addr, 570 v1s->data_in); 571 v1s->cmd = REG_EMPTY; 572 } else { 573 /* it's a write, we need one more parameter */ 574 trace_via1_rtc_internal_set_alt(addr, sector, addr); 575 v1s->alt = addr; 576 } 577 break; 578 default: 579 g_assert_not_reached(); 580 break; 581 } 582 return; 583 } 584 585 /* third byte: it's the data of a REG_PRAM_SECT write */ 586 g_assert(REG_PRAM_SECT <= v1s->cmd && v1s->cmd <= REG_PRAM_SECT_LAST); 587 sector = v1s->cmd - REG_PRAM_SECT; 588 v1s->PRAM[sector * 32 + v1s->alt] = v1s->data_out; 589 pram_update(v1s); 590 trace_via1_rtc_cmd_pram_sect_write(sector, v1s->alt, sector * 32 + v1s->alt, 591 v1s->data_out); 592 v1s->alt = REG_EMPTY; 593 v1s->cmd = REG_EMPTY; 594 } 595 596 static void adb_via_poll(void *opaque) 597 { 598 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 599 MOS6522State *s = MOS6522(v1s); 600 ADBBusState *adb_bus = &v1s->adb_bus; 601 uint8_t obuf[9]; 602 uint8_t *data = &s->sr; 603 int olen; 604 605 /* 606 * Setting vADBInt below indicates that an autopoll reply has been 607 * received, however we must block autopoll until the point where 608 * the entire reply has been read back to the host 609 */ 610 adb_autopoll_block(adb_bus); 611 612 if (v1s->adb_data_in_size > 0 && v1s->adb_data_in_index == 0) { 613 /* 614 * For older Linux kernels that switch to IDLE mode after sending the 615 * ADB command, detect if there is an existing response and return that 616 * as a a "fake" autopoll reply or bus timeout accordingly 617 */ 618 *data = v1s->adb_data_out[0]; 619 olen = v1s->adb_data_in_size; 620 621 s->b &= ~VIA1B_vADBInt; 622 qemu_irq_raise(v1s->adb_data_ready); 623 } else { 624 /* 625 * Otherwise poll as normal 626 */ 627 v1s->adb_data_in_index = 0; 628 v1s->adb_data_out_index = 0; 629 olen = adb_poll(adb_bus, obuf, adb_bus->autopoll_mask); 630 631 if (olen > 0) { 632 /* Autopoll response */ 633 *data = obuf[0]; 634 olen--; 635 memcpy(v1s->adb_data_in, &obuf[1], olen); 636 v1s->adb_data_in_size = olen; 637 638 s->b &= ~VIA1B_vADBInt; 639 qemu_irq_raise(v1s->adb_data_ready); 640 } else { 641 *data = v1s->adb_autopoll_cmd; 642 obuf[0] = 0xff; 643 obuf[1] = 0xff; 644 olen = 2; 645 646 memcpy(v1s->adb_data_in, obuf, olen); 647 v1s->adb_data_in_size = olen; 648 649 s->b &= ~VIA1B_vADBInt; 650 qemu_irq_raise(v1s->adb_data_ready); 651 } 652 } 653 654 trace_via1_adb_poll(*data, (s->b & VIA1B_vADBInt) ? "+" : "-", 655 adb_bus->status, v1s->adb_data_in_index, olen); 656 } 657 658 static int adb_via_send_len(uint8_t data) 659 { 660 /* Determine the send length from the given ADB command */ 661 uint8_t cmd = data & 0xc; 662 uint8_t reg = data & 0x3; 663 664 switch (cmd) { 665 case 0x8: 666 /* Listen command */ 667 switch (reg) { 668 case 2: 669 /* Register 2 is only used for the keyboard */ 670 return 3; 671 case 3: 672 /* 673 * Fortunately our devices only implement writes 674 * to register 3 which is fixed at 2 bytes 675 */ 676 return 3; 677 default: 678 qemu_log_mask(LOG_UNIMP, "ADB unknown length for register %d\n", 679 reg); 680 return 1; 681 } 682 default: 683 /* Talk, BusReset */ 684 return 1; 685 } 686 } 687 688 static void adb_via_send(MOS6522Q800VIA1State *v1s, int state, uint8_t data) 689 { 690 MOS6522State *ms = MOS6522(v1s); 691 ADBBusState *adb_bus = &v1s->adb_bus; 692 uint16_t autopoll_mask; 693 694 switch (state) { 695 case ADB_STATE_NEW: 696 /* 697 * Command byte: vADBInt tells host autopoll data already present 698 * in VIA shift register and ADB transceiver 699 */ 700 adb_autopoll_block(adb_bus); 701 702 if (adb_bus->status & ADB_STATUS_POLLREPLY) { 703 /* Tell the host the existing data is from autopoll */ 704 ms->b &= ~VIA1B_vADBInt; 705 } else { 706 ms->b |= VIA1B_vADBInt; 707 v1s->adb_data_out_index = 0; 708 v1s->adb_data_out[v1s->adb_data_out_index++] = data; 709 } 710 711 trace_via1_adb_send(" NEW", data, (ms->b & VIA1B_vADBInt) ? "+" : "-"); 712 qemu_irq_raise(v1s->adb_data_ready); 713 break; 714 715 case ADB_STATE_EVEN: 716 case ADB_STATE_ODD: 717 ms->b |= VIA1B_vADBInt; 718 v1s->adb_data_out[v1s->adb_data_out_index++] = data; 719 720 trace_via1_adb_send(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 721 data, (ms->b & VIA1B_vADBInt) ? "+" : "-"); 722 qemu_irq_raise(v1s->adb_data_ready); 723 break; 724 725 case ADB_STATE_IDLE: 726 return; 727 } 728 729 /* If the command is complete, execute it */ 730 if (v1s->adb_data_out_index == adb_via_send_len(v1s->adb_data_out[0])) { 731 v1s->adb_data_in_size = adb_request(adb_bus, v1s->adb_data_in, 732 v1s->adb_data_out, 733 v1s->adb_data_out_index); 734 v1s->adb_data_in_index = 0; 735 736 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 737 /* 738 * Bus timeout (but allow first EVEN and ODD byte to indicate 739 * timeout via vADBInt and SRQ status) 740 */ 741 v1s->adb_data_in[0] = 0xff; 742 v1s->adb_data_in[1] = 0xff; 743 v1s->adb_data_in_size = 2; 744 } 745 746 /* 747 * If last command is TALK, store it for use by autopoll and adjust 748 * the autopoll mask accordingly 749 */ 750 if ((v1s->adb_data_out[0] & 0xc) == 0xc) { 751 v1s->adb_autopoll_cmd = v1s->adb_data_out[0]; 752 753 autopoll_mask = 1 << (v1s->adb_autopoll_cmd >> 4); 754 adb_set_autopoll_mask(adb_bus, autopoll_mask); 755 } 756 } 757 } 758 759 static void adb_via_receive(MOS6522Q800VIA1State *v1s, int state, uint8_t *data) 760 { 761 MOS6522State *ms = MOS6522(v1s); 762 ADBBusState *adb_bus = &v1s->adb_bus; 763 uint16_t pending; 764 765 switch (state) { 766 case ADB_STATE_NEW: 767 ms->b |= VIA1B_vADBInt; 768 return; 769 770 case ADB_STATE_IDLE: 771 ms->b |= VIA1B_vADBInt; 772 adb_autopoll_unblock(adb_bus); 773 774 trace_via1_adb_receive("IDLE", *data, 775 (ms->b & VIA1B_vADBInt) ? "+" : "-", adb_bus->status, 776 v1s->adb_data_in_index, v1s->adb_data_in_size); 777 778 break; 779 780 case ADB_STATE_EVEN: 781 case ADB_STATE_ODD: 782 switch (v1s->adb_data_in_index) { 783 case 0: 784 /* First EVEN byte: vADBInt indicates bus timeout */ 785 *data = v1s->adb_data_in[v1s->adb_data_in_index]; 786 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 787 ms->b &= ~VIA1B_vADBInt; 788 } else { 789 ms->b |= VIA1B_vADBInt; 790 } 791 792 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 793 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 794 adb_bus->status, v1s->adb_data_in_index, 795 v1s->adb_data_in_size); 796 797 v1s->adb_data_in_index++; 798 break; 799 800 case 1: 801 /* First ODD byte: vADBInt indicates SRQ */ 802 *data = v1s->adb_data_in[v1s->adb_data_in_index]; 803 pending = adb_bus->pending & ~(1 << (v1s->adb_autopoll_cmd >> 4)); 804 if (pending) { 805 ms->b &= ~VIA1B_vADBInt; 806 } else { 807 ms->b |= VIA1B_vADBInt; 808 } 809 810 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 811 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 812 adb_bus->status, v1s->adb_data_in_index, 813 v1s->adb_data_in_size); 814 815 v1s->adb_data_in_index++; 816 break; 817 818 default: 819 /* 820 * Otherwise vADBInt indicates end of data. Note that Linux 821 * specifically checks for the sequence 0x0 0xff to confirm the 822 * end of the poll reply, so provide these extra bytes below to 823 * keep it happy 824 */ 825 if (v1s->adb_data_in_index < v1s->adb_data_in_size) { 826 /* Next data byte */ 827 *data = v1s->adb_data_in[v1s->adb_data_in_index]; 828 ms->b |= VIA1B_vADBInt; 829 } else if (v1s->adb_data_in_index == v1s->adb_data_in_size) { 830 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 831 /* Bus timeout (no more data) */ 832 *data = 0xff; 833 } else { 834 /* Return 0x0 after reply */ 835 *data = 0; 836 } 837 ms->b &= ~VIA1B_vADBInt; 838 } else { 839 /* Bus timeout (no more data) */ 840 *data = 0xff; 841 ms->b &= ~VIA1B_vADBInt; 842 adb_bus->status = 0; 843 adb_autopoll_unblock(adb_bus); 844 } 845 846 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 847 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 848 adb_bus->status, v1s->adb_data_in_index, 849 v1s->adb_data_in_size); 850 851 if (v1s->adb_data_in_index <= v1s->adb_data_in_size) { 852 v1s->adb_data_in_index++; 853 } 854 break; 855 } 856 857 qemu_irq_raise(v1s->adb_data_ready); 858 break; 859 } 860 } 861 862 static void via1_adb_update(MOS6522Q800VIA1State *v1s) 863 { 864 MOS6522State *s = MOS6522(v1s); 865 int oldstate, state; 866 867 oldstate = (v1s->last_b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; 868 state = (s->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; 869 870 if (state != oldstate) { 871 if (s->acr & VIA1ACR_vShiftOut) { 872 /* output mode */ 873 adb_via_send(v1s, state, s->sr); 874 } else { 875 /* input mode */ 876 adb_via_receive(v1s, state, &s->sr); 877 } 878 } 879 } 880 881 static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size) 882 { 883 MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque); 884 MOS6522State *ms = MOS6522(s); 885 886 addr = (addr >> 9) & 0xf; 887 return mos6522_read(ms, addr, size); 888 } 889 890 static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val, 891 unsigned size) 892 { 893 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 894 MOS6522State *ms = MOS6522(v1s); 895 896 addr = (addr >> 9) & 0xf; 897 mos6522_write(ms, addr, val, size); 898 899 switch (addr) { 900 case VIA_REG_B: 901 via1_rtc_update(v1s); 902 via1_adb_update(v1s); 903 904 v1s->last_b = ms->b; 905 break; 906 } 907 } 908 909 static const MemoryRegionOps mos6522_q800_via1_ops = { 910 .read = mos6522_q800_via1_read, 911 .write = mos6522_q800_via1_write, 912 .endianness = DEVICE_BIG_ENDIAN, 913 .valid = { 914 .min_access_size = 1, 915 .max_access_size = 4, 916 }, 917 }; 918 919 static uint64_t mos6522_q800_via2_read(void *opaque, hwaddr addr, unsigned size) 920 { 921 MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque); 922 MOS6522State *ms = MOS6522(s); 923 924 addr = (addr >> 9) & 0xf; 925 return mos6522_read(ms, addr, size); 926 } 927 928 static void mos6522_q800_via2_write(void *opaque, hwaddr addr, uint64_t val, 929 unsigned size) 930 { 931 MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque); 932 MOS6522State *ms = MOS6522(s); 933 934 addr = (addr >> 9) & 0xf; 935 mos6522_write(ms, addr, val, size); 936 } 937 938 static const MemoryRegionOps mos6522_q800_via2_ops = { 939 .read = mos6522_q800_via2_read, 940 .write = mos6522_q800_via2_write, 941 .endianness = DEVICE_BIG_ENDIAN, 942 .valid = { 943 .min_access_size = 1, 944 .max_access_size = 4, 945 }, 946 }; 947 948 static void mac_via_realize(DeviceState *dev, Error **errp) 949 { 950 MacVIAState *m = MAC_VIA(dev); 951 MOS6522State *ms; 952 953 /* Pass through mos6522 output IRQs */ 954 ms = MOS6522(&m->mos6522_via1); 955 object_property_add_alias(OBJECT(dev), "irq[0]", OBJECT(ms), 956 SYSBUS_DEVICE_GPIO_IRQ "[0]"); 957 ms = MOS6522(&m->mos6522_via2); 958 object_property_add_alias(OBJECT(dev), "irq[1]", OBJECT(ms), 959 SYSBUS_DEVICE_GPIO_IRQ "[0]"); 960 961 sysbus_realize(SYS_BUS_DEVICE(&m->mos6522_via1), &error_abort); 962 sysbus_realize(SYS_BUS_DEVICE(&m->mos6522_via2), &error_abort); 963 964 /* Pass through mos6522 input IRQs */ 965 qdev_pass_gpios(DEVICE(&m->mos6522_via1), dev, "via1-irq"); 966 qdev_pass_gpios(DEVICE(&m->mos6522_via2), dev, "via2-irq"); 967 } 968 969 static void mac_via_init(Object *obj) 970 { 971 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 972 MacVIAState *m = MAC_VIA(obj); 973 974 /* MMIO */ 975 memory_region_init(&m->mmio, obj, "mac-via", 2 * VIA_SIZE); 976 sysbus_init_mmio(sbd, &m->mmio); 977 978 memory_region_init_io(&m->via1mem, obj, &mos6522_q800_via1_ops, 979 &m->mos6522_via1, "via1", VIA_SIZE); 980 memory_region_add_subregion(&m->mmio, 0x0, &m->via1mem); 981 982 memory_region_init_io(&m->via2mem, obj, &mos6522_q800_via2_ops, 983 &m->mos6522_via2, "via2", VIA_SIZE); 984 memory_region_add_subregion(&m->mmio, VIA_SIZE, &m->via2mem); 985 986 /* Init VIAs 1 and 2 */ 987 object_initialize_child(obj, "via1", &m->mos6522_via1, 988 TYPE_MOS6522_Q800_VIA1); 989 990 object_initialize_child(obj, "via2", &m->mos6522_via2, 991 TYPE_MOS6522_Q800_VIA2); 992 } 993 994 static void via1_postload_update_cb(void *opaque, bool running, RunState state) 995 { 996 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 997 998 qemu_del_vm_change_state_handler(v1s->vmstate); 999 v1s->vmstate = NULL; 1000 1001 pram_update(v1s); 1002 } 1003 1004 static int via1_post_load(void *opaque, int version_id) 1005 { 1006 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 1007 1008 if (v1s->blk) { 1009 v1s->vmstate = qemu_add_vm_change_state_handler( 1010 via1_postload_update_cb, v1s); 1011 } 1012 1013 return 0; 1014 } 1015 1016 static void mac_via_class_init(ObjectClass *oc, void *data) 1017 { 1018 DeviceClass *dc = DEVICE_CLASS(oc); 1019 1020 dc->realize = mac_via_realize; 1021 } 1022 1023 static TypeInfo mac_via_info = { 1024 .name = TYPE_MAC_VIA, 1025 .parent = TYPE_SYS_BUS_DEVICE, 1026 .instance_size = sizeof(MacVIAState), 1027 .instance_init = mac_via_init, 1028 .class_init = mac_via_class_init, 1029 }; 1030 1031 /* VIA 1 */ 1032 static void mos6522_q800_via1_reset(DeviceState *dev) 1033 { 1034 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(dev); 1035 MOS6522State *ms = MOS6522(v1s); 1036 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 1037 ADBBusState *adb_bus = &v1s->adb_bus; 1038 1039 mdc->parent_reset(dev); 1040 1041 ms->timers[0].frequency = VIA_TIMER_FREQ; 1042 ms->timers[1].frequency = VIA_TIMER_FREQ; 1043 1044 ms->b = VIA1B_vADB_StateMask | VIA1B_vADBInt | VIA1B_vRTCEnb; 1045 1046 /* ADB/RTC */ 1047 adb_set_autopoll_enabled(adb_bus, true); 1048 v1s->cmd = REG_EMPTY; 1049 v1s->alt = REG_EMPTY; 1050 } 1051 1052 static void mos6522_q800_via1_realize(DeviceState *dev, Error **errp) 1053 { 1054 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(dev); 1055 ADBBusState *adb_bus = &v1s->adb_bus; 1056 struct tm tm; 1057 int ret; 1058 1059 v1s->one_second_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, via1_one_second, 1060 v1s); 1061 via1_one_second_update(v1s); 1062 v1s->sixty_hz_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, via1_sixty_hz, 1063 v1s); 1064 via1_sixty_hz_update(v1s); 1065 1066 qemu_get_timedate(&tm, 0); 1067 v1s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; 1068 1069 adb_register_autopoll_callback(adb_bus, adb_via_poll, v1s); 1070 v1s->adb_data_ready = qdev_get_gpio_in_named(dev, "via1-irq", 1071 VIA1_IRQ_ADB_READY_BIT); 1072 1073 if (v1s->blk) { 1074 int64_t len = blk_getlength(v1s->blk); 1075 if (len < 0) { 1076 error_setg_errno(errp, -len, 1077 "could not get length of backing image"); 1078 return; 1079 } 1080 ret = blk_set_perm(v1s->blk, 1081 BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, 1082 BLK_PERM_ALL, errp); 1083 if (ret < 0) { 1084 return; 1085 } 1086 1087 len = blk_pread(v1s->blk, 0, v1s->PRAM, sizeof(v1s->PRAM)); 1088 if (len != sizeof(v1s->PRAM)) { 1089 error_setg(errp, "can't read PRAM contents"); 1090 return; 1091 } 1092 } 1093 } 1094 1095 static void mos6522_q800_via1_init(Object *obj) 1096 { 1097 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(obj); 1098 1099 /* ADB */ 1100 qbus_create_inplace((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus), 1101 TYPE_ADB_BUS, DEVICE(v1s), "adb.0"); 1102 1103 qdev_init_gpio_in_named(DEVICE(obj), via1_irq_request, "via1-irq", 1104 VIA1_IRQ_NB); 1105 } 1106 1107 static const VMStateDescription vmstate_q800_via1 = { 1108 .name = "q800-via1", 1109 .version_id = 0, 1110 .minimum_version_id = 0, 1111 .post_load = via1_post_load, 1112 .fields = (VMStateField[]) { 1113 VMSTATE_STRUCT(parent_obj, MOS6522Q800VIA1State, 0, vmstate_mos6522, 1114 MOS6522State), 1115 VMSTATE_UINT8(last_b, MOS6522Q800VIA1State), 1116 /* RTC */ 1117 VMSTATE_BUFFER(PRAM, MOS6522Q800VIA1State), 1118 VMSTATE_UINT32(tick_offset, MOS6522Q800VIA1State), 1119 VMSTATE_UINT8(data_out, MOS6522Q800VIA1State), 1120 VMSTATE_INT32(data_out_cnt, MOS6522Q800VIA1State), 1121 VMSTATE_UINT8(data_in, MOS6522Q800VIA1State), 1122 VMSTATE_UINT8(data_in_cnt, MOS6522Q800VIA1State), 1123 VMSTATE_UINT8(cmd, MOS6522Q800VIA1State), 1124 VMSTATE_INT32(wprotect, MOS6522Q800VIA1State), 1125 VMSTATE_INT32(alt, MOS6522Q800VIA1State), 1126 /* ADB */ 1127 VMSTATE_INT32(adb_data_in_size, MOS6522Q800VIA1State), 1128 VMSTATE_INT32(adb_data_in_index, MOS6522Q800VIA1State), 1129 VMSTATE_INT32(adb_data_out_index, MOS6522Q800VIA1State), 1130 VMSTATE_BUFFER(adb_data_in, MOS6522Q800VIA1State), 1131 VMSTATE_BUFFER(adb_data_out, MOS6522Q800VIA1State), 1132 VMSTATE_UINT8(adb_autopoll_cmd, MOS6522Q800VIA1State), 1133 /* Timers */ 1134 VMSTATE_TIMER_PTR(one_second_timer, MOS6522Q800VIA1State), 1135 VMSTATE_INT64(next_second, MOS6522Q800VIA1State), 1136 VMSTATE_TIMER_PTR(sixty_hz_timer, MOS6522Q800VIA1State), 1137 VMSTATE_INT64(next_sixty_hz, MOS6522Q800VIA1State), 1138 VMSTATE_END_OF_LIST() 1139 } 1140 }; 1141 1142 static Property mos6522_q800_via1_properties[] = { 1143 DEFINE_PROP_DRIVE("drive", MOS6522Q800VIA1State, blk), 1144 DEFINE_PROP_END_OF_LIST(), 1145 }; 1146 1147 static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data) 1148 { 1149 DeviceClass *dc = DEVICE_CLASS(oc); 1150 1151 dc->realize = mos6522_q800_via1_realize; 1152 dc->reset = mos6522_q800_via1_reset; 1153 dc->vmsd = &vmstate_q800_via1; 1154 device_class_set_props(dc, mos6522_q800_via1_properties); 1155 } 1156 1157 static const TypeInfo mos6522_q800_via1_type_info = { 1158 .name = TYPE_MOS6522_Q800_VIA1, 1159 .parent = TYPE_MOS6522, 1160 .instance_size = sizeof(MOS6522Q800VIA1State), 1161 .instance_init = mos6522_q800_via1_init, 1162 .class_init = mos6522_q800_via1_class_init, 1163 }; 1164 1165 /* VIA 2 */ 1166 static void mos6522_q800_via2_portB_write(MOS6522State *s) 1167 { 1168 if (s->dirb & VIA2B_vPower && (s->b & VIA2B_vPower) == 0) { 1169 /* shutdown */ 1170 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 1171 } 1172 } 1173 1174 static void mos6522_q800_via2_reset(DeviceState *dev) 1175 { 1176 MOS6522State *ms = MOS6522(dev); 1177 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 1178 1179 mdc->parent_reset(dev); 1180 1181 ms->timers[0].frequency = VIA_TIMER_FREQ; 1182 ms->timers[1].frequency = VIA_TIMER_FREQ; 1183 1184 ms->dirb = 0; 1185 ms->b = 0; 1186 } 1187 1188 static void mos6522_q800_via2_init(Object *obj) 1189 { 1190 qdev_init_gpio_in_named(DEVICE(obj), via2_irq_request, "via2-irq", 1191 VIA2_IRQ_NB); 1192 } 1193 1194 static const VMStateDescription vmstate_q800_via2 = { 1195 .name = "q800-via2", 1196 .version_id = 0, 1197 .minimum_version_id = 0, 1198 .fields = (VMStateField[]) { 1199 VMSTATE_STRUCT(parent_obj, MOS6522Q800VIA2State, 0, vmstate_mos6522, 1200 MOS6522State), 1201 VMSTATE_END_OF_LIST() 1202 } 1203 }; 1204 1205 static void mos6522_q800_via2_class_init(ObjectClass *oc, void *data) 1206 { 1207 DeviceClass *dc = DEVICE_CLASS(oc); 1208 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); 1209 1210 dc->reset = mos6522_q800_via2_reset; 1211 dc->vmsd = &vmstate_q800_via2; 1212 mdc->portB_write = mos6522_q800_via2_portB_write; 1213 } 1214 1215 static const TypeInfo mos6522_q800_via2_type_info = { 1216 .name = TYPE_MOS6522_Q800_VIA2, 1217 .parent = TYPE_MOS6522, 1218 .instance_size = sizeof(MOS6522Q800VIA2State), 1219 .instance_init = mos6522_q800_via2_init, 1220 .class_init = mos6522_q800_via2_class_init, 1221 }; 1222 1223 static void mac_via_register_types(void) 1224 { 1225 type_register_static(&mos6522_q800_via1_type_info); 1226 type_register_static(&mos6522_q800_via2_type_info); 1227 type_register_static(&mac_via_info); 1228 } 1229 1230 type_init(mac_via_register_types); 1231