1 /* 2 * QEMU m68k Macintosh VIA device support 3 * 4 * Copyright (c) 2011-2018 Laurent Vivier 5 * Copyright (c) 2018 Mark Cave-Ayland 6 * 7 * Some parts from hw/misc/macio/cuda.c 8 * 9 * Copyright (c) 2004-2007 Fabrice Bellard 10 * Copyright (c) 2007 Jocelyn Mayer 11 * 12 * some parts from linux-2.6.29, arch/m68k/include/asm/mac_via.h 13 * 14 * This work is licensed under the terms of the GNU GPL, version 2 or later. 15 * See the COPYING file in the top-level directory. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu-common.h" 20 #include "migration/vmstate.h" 21 #include "hw/sysbus.h" 22 #include "hw/irq.h" 23 #include "qemu/timer.h" 24 #include "hw/misc/mac_via.h" 25 #include "hw/misc/mos6522.h" 26 #include "hw/input/adb.h" 27 #include "sysemu/runstate.h" 28 #include "qapi/error.h" 29 #include "qemu/cutils.h" 30 #include "hw/qdev-properties.h" 31 #include "hw/qdev-properties-system.h" 32 #include "sysemu/block-backend.h" 33 #include "trace.h" 34 #include "qemu/log.h" 35 36 /* 37 * VIAs: There are two in every machine, 38 */ 39 40 #define VIA_SIZE (0x2000) 41 42 /* 43 * Not all of these are true post MacII I think. 44 * CSA: probably the ones CHRP marks as 'unused' change purposes 45 * when the IWM becomes the SWIM. 46 * http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html 47 * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf 48 * 49 * also, http://developer.apple.com/technotes/hw/hw_09.html claims the 50 * following changes for IIfx: 51 * VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP. 52 * Also, "All of the functionality of VIA2 has been moved to other chips". 53 */ 54 55 #define VIA1A_vSccWrReq 0x80 /* 56 * SCC write. (input) 57 * [CHRP] SCC WREQ: Reflects the state of the 58 * Wait/Request pins from the SCC. 59 * [Macintosh Family Hardware] 60 * as CHRP on SE/30,II,IIx,IIcx,IIci. 61 * on IIfx, "0 means an active request" 62 */ 63 #define VIA1A_vRev8 0x40 /* 64 * Revision 8 board ??? 65 * [CHRP] En WaitReqB: Lets the WaitReq_L 66 * signal from port B of the SCC appear on 67 * the PA7 input pin. Output. 68 * [Macintosh Family] On the SE/30, this 69 * is the bit to flip screen buffers. 70 * 0=alternate, 1=main. 71 * on II,IIx,IIcx,IIci,IIfx this is a bit 72 * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx 73 */ 74 #define VIA1A_vHeadSel 0x20 /* 75 * Head select for IWM. 76 * [CHRP] unused. 77 * [Macintosh Family] "Floppy disk 78 * state-control line SEL" on all but IIfx 79 */ 80 #define VIA1A_vOverlay 0x10 /* 81 * [Macintosh Family] On SE/30,II,IIx,IIcx 82 * this bit enables the "Overlay" address 83 * map in the address decoders as it is on 84 * reset for mapping the ROM over the reset 85 * vector. 1=use overlay map. 86 * On the IIci,IIfx it is another bit of the 87 * CPU ID: 0=normal IIci, 1=IIci with parity 88 * feature or IIfx. 89 * [CHRP] En WaitReqA: Lets the WaitReq_L 90 * signal from port A of the SCC appear 91 * on the PA7 input pin (CHRP). Output. 92 * [MkLinux] "Drive Select" 93 * (with 0x20 being 'disk head select') 94 */ 95 #define VIA1A_vSync 0x08 /* 96 * [CHRP] Sync Modem: modem clock select: 97 * 1: select the external serial clock to 98 * drive the SCC's /RTxCA pin. 99 * 0: Select the 3.6864MHz clock to drive 100 * the SCC cell. 101 * [Macintosh Family] Correct on all but IIfx 102 */ 103 104 /* 105 * Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control 106 * on Macs which had the PWM sound hardware. Reserved on newer models. 107 * On IIci,IIfx, bits 1-2 are the rest of the CPU ID: 108 * bit 2: 1=IIci, 0=IIfx 109 * bit 1: 1 on both IIci and IIfx. 110 * MkLinux sez bit 0 is 'burnin flag' in this case. 111 * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as 112 * inputs, these bits will read 0. 113 */ 114 #define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */ 115 #define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */ 116 #define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */ 117 #define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */ 118 #define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */ 119 120 /* 121 * Info on VIA1B is from Macintosh Family Hardware & MkLinux. 122 * CHRP offers no info. 123 */ 124 #define VIA1B_vSound 0x80 /* 125 * Sound enable (for compatibility with 126 * PWM hardware) 0=enabled. 127 * Also, on IIci w/parity, shows parity error 128 * 0=error, 1=OK. 129 */ 130 #define VIA1B_vMystery 0x40 /* 131 * On IIci, parity enable. 0=enabled,1=disabled 132 * On SE/30, vertical sync interrupt enable. 133 * 0=enabled. This vSync interrupt shows up 134 * as a slot $E interrupt. 135 */ 136 #define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */ 137 #define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */ 138 #define VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/ 139 #define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */ 140 #define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */ 141 #define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */ 142 143 /* 144 * VIA2 A register is the interrupt lines raised off the nubus 145 * slots. 146 * The below info is from 'Macintosh Family Hardware.' 147 * MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.' 148 * It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and 149 * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike. 150 * Perhaps OSS uses vRAM1 and vRAM2 for ADB. 151 */ 152 153 #define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */ 154 #define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */ 155 #define VIA2A_vIRQE 0x20 /* IRQ from slot $E */ 156 #define VIA2A_vIRQD 0x10 /* IRQ from slot $D */ 157 #define VIA2A_vIRQC 0x08 /* IRQ from slot $C */ 158 #define VIA2A_vIRQB 0x04 /* IRQ from slot $B */ 159 #define VIA2A_vIRQA 0x02 /* IRQ from slot $A */ 160 #define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */ 161 162 /* 163 * RAM size bits decoded as follows: 164 * bit1 bit0 size of ICs in bank A 165 * 0 0 256 kbit 166 * 0 1 1 Mbit 167 * 1 0 4 Mbit 168 * 1 1 16 Mbit 169 */ 170 171 /* 172 * Register B has the fun stuff in it 173 */ 174 175 #define VIA2B_vVBL 0x80 /* 176 * VBL output to VIA1 (60.15Hz) driven by 177 * timer T1. 178 * on IIci, parity test: 0=test mode. 179 * [MkLinux] RBV_PARODD: 1=odd,0=even. 180 */ 181 #define VIA2B_vSndJck 0x40 /* 182 * External sound jack status. 183 * 0=plug is inserted. On SE/30, always 0 184 */ 185 #define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */ 186 #define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */ 187 #define VIA2B_vMode32 0x08 /* 188 * 24/32bit switch - doubles as cache flush 189 * on II, AMU/PMMU control. 190 * if AMU, 0=24bit to 32bit translation 191 * if PMMU, 1=PMMU is accessing page table. 192 * on SE/30 tied low. 193 * on IIx,IIcx,IIfx, unused. 194 * on IIci/RBV, cache control. 0=flush cache. 195 */ 196 #define VIA2B_vPower 0x04 /* 197 * Power off, 0=shut off power. 198 * on SE/30 this signal sent to PDS card. 199 */ 200 #define VIA2B_vBusLk 0x02 /* 201 * Lock NuBus transactions, 0=locked. 202 * on SE/30 sent to PDS card. 203 */ 204 #define VIA2B_vCDis 0x01 /* 205 * Cache control. On IIci, 1=disable cache card 206 * on others, 0=disable processor's instruction 207 * and data caches. 208 */ 209 210 /* interrupt flags */ 211 212 #define IRQ_SET 0x80 213 214 /* common */ 215 216 #define VIA_IRQ_TIMER1 0x40 217 #define VIA_IRQ_TIMER2 0x20 218 219 /* 220 * Apple sez: http://developer.apple.com/technotes/ov/ov_04.html 221 * Another example of a valid function that has no ROM support is the use 222 * of the alternate video page for page-flipping animation. Since there 223 * is no ROM call to flip pages, it is necessary to go play with the 224 * right bit in the VIA chip (6522 Versatile Interface Adapter). 225 * [CSA: don't know which one this is, but it's one of 'em!] 226 */ 227 228 /* 229 * 6522 registers - see databook. 230 * CSA: Assignments for VIA1 confirmed from CHRP spec. 231 */ 232 233 /* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */ 234 /* Note: 15 VIA regs, 8 RBV regs */ 235 236 #define vBufB 0x0000 /* [VIA/RBV] Register B */ 237 #define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */ 238 #define vDirB 0x0400 /* [VIA only] Data Direction Register B. */ 239 #define vDirA 0x0600 /* [VIA only] Data Direction Register A. */ 240 #define vT1CL 0x0800 /* [VIA only] Timer one counter low. */ 241 #define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */ 242 #define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */ 243 #define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */ 244 #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ 245 #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ 246 #define vSR 0x1400 /* [VIA only] Shift register. */ 247 #define vACR 0x1600 /* [VIA only] Auxilary control register. */ 248 #define vPCR 0x1800 /* [VIA only] Peripheral control register. */ 249 /* 250 * CHRP sez never ever to *write* this. 251 * Mac family says never to *change* this. 252 * In fact we need to initialize it once at start. 253 */ 254 #define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */ 255 #define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */ 256 #define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */ 257 258 /* from linux 2.6 drivers/macintosh/via-macii.c */ 259 260 /* Bits in ACR */ 261 262 #define VIA1ACR_vShiftCtrl 0x1c /* Shift register control bits */ 263 #define VIA1ACR_vShiftExtClk 0x0c /* Shift on external clock */ 264 #define VIA1ACR_vShiftOut 0x10 /* Shift out if 1 */ 265 266 /* 267 * Apple Macintosh Family Hardware Refenece 268 * Table 19-10 ADB transaction states 269 */ 270 271 #define ADB_STATE_NEW 0 272 #define ADB_STATE_EVEN 1 273 #define ADB_STATE_ODD 2 274 #define ADB_STATE_IDLE 3 275 276 #define VIA1B_vADB_StateMask (VIA1B_vADBS1 | VIA1B_vADBS2) 277 #define VIA1B_vADB_StateShift 4 278 279 #define VIA_TIMER_FREQ (783360) 280 #define VIA_ADB_POLL_FREQ 50 /* XXX: not real */ 281 282 /* 283 * Guide to the Macintosh Family Hardware ch. 12 "Displays" p. 401 gives the 284 * precise 60Hz interrupt frequency as ~60.15Hz with a period of 16625.8 us 285 */ 286 #define VIA_60HZ_TIMER_PERIOD_NS 16625800 287 288 /* VIA returns time offset from Jan 1, 1904, not 1970 */ 289 #define RTC_OFFSET 2082844800 290 291 enum { 292 REG_0, 293 REG_1, 294 REG_2, 295 REG_3, 296 REG_TEST, 297 REG_WPROTECT, 298 REG_PRAM_ADDR, 299 REG_PRAM_ADDR_LAST = REG_PRAM_ADDR + 19, 300 REG_PRAM_SECT, 301 REG_PRAM_SECT_LAST = REG_PRAM_SECT + 7, 302 REG_INVALID, 303 REG_EMPTY = 0xff, 304 }; 305 306 static void via1_sixty_hz_update(MOS6522Q800VIA1State *v1s) 307 { 308 MOS6522State *s = MOS6522(v1s); 309 310 /* 60 Hz irq */ 311 v1s->next_sixty_hz = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 312 VIA_60HZ_TIMER_PERIOD_NS) / 313 VIA_60HZ_TIMER_PERIOD_NS * VIA_60HZ_TIMER_PERIOD_NS; 314 315 if (s->ier & VIA1_IRQ_60HZ) { 316 timer_mod(v1s->sixty_hz_timer, v1s->next_sixty_hz); 317 } else { 318 timer_del(v1s->sixty_hz_timer); 319 } 320 } 321 322 static void via1_one_second_update(MOS6522Q800VIA1State *v1s) 323 { 324 MOS6522State *s = MOS6522(v1s); 325 326 v1s->next_second = (qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000) / 327 1000 * 1000; 328 if (s->ier & VIA1_IRQ_ONE_SECOND) { 329 timer_mod(v1s->one_second_timer, v1s->next_second); 330 } else { 331 timer_del(v1s->one_second_timer); 332 } 333 } 334 335 static void via1_sixty_hz(void *opaque) 336 { 337 MOS6522Q800VIA1State *v1s = opaque; 338 MOS6522State *s = MOS6522(v1s); 339 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 340 341 s->ifr |= VIA1_IRQ_60HZ; 342 mdc->update_irq(s); 343 344 via1_sixty_hz_update(v1s); 345 } 346 347 static void via1_one_second(void *opaque) 348 { 349 MOS6522Q800VIA1State *v1s = opaque; 350 MOS6522State *s = MOS6522(v1s); 351 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 352 353 s->ifr |= VIA1_IRQ_ONE_SECOND; 354 mdc->update_irq(s); 355 356 via1_one_second_update(v1s); 357 } 358 359 static void via1_irq_request(void *opaque, int irq, int level) 360 { 361 MOS6522Q800VIA1State *v1s = opaque; 362 MOS6522State *s = MOS6522(v1s); 363 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 364 365 if (level) { 366 s->ifr |= 1 << irq; 367 } else { 368 s->ifr &= ~(1 << irq); 369 } 370 371 mdc->update_irq(s); 372 } 373 374 static void via2_irq_request(void *opaque, int irq, int level) 375 { 376 MOS6522Q800VIA2State *v2s = opaque; 377 MOS6522State *s = MOS6522(v2s); 378 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 379 380 if (level) { 381 s->ifr |= 1 << irq; 382 } else { 383 s->ifr &= ~(1 << irq); 384 } 385 386 mdc->update_irq(s); 387 } 388 389 390 static void pram_update(MacVIAState *m) 391 { 392 if (m->blk) { 393 if (blk_pwrite(m->blk, 0, m->mos6522_via1.PRAM, 394 sizeof(m->mos6522_via1.PRAM), 0) < 0) { 395 qemu_log("pram_update: cannot write to file\n"); 396 } 397 } 398 } 399 400 /* 401 * RTC Commands 402 * 403 * Command byte Register addressed by the command 404 * 405 * z0000001 Seconds register 0 (lowest-order byte) 406 * z0000101 Seconds register 1 407 * z0001001 Seconds register 2 408 * z0001101 Seconds register 3 (highest-order byte) 409 * 00110001 Test register (write-only) 410 * 00110101 Write-Protect Register (write-only) 411 * z010aa01 RAM address 100aa ($10-$13) (first 20 bytes only) 412 * z1aaaa01 RAM address 0aaaa ($00-$0F) (first 20 bytes only) 413 * z0111aaa Extended memory designator and sector number 414 * 415 * For a read request, z=1, for a write z=0 416 * The letter a indicates bits whose value depend on what parameter 417 * RAM byte you want to address 418 */ 419 static int via1_rtc_compact_cmd(uint8_t value) 420 { 421 uint8_t read = value & 0x80; 422 423 value &= 0x7f; 424 425 /* the last 2 bits of a command byte must always be 0b01 ... */ 426 if ((value & 0x78) == 0x38) { 427 /* except for the extended memory designator */ 428 return read | (REG_PRAM_SECT + (value & 0x07)); 429 } 430 if ((value & 0x03) == 0x01) { 431 value >>= 2; 432 if ((value & 0x1c) == 0) { 433 /* seconds registers */ 434 return read | (REG_0 + (value & 0x03)); 435 } else if ((value == 0x0c) && !read) { 436 return REG_TEST; 437 } else if ((value == 0x0d) && !read) { 438 return REG_WPROTECT; 439 } else if ((value & 0x1c) == 0x08) { 440 /* RAM address 0x10 to 0x13 */ 441 return read | (REG_PRAM_ADDR + 0x10 + (value & 0x03)); 442 } else if ((value & 0x43) == 0x41) { 443 /* RAM address 0x00 to 0x0f */ 444 return read | (REG_PRAM_ADDR + (value & 0x0f)); 445 } 446 } 447 return REG_INVALID; 448 } 449 450 static void via1_rtc_update(MacVIAState *m) 451 { 452 MOS6522Q800VIA1State *v1s = &m->mos6522_via1; 453 MOS6522State *s = MOS6522(v1s); 454 int cmd, sector, addr; 455 uint32_t time; 456 457 if (s->b & VIA1B_vRTCEnb) { 458 return; 459 } 460 461 if (s->dirb & VIA1B_vRTCData) { 462 /* send bits to the RTC */ 463 if (!(v1s->last_b & VIA1B_vRTCClk) && (s->b & VIA1B_vRTCClk)) { 464 m->data_out <<= 1; 465 m->data_out |= s->b & VIA1B_vRTCData; 466 m->data_out_cnt++; 467 } 468 trace_via1_rtc_update_data_out(m->data_out_cnt, m->data_out); 469 } else { 470 trace_via1_rtc_update_data_in(m->data_in_cnt, m->data_in); 471 /* receive bits from the RTC */ 472 if ((v1s->last_b & VIA1B_vRTCClk) && 473 !(s->b & VIA1B_vRTCClk) && 474 m->data_in_cnt) { 475 s->b = (s->b & ~VIA1B_vRTCData) | 476 ((m->data_in >> 7) & VIA1B_vRTCData); 477 m->data_in <<= 1; 478 m->data_in_cnt--; 479 } 480 return; 481 } 482 483 if (m->data_out_cnt != 8) { 484 return; 485 } 486 487 m->data_out_cnt = 0; 488 489 trace_via1_rtc_internal_status(m->cmd, m->alt, m->data_out); 490 /* first byte: it's a command */ 491 if (m->cmd == REG_EMPTY) { 492 493 cmd = via1_rtc_compact_cmd(m->data_out); 494 trace_via1_rtc_internal_cmd(cmd); 495 496 if (cmd == REG_INVALID) { 497 trace_via1_rtc_cmd_invalid(m->data_out); 498 return; 499 } 500 501 if (cmd & 0x80) { /* this is a read command */ 502 switch (cmd & 0x7f) { 503 case REG_0...REG_3: /* seconds registers */ 504 /* 505 * register 0 is lowest-order byte 506 * register 3 is highest-order byte 507 */ 508 509 time = m->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 510 / NANOSECONDS_PER_SECOND); 511 trace_via1_rtc_internal_time(time); 512 m->data_in = (time >> ((cmd & 0x03) << 3)) & 0xff; 513 m->data_in_cnt = 8; 514 trace_via1_rtc_cmd_seconds_read((cmd & 0x7f) - REG_0, 515 m->data_in); 516 break; 517 case REG_PRAM_ADDR...REG_PRAM_ADDR_LAST: 518 /* PRAM address 0x00 -> 0x13 */ 519 m->data_in = v1s->PRAM[(cmd & 0x7f) - REG_PRAM_ADDR]; 520 m->data_in_cnt = 8; 521 trace_via1_rtc_cmd_pram_read((cmd & 0x7f) - REG_PRAM_ADDR, 522 m->data_in); 523 break; 524 case REG_PRAM_SECT...REG_PRAM_SECT_LAST: 525 /* 526 * extended memory designator and sector number 527 * the only two-byte read command 528 */ 529 trace_via1_rtc_internal_set_cmd(cmd); 530 m->cmd = cmd; 531 break; 532 default: 533 g_assert_not_reached(); 534 break; 535 } 536 return; 537 } 538 539 /* this is a write command, needs a parameter */ 540 if (cmd == REG_WPROTECT || !m->wprotect) { 541 trace_via1_rtc_internal_set_cmd(cmd); 542 m->cmd = cmd; 543 } else { 544 trace_via1_rtc_internal_ignore_cmd(cmd); 545 } 546 return; 547 } 548 549 /* second byte: it's a parameter */ 550 if (m->alt == REG_EMPTY) { 551 switch (m->cmd & 0x7f) { 552 case REG_0...REG_3: /* seconds register */ 553 /* FIXME */ 554 trace_via1_rtc_cmd_seconds_write(m->cmd - REG_0, m->data_out); 555 m->cmd = REG_EMPTY; 556 break; 557 case REG_TEST: 558 /* device control: nothing to do */ 559 trace_via1_rtc_cmd_test_write(m->data_out); 560 m->cmd = REG_EMPTY; 561 break; 562 case REG_WPROTECT: 563 /* Write Protect register */ 564 trace_via1_rtc_cmd_wprotect_write(m->data_out); 565 m->wprotect = !!(m->data_out & 0x80); 566 m->cmd = REG_EMPTY; 567 break; 568 case REG_PRAM_ADDR...REG_PRAM_ADDR_LAST: 569 /* PRAM address 0x00 -> 0x13 */ 570 trace_via1_rtc_cmd_pram_write(m->cmd - REG_PRAM_ADDR, m->data_out); 571 v1s->PRAM[m->cmd - REG_PRAM_ADDR] = m->data_out; 572 pram_update(m); 573 m->cmd = REG_EMPTY; 574 break; 575 case REG_PRAM_SECT...REG_PRAM_SECT_LAST: 576 addr = (m->data_out >> 2) & 0x1f; 577 sector = (m->cmd & 0x7f) - REG_PRAM_SECT; 578 if (m->cmd & 0x80) { 579 /* it's a read */ 580 m->data_in = v1s->PRAM[sector * 32 + addr]; 581 m->data_in_cnt = 8; 582 trace_via1_rtc_cmd_pram_sect_read(sector, addr, 583 sector * 32 + addr, 584 m->data_in); 585 m->cmd = REG_EMPTY; 586 } else { 587 /* it's a write, we need one more parameter */ 588 trace_via1_rtc_internal_set_alt(addr, sector, addr); 589 m->alt = addr; 590 } 591 break; 592 default: 593 g_assert_not_reached(); 594 break; 595 } 596 return; 597 } 598 599 /* third byte: it's the data of a REG_PRAM_SECT write */ 600 g_assert(REG_PRAM_SECT <= m->cmd && m->cmd <= REG_PRAM_SECT_LAST); 601 sector = m->cmd - REG_PRAM_SECT; 602 v1s->PRAM[sector * 32 + m->alt] = m->data_out; 603 pram_update(m); 604 trace_via1_rtc_cmd_pram_sect_write(sector, m->alt, sector * 32 + m->alt, 605 m->data_out); 606 m->alt = REG_EMPTY; 607 m->cmd = REG_EMPTY; 608 } 609 610 static void adb_via_poll(void *opaque) 611 { 612 MacVIAState *m = opaque; 613 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&m->mos6522_via1); 614 MOS6522State *s = MOS6522(v1s); 615 ADBBusState *adb_bus = &m->adb_bus; 616 uint8_t obuf[9]; 617 uint8_t *data = &s->sr; 618 int olen; 619 620 /* 621 * Setting vADBInt below indicates that an autopoll reply has been 622 * received, however we must block autopoll until the point where 623 * the entire reply has been read back to the host 624 */ 625 adb_autopoll_block(adb_bus); 626 627 if (m->adb_data_in_size > 0 && m->adb_data_in_index == 0) { 628 /* 629 * For older Linux kernels that switch to IDLE mode after sending the 630 * ADB command, detect if there is an existing response and return that 631 * as a a "fake" autopoll reply or bus timeout accordingly 632 */ 633 *data = m->adb_data_out[0]; 634 olen = m->adb_data_in_size; 635 636 s->b &= ~VIA1B_vADBInt; 637 qemu_irq_raise(m->adb_data_ready); 638 } else { 639 /* 640 * Otherwise poll as normal 641 */ 642 m->adb_data_in_index = 0; 643 m->adb_data_out_index = 0; 644 olen = adb_poll(adb_bus, obuf, adb_bus->autopoll_mask); 645 646 if (olen > 0) { 647 /* Autopoll response */ 648 *data = obuf[0]; 649 olen--; 650 memcpy(m->adb_data_in, &obuf[1], olen); 651 m->adb_data_in_size = olen; 652 653 s->b &= ~VIA1B_vADBInt; 654 qemu_irq_raise(m->adb_data_ready); 655 } else { 656 *data = m->adb_autopoll_cmd; 657 obuf[0] = 0xff; 658 obuf[1] = 0xff; 659 olen = 2; 660 661 memcpy(m->adb_data_in, obuf, olen); 662 m->adb_data_in_size = olen; 663 664 s->b &= ~VIA1B_vADBInt; 665 qemu_irq_raise(m->adb_data_ready); 666 } 667 } 668 669 trace_via1_adb_poll(*data, (s->b & VIA1B_vADBInt) ? "+" : "-", 670 adb_bus->status, m->adb_data_in_index, olen); 671 } 672 673 static int adb_via_send_len(uint8_t data) 674 { 675 /* Determine the send length from the given ADB command */ 676 uint8_t cmd = data & 0xc; 677 uint8_t reg = data & 0x3; 678 679 switch (cmd) { 680 case 0x8: 681 /* Listen command */ 682 switch (reg) { 683 case 2: 684 /* Register 2 is only used for the keyboard */ 685 return 3; 686 case 3: 687 /* 688 * Fortunately our devices only implement writes 689 * to register 3 which is fixed at 2 bytes 690 */ 691 return 3; 692 default: 693 qemu_log_mask(LOG_UNIMP, "ADB unknown length for register %d\n", 694 reg); 695 return 1; 696 } 697 default: 698 /* Talk, BusReset */ 699 return 1; 700 } 701 } 702 703 static void adb_via_send(MacVIAState *s, int state, uint8_t data) 704 { 705 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&s->mos6522_via1); 706 MOS6522State *ms = MOS6522(v1s); 707 ADBBusState *adb_bus = &s->adb_bus; 708 uint16_t autopoll_mask; 709 710 switch (state) { 711 case ADB_STATE_NEW: 712 /* 713 * Command byte: vADBInt tells host autopoll data already present 714 * in VIA shift register and ADB transceiver 715 */ 716 adb_autopoll_block(adb_bus); 717 718 if (adb_bus->status & ADB_STATUS_POLLREPLY) { 719 /* Tell the host the existing data is from autopoll */ 720 ms->b &= ~VIA1B_vADBInt; 721 } else { 722 ms->b |= VIA1B_vADBInt; 723 s->adb_data_out_index = 0; 724 s->adb_data_out[s->adb_data_out_index++] = data; 725 } 726 727 trace_via1_adb_send(" NEW", data, (ms->b & VIA1B_vADBInt) ? "+" : "-"); 728 qemu_irq_raise(s->adb_data_ready); 729 break; 730 731 case ADB_STATE_EVEN: 732 case ADB_STATE_ODD: 733 ms->b |= VIA1B_vADBInt; 734 s->adb_data_out[s->adb_data_out_index++] = data; 735 736 trace_via1_adb_send(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 737 data, (ms->b & VIA1B_vADBInt) ? "+" : "-"); 738 qemu_irq_raise(s->adb_data_ready); 739 break; 740 741 case ADB_STATE_IDLE: 742 return; 743 } 744 745 /* If the command is complete, execute it */ 746 if (s->adb_data_out_index == adb_via_send_len(s->adb_data_out[0])) { 747 s->adb_data_in_size = adb_request(adb_bus, s->adb_data_in, 748 s->adb_data_out, 749 s->adb_data_out_index); 750 s->adb_data_in_index = 0; 751 752 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 753 /* 754 * Bus timeout (but allow first EVEN and ODD byte to indicate 755 * timeout via vADBInt and SRQ status) 756 */ 757 s->adb_data_in[0] = 0xff; 758 s->adb_data_in[1] = 0xff; 759 s->adb_data_in_size = 2; 760 } 761 762 /* 763 * If last command is TALK, store it for use by autopoll and adjust 764 * the autopoll mask accordingly 765 */ 766 if ((s->adb_data_out[0] & 0xc) == 0xc) { 767 s->adb_autopoll_cmd = s->adb_data_out[0]; 768 769 autopoll_mask = 1 << (s->adb_autopoll_cmd >> 4); 770 adb_set_autopoll_mask(adb_bus, autopoll_mask); 771 } 772 } 773 } 774 775 static void adb_via_receive(MacVIAState *s, int state, uint8_t *data) 776 { 777 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&s->mos6522_via1); 778 MOS6522State *ms = MOS6522(v1s); 779 ADBBusState *adb_bus = &s->adb_bus; 780 uint16_t pending; 781 782 switch (state) { 783 case ADB_STATE_NEW: 784 ms->b |= VIA1B_vADBInt; 785 return; 786 787 case ADB_STATE_IDLE: 788 ms->b |= VIA1B_vADBInt; 789 adb_autopoll_unblock(adb_bus); 790 791 trace_via1_adb_receive("IDLE", *data, 792 (ms->b & VIA1B_vADBInt) ? "+" : "-", adb_bus->status, 793 s->adb_data_in_index, s->adb_data_in_size); 794 795 break; 796 797 case ADB_STATE_EVEN: 798 case ADB_STATE_ODD: 799 switch (s->adb_data_in_index) { 800 case 0: 801 /* First EVEN byte: vADBInt indicates bus timeout */ 802 *data = s->adb_data_in[s->adb_data_in_index]; 803 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 804 ms->b &= ~VIA1B_vADBInt; 805 } else { 806 ms->b |= VIA1B_vADBInt; 807 } 808 809 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 810 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 811 adb_bus->status, s->adb_data_in_index, 812 s->adb_data_in_size); 813 814 s->adb_data_in_index++; 815 break; 816 817 case 1: 818 /* First ODD byte: vADBInt indicates SRQ */ 819 *data = s->adb_data_in[s->adb_data_in_index]; 820 pending = adb_bus->pending & ~(1 << (s->adb_autopoll_cmd >> 4)); 821 if (pending) { 822 ms->b &= ~VIA1B_vADBInt; 823 } else { 824 ms->b |= VIA1B_vADBInt; 825 } 826 827 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 828 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 829 adb_bus->status, s->adb_data_in_index, 830 s->adb_data_in_size); 831 832 s->adb_data_in_index++; 833 break; 834 835 default: 836 /* 837 * Otherwise vADBInt indicates end of data. Note that Linux 838 * specifically checks for the sequence 0x0 0xff to confirm the 839 * end of the poll reply, so provide these extra bytes below to 840 * keep it happy 841 */ 842 if (s->adb_data_in_index < s->adb_data_in_size) { 843 /* Next data byte */ 844 *data = s->adb_data_in[s->adb_data_in_index]; 845 ms->b |= VIA1B_vADBInt; 846 } else if (s->adb_data_in_index == s->adb_data_in_size) { 847 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 848 /* Bus timeout (no more data) */ 849 *data = 0xff; 850 } else { 851 /* Return 0x0 after reply */ 852 *data = 0; 853 } 854 ms->b &= ~VIA1B_vADBInt; 855 } else { 856 /* Bus timeout (no more data) */ 857 *data = 0xff; 858 ms->b &= ~VIA1B_vADBInt; 859 adb_bus->status = 0; 860 adb_autopoll_unblock(adb_bus); 861 } 862 863 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 864 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 865 adb_bus->status, s->adb_data_in_index, 866 s->adb_data_in_size); 867 868 if (s->adb_data_in_index <= s->adb_data_in_size) { 869 s->adb_data_in_index++; 870 } 871 break; 872 } 873 874 qemu_irq_raise(s->adb_data_ready); 875 break; 876 } 877 } 878 879 static void via1_adb_update(MacVIAState *m) 880 { 881 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&m->mos6522_via1); 882 MOS6522State *s = MOS6522(v1s); 883 int oldstate, state; 884 885 oldstate = (v1s->last_b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; 886 state = (s->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; 887 888 if (state != oldstate) { 889 if (s->acr & VIA1ACR_vShiftOut) { 890 /* output mode */ 891 adb_via_send(m, state, s->sr); 892 } else { 893 /* input mode */ 894 adb_via_receive(m, state, &s->sr); 895 } 896 } 897 } 898 899 static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size) 900 { 901 MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque); 902 MOS6522State *ms = MOS6522(s); 903 int64_t now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); 904 905 /* 906 * If IRQs are disabled, timers are disabled, but we need to update 907 * VIA1_IRQ_60HZ and VIA1_IRQ_ONE_SECOND bits in the IFR 908 */ 909 910 if (now >= s->next_sixty_hz) { 911 ms->ifr |= VIA1_IRQ_60HZ; 912 via1_sixty_hz_update(s); 913 } 914 if (now >= s->next_second) { 915 ms->ifr |= VIA1_IRQ_ONE_SECOND; 916 via1_one_second_update(s); 917 } 918 919 addr = (addr >> 9) & 0xf; 920 return mos6522_read(ms, addr, size); 921 } 922 923 static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val, 924 unsigned size) 925 { 926 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 927 MacVIAState *m = container_of(v1s, MacVIAState, mos6522_via1); 928 MOS6522State *ms = MOS6522(v1s); 929 930 addr = (addr >> 9) & 0xf; 931 mos6522_write(ms, addr, val, size); 932 933 switch (addr) { 934 case VIA_REG_B: 935 via1_rtc_update(m); 936 via1_adb_update(m); 937 938 v1s->last_b = ms->b; 939 break; 940 } 941 942 via1_one_second_update(v1s); 943 via1_sixty_hz_update(v1s); 944 } 945 946 static const MemoryRegionOps mos6522_q800_via1_ops = { 947 .read = mos6522_q800_via1_read, 948 .write = mos6522_q800_via1_write, 949 .endianness = DEVICE_BIG_ENDIAN, 950 .valid = { 951 .min_access_size = 1, 952 .max_access_size = 4, 953 }, 954 }; 955 956 static uint64_t mos6522_q800_via2_read(void *opaque, hwaddr addr, unsigned size) 957 { 958 MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque); 959 MOS6522State *ms = MOS6522(s); 960 961 addr = (addr >> 9) & 0xf; 962 return mos6522_read(ms, addr, size); 963 } 964 965 static void mos6522_q800_via2_write(void *opaque, hwaddr addr, uint64_t val, 966 unsigned size) 967 { 968 MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque); 969 MOS6522State *ms = MOS6522(s); 970 971 addr = (addr >> 9) & 0xf; 972 mos6522_write(ms, addr, val, size); 973 } 974 975 static const MemoryRegionOps mos6522_q800_via2_ops = { 976 .read = mos6522_q800_via2_read, 977 .write = mos6522_q800_via2_write, 978 .endianness = DEVICE_BIG_ENDIAN, 979 .valid = { 980 .min_access_size = 1, 981 .max_access_size = 4, 982 }, 983 }; 984 985 static void mac_via_reset(DeviceState *dev) 986 { 987 MacVIAState *m = MAC_VIA(dev); 988 MOS6522Q800VIA1State *v1s = &m->mos6522_via1; 989 ADBBusState *adb_bus = &m->adb_bus; 990 991 adb_set_autopoll_enabled(adb_bus, true); 992 993 timer_del(v1s->sixty_hz_timer); 994 v1s->next_sixty_hz = 0; 995 timer_del(v1s->one_second_timer); 996 v1s->next_second = 0; 997 998 m->cmd = REG_EMPTY; 999 m->alt = REG_EMPTY; 1000 } 1001 1002 static void mac_via_realize(DeviceState *dev, Error **errp) 1003 { 1004 MacVIAState *m = MAC_VIA(dev); 1005 MOS6522State *ms; 1006 ADBBusState *adb_bus = &m->adb_bus; 1007 struct tm tm; 1008 int ret; 1009 1010 /* Init VIAs 1 and 2 */ 1011 object_initialize_child(OBJECT(dev), "via1", &m->mos6522_via1, 1012 TYPE_MOS6522_Q800_VIA1); 1013 1014 object_initialize_child(OBJECT(dev), "via2", &m->mos6522_via2, 1015 TYPE_MOS6522_Q800_VIA2); 1016 1017 /* Pass through mos6522 output IRQs */ 1018 ms = MOS6522(&m->mos6522_via1); 1019 object_property_add_alias(OBJECT(dev), "irq[0]", OBJECT(ms), 1020 SYSBUS_DEVICE_GPIO_IRQ "[0]"); 1021 ms = MOS6522(&m->mos6522_via2); 1022 object_property_add_alias(OBJECT(dev), "irq[1]", OBJECT(ms), 1023 SYSBUS_DEVICE_GPIO_IRQ "[0]"); 1024 1025 sysbus_realize(SYS_BUS_DEVICE(&m->mos6522_via1), &error_abort); 1026 sysbus_realize(SYS_BUS_DEVICE(&m->mos6522_via2), &error_abort); 1027 1028 /* Pass through mos6522 input IRQs */ 1029 qdev_pass_gpios(DEVICE(&m->mos6522_via1), dev, "via1-irq"); 1030 qdev_pass_gpios(DEVICE(&m->mos6522_via2), dev, "via2-irq"); 1031 1032 /* VIA 1 */ 1033 m->mos6522_via1.one_second_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 1034 via1_one_second, 1035 &m->mos6522_via1); 1036 m->mos6522_via1.sixty_hz_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1037 via1_sixty_hz, 1038 &m->mos6522_via1); 1039 1040 qemu_get_timedate(&tm, 0); 1041 m->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; 1042 1043 adb_register_autopoll_callback(adb_bus, adb_via_poll, m); 1044 m->adb_data_ready = qdev_get_gpio_in_named(dev, "via1-irq", 1045 VIA1_IRQ_ADB_READY_BIT); 1046 1047 if (m->blk) { 1048 int64_t len = blk_getlength(m->blk); 1049 if (len < 0) { 1050 error_setg_errno(errp, -len, 1051 "could not get length of backing image"); 1052 return; 1053 } 1054 ret = blk_set_perm(m->blk, 1055 BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, 1056 BLK_PERM_ALL, errp); 1057 if (ret < 0) { 1058 return; 1059 } 1060 1061 len = blk_pread(m->blk, 0, m->mos6522_via1.PRAM, 1062 sizeof(m->mos6522_via1.PRAM)); 1063 if (len != sizeof(m->mos6522_via1.PRAM)) { 1064 error_setg(errp, "can't read PRAM contents"); 1065 return; 1066 } 1067 } 1068 } 1069 1070 static void mac_via_init(Object *obj) 1071 { 1072 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1073 MacVIAState *m = MAC_VIA(obj); 1074 1075 /* MMIO */ 1076 memory_region_init(&m->mmio, obj, "mac-via", 2 * VIA_SIZE); 1077 sysbus_init_mmio(sbd, &m->mmio); 1078 1079 memory_region_init_io(&m->via1mem, obj, &mos6522_q800_via1_ops, 1080 &m->mos6522_via1, "via1", VIA_SIZE); 1081 memory_region_add_subregion(&m->mmio, 0x0, &m->via1mem); 1082 1083 memory_region_init_io(&m->via2mem, obj, &mos6522_q800_via2_ops, 1084 &m->mos6522_via2, "via2", VIA_SIZE); 1085 memory_region_add_subregion(&m->mmio, VIA_SIZE, &m->via2mem); 1086 1087 /* ADB */ 1088 qbus_create_inplace((BusState *)&m->adb_bus, sizeof(m->adb_bus), 1089 TYPE_ADB_BUS, DEVICE(obj), "adb.0"); 1090 } 1091 1092 static void postload_update_cb(void *opaque, bool running, RunState state) 1093 { 1094 MacVIAState *m = MAC_VIA(opaque); 1095 1096 qemu_del_vm_change_state_handler(m->vmstate); 1097 m->vmstate = NULL; 1098 1099 pram_update(m); 1100 } 1101 1102 static int mac_via_post_load(void *opaque, int version_id) 1103 { 1104 MacVIAState *m = MAC_VIA(opaque); 1105 1106 if (m->blk) { 1107 m->vmstate = qemu_add_vm_change_state_handler(postload_update_cb, 1108 m); 1109 } 1110 1111 return 0; 1112 } 1113 1114 static const VMStateDescription vmstate_mac_via = { 1115 .name = "mac-via", 1116 .version_id = 2, 1117 .minimum_version_id = 2, 1118 .post_load = mac_via_post_load, 1119 .fields = (VMStateField[]) { 1120 /* VIAs */ 1121 VMSTATE_STRUCT(mos6522_via1.parent_obj, MacVIAState, 0, vmstate_mos6522, 1122 MOS6522State), 1123 VMSTATE_UINT8(mos6522_via1.last_b, MacVIAState), 1124 VMSTATE_BUFFER(mos6522_via1.PRAM, MacVIAState), 1125 VMSTATE_TIMER_PTR(mos6522_via1.one_second_timer, MacVIAState), 1126 VMSTATE_INT64(mos6522_via1.next_second, MacVIAState), 1127 VMSTATE_TIMER_PTR(mos6522_via1.sixty_hz_timer, MacVIAState), 1128 VMSTATE_INT64(mos6522_via1.next_sixty_hz, MacVIAState), 1129 VMSTATE_STRUCT(mos6522_via2.parent_obj, MacVIAState, 0, vmstate_mos6522, 1130 MOS6522State), 1131 /* RTC */ 1132 VMSTATE_UINT32(tick_offset, MacVIAState), 1133 VMSTATE_UINT8(data_out, MacVIAState), 1134 VMSTATE_INT32(data_out_cnt, MacVIAState), 1135 VMSTATE_UINT8(data_in, MacVIAState), 1136 VMSTATE_UINT8(data_in_cnt, MacVIAState), 1137 VMSTATE_UINT8(cmd, MacVIAState), 1138 VMSTATE_INT32(wprotect, MacVIAState), 1139 VMSTATE_INT32(alt, MacVIAState), 1140 /* ADB */ 1141 VMSTATE_INT32(adb_data_in_size, MacVIAState), 1142 VMSTATE_INT32(adb_data_in_index, MacVIAState), 1143 VMSTATE_INT32(adb_data_out_index, MacVIAState), 1144 VMSTATE_BUFFER(adb_data_in, MacVIAState), 1145 VMSTATE_BUFFER(adb_data_out, MacVIAState), 1146 VMSTATE_UINT8(adb_autopoll_cmd, MacVIAState), 1147 VMSTATE_END_OF_LIST() 1148 } 1149 }; 1150 1151 static Property mac_via_properties[] = { 1152 DEFINE_PROP_DRIVE("drive", MacVIAState, blk), 1153 DEFINE_PROP_END_OF_LIST(), 1154 }; 1155 1156 static void mac_via_class_init(ObjectClass *oc, void *data) 1157 { 1158 DeviceClass *dc = DEVICE_CLASS(oc); 1159 1160 dc->realize = mac_via_realize; 1161 dc->reset = mac_via_reset; 1162 dc->vmsd = &vmstate_mac_via; 1163 device_class_set_props(dc, mac_via_properties); 1164 } 1165 1166 static TypeInfo mac_via_info = { 1167 .name = TYPE_MAC_VIA, 1168 .parent = TYPE_SYS_BUS_DEVICE, 1169 .instance_size = sizeof(MacVIAState), 1170 .instance_init = mac_via_init, 1171 .class_init = mac_via_class_init, 1172 }; 1173 1174 /* VIA 1 */ 1175 static void mos6522_q800_via1_reset(DeviceState *dev) 1176 { 1177 MOS6522State *ms = MOS6522(dev); 1178 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 1179 1180 mdc->parent_reset(dev); 1181 1182 ms->timers[0].frequency = VIA_TIMER_FREQ; 1183 ms->timers[1].frequency = VIA_TIMER_FREQ; 1184 1185 ms->b = VIA1B_vADB_StateMask | VIA1B_vADBInt | VIA1B_vRTCEnb; 1186 } 1187 1188 static void mos6522_q800_via1_init(Object *obj) 1189 { 1190 qdev_init_gpio_in_named(DEVICE(obj), via1_irq_request, "via1-irq", 1191 VIA1_IRQ_NB); 1192 } 1193 1194 static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data) 1195 { 1196 DeviceClass *dc = DEVICE_CLASS(oc); 1197 1198 dc->reset = mos6522_q800_via1_reset; 1199 } 1200 1201 static const TypeInfo mos6522_q800_via1_type_info = { 1202 .name = TYPE_MOS6522_Q800_VIA1, 1203 .parent = TYPE_MOS6522, 1204 .instance_size = sizeof(MOS6522Q800VIA1State), 1205 .instance_init = mos6522_q800_via1_init, 1206 .class_init = mos6522_q800_via1_class_init, 1207 }; 1208 1209 /* VIA 2 */ 1210 static void mos6522_q800_via2_portB_write(MOS6522State *s) 1211 { 1212 if (s->dirb & VIA2B_vPower && (s->b & VIA2B_vPower) == 0) { 1213 /* shutdown */ 1214 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 1215 } 1216 } 1217 1218 static void mos6522_q800_via2_reset(DeviceState *dev) 1219 { 1220 MOS6522State *ms = MOS6522(dev); 1221 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 1222 1223 mdc->parent_reset(dev); 1224 1225 ms->timers[0].frequency = VIA_TIMER_FREQ; 1226 ms->timers[1].frequency = VIA_TIMER_FREQ; 1227 1228 ms->dirb = 0; 1229 ms->b = 0; 1230 } 1231 1232 static void mos6522_q800_via2_init(Object *obj) 1233 { 1234 qdev_init_gpio_in_named(DEVICE(obj), via2_irq_request, "via2-irq", 1235 VIA2_IRQ_NB); 1236 } 1237 1238 static void mos6522_q800_via2_class_init(ObjectClass *oc, void *data) 1239 { 1240 DeviceClass *dc = DEVICE_CLASS(oc); 1241 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); 1242 1243 dc->reset = mos6522_q800_via2_reset; 1244 mdc->portB_write = mos6522_q800_via2_portB_write; 1245 } 1246 1247 static const TypeInfo mos6522_q800_via2_type_info = { 1248 .name = TYPE_MOS6522_Q800_VIA2, 1249 .parent = TYPE_MOS6522, 1250 .instance_size = sizeof(MOS6522Q800VIA2State), 1251 .instance_init = mos6522_q800_via2_init, 1252 .class_init = mos6522_q800_via2_class_init, 1253 }; 1254 1255 static void mac_via_register_types(void) 1256 { 1257 type_register_static(&mos6522_q800_via1_type_info); 1258 type_register_static(&mos6522_q800_via2_type_info); 1259 type_register_static(&mac_via_info); 1260 } 1261 1262 type_init(mac_via_register_types); 1263