1 /* 2 * QEMU m68k Macintosh VIA device support 3 * 4 * Copyright (c) 2011-2018 Laurent Vivier 5 * Copyright (c) 2018 Mark Cave-Ayland 6 * 7 * Some parts from hw/misc/macio/cuda.c 8 * 9 * Copyright (c) 2004-2007 Fabrice Bellard 10 * Copyright (c) 2007 Jocelyn Mayer 11 * 12 * some parts from linux-2.6.29, arch/m68k/include/asm/mac_via.h 13 * 14 * This work is licensed under the terms of the GNU GPL, version 2 or later. 15 * See the COPYING file in the top-level directory. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu-common.h" 20 #include "migration/vmstate.h" 21 #include "hw/sysbus.h" 22 #include "hw/irq.h" 23 #include "qemu/timer.h" 24 #include "hw/misc/mac_via.h" 25 #include "hw/misc/mos6522.h" 26 #include "hw/input/adb.h" 27 #include "sysemu/runstate.h" 28 #include "qapi/error.h" 29 #include "qemu/cutils.h" 30 #include "hw/qdev-properties.h" 31 #include "hw/qdev-properties-system.h" 32 #include "sysemu/block-backend.h" 33 #include "trace.h" 34 #include "qemu/log.h" 35 36 /* 37 * VIAs: There are two in every machine, 38 */ 39 40 #define VIA_SIZE (0x2000) 41 42 /* 43 * Not all of these are true post MacII I think. 44 * CSA: probably the ones CHRP marks as 'unused' change purposes 45 * when the IWM becomes the SWIM. 46 * http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html 47 * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf 48 * 49 * also, http://developer.apple.com/technotes/hw/hw_09.html claims the 50 * following changes for IIfx: 51 * VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP. 52 * Also, "All of the functionality of VIA2 has been moved to other chips". 53 */ 54 55 #define VIA1A_vSccWrReq 0x80 /* 56 * SCC write. (input) 57 * [CHRP] SCC WREQ: Reflects the state of the 58 * Wait/Request pins from the SCC. 59 * [Macintosh Family Hardware] 60 * as CHRP on SE/30,II,IIx,IIcx,IIci. 61 * on IIfx, "0 means an active request" 62 */ 63 #define VIA1A_vRev8 0x40 /* 64 * Revision 8 board ??? 65 * [CHRP] En WaitReqB: Lets the WaitReq_L 66 * signal from port B of the SCC appear on 67 * the PA7 input pin. Output. 68 * [Macintosh Family] On the SE/30, this 69 * is the bit to flip screen buffers. 70 * 0=alternate, 1=main. 71 * on II,IIx,IIcx,IIci,IIfx this is a bit 72 * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx 73 */ 74 #define VIA1A_vHeadSel 0x20 /* 75 * Head select for IWM. 76 * [CHRP] unused. 77 * [Macintosh Family] "Floppy disk 78 * state-control line SEL" on all but IIfx 79 */ 80 #define VIA1A_vOverlay 0x10 /* 81 * [Macintosh Family] On SE/30,II,IIx,IIcx 82 * this bit enables the "Overlay" address 83 * map in the address decoders as it is on 84 * reset for mapping the ROM over the reset 85 * vector. 1=use overlay map. 86 * On the IIci,IIfx it is another bit of the 87 * CPU ID: 0=normal IIci, 1=IIci with parity 88 * feature or IIfx. 89 * [CHRP] En WaitReqA: Lets the WaitReq_L 90 * signal from port A of the SCC appear 91 * on the PA7 input pin (CHRP). Output. 92 * [MkLinux] "Drive Select" 93 * (with 0x20 being 'disk head select') 94 */ 95 #define VIA1A_vSync 0x08 /* 96 * [CHRP] Sync Modem: modem clock select: 97 * 1: select the external serial clock to 98 * drive the SCC's /RTxCA pin. 99 * 0: Select the 3.6864MHz clock to drive 100 * the SCC cell. 101 * [Macintosh Family] Correct on all but IIfx 102 */ 103 104 /* 105 * Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control 106 * on Macs which had the PWM sound hardware. Reserved on newer models. 107 * On IIci,IIfx, bits 1-2 are the rest of the CPU ID: 108 * bit 2: 1=IIci, 0=IIfx 109 * bit 1: 1 on both IIci and IIfx. 110 * MkLinux sez bit 0 is 'burnin flag' in this case. 111 * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as 112 * inputs, these bits will read 0. 113 */ 114 #define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */ 115 #define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */ 116 #define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */ 117 #define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */ 118 #define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */ 119 120 /* 121 * Info on VIA1B is from Macintosh Family Hardware & MkLinux. 122 * CHRP offers no info. 123 */ 124 #define VIA1B_vSound 0x80 /* 125 * Sound enable (for compatibility with 126 * PWM hardware) 0=enabled. 127 * Also, on IIci w/parity, shows parity error 128 * 0=error, 1=OK. 129 */ 130 #define VIA1B_vMystery 0x40 /* 131 * On IIci, parity enable. 0=enabled,1=disabled 132 * On SE/30, vertical sync interrupt enable. 133 * 0=enabled. This vSync interrupt shows up 134 * as a slot $E interrupt. 135 */ 136 #define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */ 137 #define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */ 138 #define VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/ 139 #define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */ 140 #define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */ 141 #define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */ 142 143 /* 144 * VIA2 A register is the interrupt lines raised off the nubus 145 * slots. 146 * The below info is from 'Macintosh Family Hardware.' 147 * MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.' 148 * It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and 149 * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike. 150 * Perhaps OSS uses vRAM1 and vRAM2 for ADB. 151 */ 152 153 #define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */ 154 #define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */ 155 #define VIA2A_vIRQE 0x20 /* IRQ from slot $E */ 156 #define VIA2A_vIRQD 0x10 /* IRQ from slot $D */ 157 #define VIA2A_vIRQC 0x08 /* IRQ from slot $C */ 158 #define VIA2A_vIRQB 0x04 /* IRQ from slot $B */ 159 #define VIA2A_vIRQA 0x02 /* IRQ from slot $A */ 160 #define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */ 161 162 /* 163 * RAM size bits decoded as follows: 164 * bit1 bit0 size of ICs in bank A 165 * 0 0 256 kbit 166 * 0 1 1 Mbit 167 * 1 0 4 Mbit 168 * 1 1 16 Mbit 169 */ 170 171 /* 172 * Register B has the fun stuff in it 173 */ 174 175 #define VIA2B_vVBL 0x80 /* 176 * VBL output to VIA1 (60.15Hz) driven by 177 * timer T1. 178 * on IIci, parity test: 0=test mode. 179 * [MkLinux] RBV_PARODD: 1=odd,0=even. 180 */ 181 #define VIA2B_vSndJck 0x40 /* 182 * External sound jack status. 183 * 0=plug is inserted. On SE/30, always 0 184 */ 185 #define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */ 186 #define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */ 187 #define VIA2B_vMode32 0x08 /* 188 * 24/32bit switch - doubles as cache flush 189 * on II, AMU/PMMU control. 190 * if AMU, 0=24bit to 32bit translation 191 * if PMMU, 1=PMMU is accessing page table. 192 * on SE/30 tied low. 193 * on IIx,IIcx,IIfx, unused. 194 * on IIci/RBV, cache control. 0=flush cache. 195 */ 196 #define VIA2B_vPower 0x04 /* 197 * Power off, 0=shut off power. 198 * on SE/30 this signal sent to PDS card. 199 */ 200 #define VIA2B_vBusLk 0x02 /* 201 * Lock NuBus transactions, 0=locked. 202 * on SE/30 sent to PDS card. 203 */ 204 #define VIA2B_vCDis 0x01 /* 205 * Cache control. On IIci, 1=disable cache card 206 * on others, 0=disable processor's instruction 207 * and data caches. 208 */ 209 210 /* interrupt flags */ 211 212 #define IRQ_SET 0x80 213 214 /* common */ 215 216 #define VIA_IRQ_TIMER1 0x40 217 #define VIA_IRQ_TIMER2 0x20 218 219 /* 220 * Apple sez: http://developer.apple.com/technotes/ov/ov_04.html 221 * Another example of a valid function that has no ROM support is the use 222 * of the alternate video page for page-flipping animation. Since there 223 * is no ROM call to flip pages, it is necessary to go play with the 224 * right bit in the VIA chip (6522 Versatile Interface Adapter). 225 * [CSA: don't know which one this is, but it's one of 'em!] 226 */ 227 228 /* 229 * 6522 registers - see databook. 230 * CSA: Assignments for VIA1 confirmed from CHRP spec. 231 */ 232 233 /* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */ 234 /* Note: 15 VIA regs, 8 RBV regs */ 235 236 #define vBufB 0x0000 /* [VIA/RBV] Register B */ 237 #define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */ 238 #define vDirB 0x0400 /* [VIA only] Data Direction Register B. */ 239 #define vDirA 0x0600 /* [VIA only] Data Direction Register A. */ 240 #define vT1CL 0x0800 /* [VIA only] Timer one counter low. */ 241 #define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */ 242 #define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */ 243 #define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */ 244 #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ 245 #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ 246 #define vSR 0x1400 /* [VIA only] Shift register. */ 247 #define vACR 0x1600 /* [VIA only] Auxilary control register. */ 248 #define vPCR 0x1800 /* [VIA only] Peripheral control register. */ 249 /* 250 * CHRP sez never ever to *write* this. 251 * Mac family says never to *change* this. 252 * In fact we need to initialize it once at start. 253 */ 254 #define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */ 255 #define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */ 256 #define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */ 257 258 /* from linux 2.6 drivers/macintosh/via-macii.c */ 259 260 /* Bits in ACR */ 261 262 #define VIA1ACR_vShiftCtrl 0x1c /* Shift register control bits */ 263 #define VIA1ACR_vShiftExtClk 0x0c /* Shift on external clock */ 264 #define VIA1ACR_vShiftOut 0x10 /* Shift out if 1 */ 265 266 /* 267 * Apple Macintosh Family Hardware Refenece 268 * Table 19-10 ADB transaction states 269 */ 270 271 #define ADB_STATE_NEW 0 272 #define ADB_STATE_EVEN 1 273 #define ADB_STATE_ODD 2 274 #define ADB_STATE_IDLE 3 275 276 #define VIA1B_vADB_StateMask (VIA1B_vADBS1 | VIA1B_vADBS2) 277 #define VIA1B_vADB_StateShift 4 278 279 #define VIA_TIMER_FREQ (783360) 280 #define VIA_ADB_POLL_FREQ 50 /* XXX: not real */ 281 282 /* 283 * Guide to the Macintosh Family Hardware ch. 12 "Displays" p. 401 gives the 284 * precise 60Hz interrupt frequency as ~60.15Hz with a period of 16625.8 us 285 */ 286 #define VIA_60HZ_TIMER_PERIOD_NS 16625800 287 288 /* VIA returns time offset from Jan 1, 1904, not 1970 */ 289 #define RTC_OFFSET 2082844800 290 291 enum { 292 REG_0, 293 REG_1, 294 REG_2, 295 REG_3, 296 REG_TEST, 297 REG_WPROTECT, 298 REG_PRAM_ADDR, 299 REG_PRAM_ADDR_LAST = REG_PRAM_ADDR + 19, 300 REG_PRAM_SECT, 301 REG_PRAM_SECT_LAST = REG_PRAM_SECT + 7, 302 REG_INVALID, 303 REG_EMPTY = 0xff, 304 }; 305 306 static void via1_sixty_hz_update(MOS6522Q800VIA1State *v1s) 307 { 308 /* 60 Hz irq */ 309 v1s->next_sixty_hz = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 310 VIA_60HZ_TIMER_PERIOD_NS) / 311 VIA_60HZ_TIMER_PERIOD_NS * VIA_60HZ_TIMER_PERIOD_NS; 312 timer_mod(v1s->sixty_hz_timer, v1s->next_sixty_hz); 313 } 314 315 static void via1_one_second_update(MOS6522Q800VIA1State *v1s) 316 { 317 v1s->next_second = (qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000) / 318 1000 * 1000; 319 timer_mod(v1s->one_second_timer, v1s->next_second); 320 } 321 322 static void via1_sixty_hz(void *opaque) 323 { 324 MOS6522Q800VIA1State *v1s = opaque; 325 MOS6522State *s = MOS6522(v1s); 326 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 327 328 s->ifr |= VIA1_IRQ_60HZ; 329 mdc->update_irq(s); 330 331 via1_sixty_hz_update(v1s); 332 } 333 334 static void via1_one_second(void *opaque) 335 { 336 MOS6522Q800VIA1State *v1s = opaque; 337 MOS6522State *s = MOS6522(v1s); 338 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 339 340 s->ifr |= VIA1_IRQ_ONE_SECOND; 341 mdc->update_irq(s); 342 343 via1_one_second_update(v1s); 344 } 345 346 static void via1_irq_request(void *opaque, int irq, int level) 347 { 348 MOS6522Q800VIA1State *v1s = opaque; 349 MOS6522State *s = MOS6522(v1s); 350 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 351 352 if (level) { 353 s->ifr |= 1 << irq; 354 } else { 355 s->ifr &= ~(1 << irq); 356 } 357 358 mdc->update_irq(s); 359 } 360 361 static void via2_irq_request(void *opaque, int irq, int level) 362 { 363 MOS6522Q800VIA2State *v2s = opaque; 364 MOS6522State *s = MOS6522(v2s); 365 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 366 367 if (level) { 368 s->ifr |= 1 << irq; 369 } else { 370 s->ifr &= ~(1 << irq); 371 } 372 373 mdc->update_irq(s); 374 } 375 376 377 static void pram_update(MOS6522Q800VIA1State *v1s) 378 { 379 if (v1s->blk) { 380 if (blk_pwrite(v1s->blk, 0, v1s->PRAM, sizeof(v1s->PRAM), 0) < 0) { 381 qemu_log("pram_update: cannot write to file\n"); 382 } 383 } 384 } 385 386 /* 387 * RTC Commands 388 * 389 * Command byte Register addressed by the command 390 * 391 * z0000001 Seconds register 0 (lowest-order byte) 392 * z0000101 Seconds register 1 393 * z0001001 Seconds register 2 394 * z0001101 Seconds register 3 (highest-order byte) 395 * 00110001 Test register (write-only) 396 * 00110101 Write-Protect Register (write-only) 397 * z010aa01 RAM address 100aa ($10-$13) (first 20 bytes only) 398 * z1aaaa01 RAM address 0aaaa ($00-$0F) (first 20 bytes only) 399 * z0111aaa Extended memory designator and sector number 400 * 401 * For a read request, z=1, for a write z=0 402 * The letter a indicates bits whose value depend on what parameter 403 * RAM byte you want to address 404 */ 405 static int via1_rtc_compact_cmd(uint8_t value) 406 { 407 uint8_t read = value & 0x80; 408 409 value &= 0x7f; 410 411 /* the last 2 bits of a command byte must always be 0b01 ... */ 412 if ((value & 0x78) == 0x38) { 413 /* except for the extended memory designator */ 414 return read | (REG_PRAM_SECT + (value & 0x07)); 415 } 416 if ((value & 0x03) == 0x01) { 417 value >>= 2; 418 if ((value & 0x1c) == 0) { 419 /* seconds registers */ 420 return read | (REG_0 + (value & 0x03)); 421 } else if ((value == 0x0c) && !read) { 422 return REG_TEST; 423 } else if ((value == 0x0d) && !read) { 424 return REG_WPROTECT; 425 } else if ((value & 0x1c) == 0x08) { 426 /* RAM address 0x10 to 0x13 */ 427 return read | (REG_PRAM_ADDR + 0x10 + (value & 0x03)); 428 } else if ((value & 0x43) == 0x41) { 429 /* RAM address 0x00 to 0x0f */ 430 return read | (REG_PRAM_ADDR + (value & 0x0f)); 431 } 432 } 433 return REG_INVALID; 434 } 435 436 static void via1_rtc_update(MacVIAState *m) 437 { 438 MOS6522Q800VIA1State *v1s = &m->mos6522_via1; 439 MOS6522State *s = MOS6522(v1s); 440 int cmd, sector, addr; 441 uint32_t time; 442 443 if (s->b & VIA1B_vRTCEnb) { 444 return; 445 } 446 447 if (s->dirb & VIA1B_vRTCData) { 448 /* send bits to the RTC */ 449 if (!(v1s->last_b & VIA1B_vRTCClk) && (s->b & VIA1B_vRTCClk)) { 450 m->data_out <<= 1; 451 m->data_out |= s->b & VIA1B_vRTCData; 452 m->data_out_cnt++; 453 } 454 trace_via1_rtc_update_data_out(m->data_out_cnt, m->data_out); 455 } else { 456 trace_via1_rtc_update_data_in(m->data_in_cnt, m->data_in); 457 /* receive bits from the RTC */ 458 if ((v1s->last_b & VIA1B_vRTCClk) && 459 !(s->b & VIA1B_vRTCClk) && 460 m->data_in_cnt) { 461 s->b = (s->b & ~VIA1B_vRTCData) | 462 ((m->data_in >> 7) & VIA1B_vRTCData); 463 m->data_in <<= 1; 464 m->data_in_cnt--; 465 } 466 return; 467 } 468 469 if (m->data_out_cnt != 8) { 470 return; 471 } 472 473 m->data_out_cnt = 0; 474 475 trace_via1_rtc_internal_status(m->cmd, m->alt, m->data_out); 476 /* first byte: it's a command */ 477 if (m->cmd == REG_EMPTY) { 478 479 cmd = via1_rtc_compact_cmd(m->data_out); 480 trace_via1_rtc_internal_cmd(cmd); 481 482 if (cmd == REG_INVALID) { 483 trace_via1_rtc_cmd_invalid(m->data_out); 484 return; 485 } 486 487 if (cmd & 0x80) { /* this is a read command */ 488 switch (cmd & 0x7f) { 489 case REG_0...REG_3: /* seconds registers */ 490 /* 491 * register 0 is lowest-order byte 492 * register 3 is highest-order byte 493 */ 494 495 time = m->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 496 / NANOSECONDS_PER_SECOND); 497 trace_via1_rtc_internal_time(time); 498 m->data_in = (time >> ((cmd & 0x03) << 3)) & 0xff; 499 m->data_in_cnt = 8; 500 trace_via1_rtc_cmd_seconds_read((cmd & 0x7f) - REG_0, 501 m->data_in); 502 break; 503 case REG_PRAM_ADDR...REG_PRAM_ADDR_LAST: 504 /* PRAM address 0x00 -> 0x13 */ 505 m->data_in = v1s->PRAM[(cmd & 0x7f) - REG_PRAM_ADDR]; 506 m->data_in_cnt = 8; 507 trace_via1_rtc_cmd_pram_read((cmd & 0x7f) - REG_PRAM_ADDR, 508 m->data_in); 509 break; 510 case REG_PRAM_SECT...REG_PRAM_SECT_LAST: 511 /* 512 * extended memory designator and sector number 513 * the only two-byte read command 514 */ 515 trace_via1_rtc_internal_set_cmd(cmd); 516 m->cmd = cmd; 517 break; 518 default: 519 g_assert_not_reached(); 520 break; 521 } 522 return; 523 } 524 525 /* this is a write command, needs a parameter */ 526 if (cmd == REG_WPROTECT || !m->wprotect) { 527 trace_via1_rtc_internal_set_cmd(cmd); 528 m->cmd = cmd; 529 } else { 530 trace_via1_rtc_internal_ignore_cmd(cmd); 531 } 532 return; 533 } 534 535 /* second byte: it's a parameter */ 536 if (m->alt == REG_EMPTY) { 537 switch (m->cmd & 0x7f) { 538 case REG_0...REG_3: /* seconds register */ 539 /* FIXME */ 540 trace_via1_rtc_cmd_seconds_write(m->cmd - REG_0, m->data_out); 541 m->cmd = REG_EMPTY; 542 break; 543 case REG_TEST: 544 /* device control: nothing to do */ 545 trace_via1_rtc_cmd_test_write(m->data_out); 546 m->cmd = REG_EMPTY; 547 break; 548 case REG_WPROTECT: 549 /* Write Protect register */ 550 trace_via1_rtc_cmd_wprotect_write(m->data_out); 551 m->wprotect = !!(m->data_out & 0x80); 552 m->cmd = REG_EMPTY; 553 break; 554 case REG_PRAM_ADDR...REG_PRAM_ADDR_LAST: 555 /* PRAM address 0x00 -> 0x13 */ 556 trace_via1_rtc_cmd_pram_write(m->cmd - REG_PRAM_ADDR, m->data_out); 557 v1s->PRAM[m->cmd - REG_PRAM_ADDR] = m->data_out; 558 pram_update(v1s); 559 m->cmd = REG_EMPTY; 560 break; 561 case REG_PRAM_SECT...REG_PRAM_SECT_LAST: 562 addr = (m->data_out >> 2) & 0x1f; 563 sector = (m->cmd & 0x7f) - REG_PRAM_SECT; 564 if (m->cmd & 0x80) { 565 /* it's a read */ 566 m->data_in = v1s->PRAM[sector * 32 + addr]; 567 m->data_in_cnt = 8; 568 trace_via1_rtc_cmd_pram_sect_read(sector, addr, 569 sector * 32 + addr, 570 m->data_in); 571 m->cmd = REG_EMPTY; 572 } else { 573 /* it's a write, we need one more parameter */ 574 trace_via1_rtc_internal_set_alt(addr, sector, addr); 575 m->alt = addr; 576 } 577 break; 578 default: 579 g_assert_not_reached(); 580 break; 581 } 582 return; 583 } 584 585 /* third byte: it's the data of a REG_PRAM_SECT write */ 586 g_assert(REG_PRAM_SECT <= m->cmd && m->cmd <= REG_PRAM_SECT_LAST); 587 sector = m->cmd - REG_PRAM_SECT; 588 v1s->PRAM[sector * 32 + m->alt] = m->data_out; 589 pram_update(v1s); 590 trace_via1_rtc_cmd_pram_sect_write(sector, m->alt, sector * 32 + m->alt, 591 m->data_out); 592 m->alt = REG_EMPTY; 593 m->cmd = REG_EMPTY; 594 } 595 596 static void adb_via_poll(void *opaque) 597 { 598 MacVIAState *m = opaque; 599 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&m->mos6522_via1); 600 MOS6522State *s = MOS6522(v1s); 601 ADBBusState *adb_bus = &m->adb_bus; 602 uint8_t obuf[9]; 603 uint8_t *data = &s->sr; 604 int olen; 605 606 /* 607 * Setting vADBInt below indicates that an autopoll reply has been 608 * received, however we must block autopoll until the point where 609 * the entire reply has been read back to the host 610 */ 611 adb_autopoll_block(adb_bus); 612 613 if (m->adb_data_in_size > 0 && m->adb_data_in_index == 0) { 614 /* 615 * For older Linux kernels that switch to IDLE mode after sending the 616 * ADB command, detect if there is an existing response and return that 617 * as a a "fake" autopoll reply or bus timeout accordingly 618 */ 619 *data = m->adb_data_out[0]; 620 olen = m->adb_data_in_size; 621 622 s->b &= ~VIA1B_vADBInt; 623 qemu_irq_raise(m->adb_data_ready); 624 } else { 625 /* 626 * Otherwise poll as normal 627 */ 628 m->adb_data_in_index = 0; 629 m->adb_data_out_index = 0; 630 olen = adb_poll(adb_bus, obuf, adb_bus->autopoll_mask); 631 632 if (olen > 0) { 633 /* Autopoll response */ 634 *data = obuf[0]; 635 olen--; 636 memcpy(m->adb_data_in, &obuf[1], olen); 637 m->adb_data_in_size = olen; 638 639 s->b &= ~VIA1B_vADBInt; 640 qemu_irq_raise(m->adb_data_ready); 641 } else { 642 *data = m->adb_autopoll_cmd; 643 obuf[0] = 0xff; 644 obuf[1] = 0xff; 645 olen = 2; 646 647 memcpy(m->adb_data_in, obuf, olen); 648 m->adb_data_in_size = olen; 649 650 s->b &= ~VIA1B_vADBInt; 651 qemu_irq_raise(m->adb_data_ready); 652 } 653 } 654 655 trace_via1_adb_poll(*data, (s->b & VIA1B_vADBInt) ? "+" : "-", 656 adb_bus->status, m->adb_data_in_index, olen); 657 } 658 659 static int adb_via_send_len(uint8_t data) 660 { 661 /* Determine the send length from the given ADB command */ 662 uint8_t cmd = data & 0xc; 663 uint8_t reg = data & 0x3; 664 665 switch (cmd) { 666 case 0x8: 667 /* Listen command */ 668 switch (reg) { 669 case 2: 670 /* Register 2 is only used for the keyboard */ 671 return 3; 672 case 3: 673 /* 674 * Fortunately our devices only implement writes 675 * to register 3 which is fixed at 2 bytes 676 */ 677 return 3; 678 default: 679 qemu_log_mask(LOG_UNIMP, "ADB unknown length for register %d\n", 680 reg); 681 return 1; 682 } 683 default: 684 /* Talk, BusReset */ 685 return 1; 686 } 687 } 688 689 static void adb_via_send(MacVIAState *s, int state, uint8_t data) 690 { 691 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&s->mos6522_via1); 692 MOS6522State *ms = MOS6522(v1s); 693 ADBBusState *adb_bus = &s->adb_bus; 694 uint16_t autopoll_mask; 695 696 switch (state) { 697 case ADB_STATE_NEW: 698 /* 699 * Command byte: vADBInt tells host autopoll data already present 700 * in VIA shift register and ADB transceiver 701 */ 702 adb_autopoll_block(adb_bus); 703 704 if (adb_bus->status & ADB_STATUS_POLLREPLY) { 705 /* Tell the host the existing data is from autopoll */ 706 ms->b &= ~VIA1B_vADBInt; 707 } else { 708 ms->b |= VIA1B_vADBInt; 709 s->adb_data_out_index = 0; 710 s->adb_data_out[s->adb_data_out_index++] = data; 711 } 712 713 trace_via1_adb_send(" NEW", data, (ms->b & VIA1B_vADBInt) ? "+" : "-"); 714 qemu_irq_raise(s->adb_data_ready); 715 break; 716 717 case ADB_STATE_EVEN: 718 case ADB_STATE_ODD: 719 ms->b |= VIA1B_vADBInt; 720 s->adb_data_out[s->adb_data_out_index++] = data; 721 722 trace_via1_adb_send(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 723 data, (ms->b & VIA1B_vADBInt) ? "+" : "-"); 724 qemu_irq_raise(s->adb_data_ready); 725 break; 726 727 case ADB_STATE_IDLE: 728 return; 729 } 730 731 /* If the command is complete, execute it */ 732 if (s->adb_data_out_index == adb_via_send_len(s->adb_data_out[0])) { 733 s->adb_data_in_size = adb_request(adb_bus, s->adb_data_in, 734 s->adb_data_out, 735 s->adb_data_out_index); 736 s->adb_data_in_index = 0; 737 738 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 739 /* 740 * Bus timeout (but allow first EVEN and ODD byte to indicate 741 * timeout via vADBInt and SRQ status) 742 */ 743 s->adb_data_in[0] = 0xff; 744 s->adb_data_in[1] = 0xff; 745 s->adb_data_in_size = 2; 746 } 747 748 /* 749 * If last command is TALK, store it for use by autopoll and adjust 750 * the autopoll mask accordingly 751 */ 752 if ((s->adb_data_out[0] & 0xc) == 0xc) { 753 s->adb_autopoll_cmd = s->adb_data_out[0]; 754 755 autopoll_mask = 1 << (s->adb_autopoll_cmd >> 4); 756 adb_set_autopoll_mask(adb_bus, autopoll_mask); 757 } 758 } 759 } 760 761 static void adb_via_receive(MacVIAState *s, int state, uint8_t *data) 762 { 763 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&s->mos6522_via1); 764 MOS6522State *ms = MOS6522(v1s); 765 ADBBusState *adb_bus = &s->adb_bus; 766 uint16_t pending; 767 768 switch (state) { 769 case ADB_STATE_NEW: 770 ms->b |= VIA1B_vADBInt; 771 return; 772 773 case ADB_STATE_IDLE: 774 ms->b |= VIA1B_vADBInt; 775 adb_autopoll_unblock(adb_bus); 776 777 trace_via1_adb_receive("IDLE", *data, 778 (ms->b & VIA1B_vADBInt) ? "+" : "-", adb_bus->status, 779 s->adb_data_in_index, s->adb_data_in_size); 780 781 break; 782 783 case ADB_STATE_EVEN: 784 case ADB_STATE_ODD: 785 switch (s->adb_data_in_index) { 786 case 0: 787 /* First EVEN byte: vADBInt indicates bus timeout */ 788 *data = s->adb_data_in[s->adb_data_in_index]; 789 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 790 ms->b &= ~VIA1B_vADBInt; 791 } else { 792 ms->b |= VIA1B_vADBInt; 793 } 794 795 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 796 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 797 adb_bus->status, s->adb_data_in_index, 798 s->adb_data_in_size); 799 800 s->adb_data_in_index++; 801 break; 802 803 case 1: 804 /* First ODD byte: vADBInt indicates SRQ */ 805 *data = s->adb_data_in[s->adb_data_in_index]; 806 pending = adb_bus->pending & ~(1 << (s->adb_autopoll_cmd >> 4)); 807 if (pending) { 808 ms->b &= ~VIA1B_vADBInt; 809 } else { 810 ms->b |= VIA1B_vADBInt; 811 } 812 813 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 814 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 815 adb_bus->status, s->adb_data_in_index, 816 s->adb_data_in_size); 817 818 s->adb_data_in_index++; 819 break; 820 821 default: 822 /* 823 * Otherwise vADBInt indicates end of data. Note that Linux 824 * specifically checks for the sequence 0x0 0xff to confirm the 825 * end of the poll reply, so provide these extra bytes below to 826 * keep it happy 827 */ 828 if (s->adb_data_in_index < s->adb_data_in_size) { 829 /* Next data byte */ 830 *data = s->adb_data_in[s->adb_data_in_index]; 831 ms->b |= VIA1B_vADBInt; 832 } else if (s->adb_data_in_index == s->adb_data_in_size) { 833 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 834 /* Bus timeout (no more data) */ 835 *data = 0xff; 836 } else { 837 /* Return 0x0 after reply */ 838 *data = 0; 839 } 840 ms->b &= ~VIA1B_vADBInt; 841 } else { 842 /* Bus timeout (no more data) */ 843 *data = 0xff; 844 ms->b &= ~VIA1B_vADBInt; 845 adb_bus->status = 0; 846 adb_autopoll_unblock(adb_bus); 847 } 848 849 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 850 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 851 adb_bus->status, s->adb_data_in_index, 852 s->adb_data_in_size); 853 854 if (s->adb_data_in_index <= s->adb_data_in_size) { 855 s->adb_data_in_index++; 856 } 857 break; 858 } 859 860 qemu_irq_raise(s->adb_data_ready); 861 break; 862 } 863 } 864 865 static void via1_adb_update(MacVIAState *m) 866 { 867 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&m->mos6522_via1); 868 MOS6522State *s = MOS6522(v1s); 869 int oldstate, state; 870 871 oldstate = (v1s->last_b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; 872 state = (s->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; 873 874 if (state != oldstate) { 875 if (s->acr & VIA1ACR_vShiftOut) { 876 /* output mode */ 877 adb_via_send(m, state, s->sr); 878 } else { 879 /* input mode */ 880 adb_via_receive(m, state, &s->sr); 881 } 882 } 883 } 884 885 static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size) 886 { 887 MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque); 888 MOS6522State *ms = MOS6522(s); 889 890 addr = (addr >> 9) & 0xf; 891 return mos6522_read(ms, addr, size); 892 } 893 894 static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val, 895 unsigned size) 896 { 897 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 898 MacVIAState *m = container_of(v1s, MacVIAState, mos6522_via1); 899 MOS6522State *ms = MOS6522(v1s); 900 901 addr = (addr >> 9) & 0xf; 902 mos6522_write(ms, addr, val, size); 903 904 switch (addr) { 905 case VIA_REG_B: 906 via1_rtc_update(m); 907 via1_adb_update(m); 908 909 v1s->last_b = ms->b; 910 break; 911 } 912 } 913 914 static const MemoryRegionOps mos6522_q800_via1_ops = { 915 .read = mos6522_q800_via1_read, 916 .write = mos6522_q800_via1_write, 917 .endianness = DEVICE_BIG_ENDIAN, 918 .valid = { 919 .min_access_size = 1, 920 .max_access_size = 4, 921 }, 922 }; 923 924 static uint64_t mos6522_q800_via2_read(void *opaque, hwaddr addr, unsigned size) 925 { 926 MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque); 927 MOS6522State *ms = MOS6522(s); 928 929 addr = (addr >> 9) & 0xf; 930 return mos6522_read(ms, addr, size); 931 } 932 933 static void mos6522_q800_via2_write(void *opaque, hwaddr addr, uint64_t val, 934 unsigned size) 935 { 936 MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque); 937 MOS6522State *ms = MOS6522(s); 938 939 addr = (addr >> 9) & 0xf; 940 mos6522_write(ms, addr, val, size); 941 } 942 943 static const MemoryRegionOps mos6522_q800_via2_ops = { 944 .read = mos6522_q800_via2_read, 945 .write = mos6522_q800_via2_write, 946 .endianness = DEVICE_BIG_ENDIAN, 947 .valid = { 948 .min_access_size = 1, 949 .max_access_size = 4, 950 }, 951 }; 952 953 static void mac_via_reset(DeviceState *dev) 954 { 955 MacVIAState *m = MAC_VIA(dev); 956 ADBBusState *adb_bus = &m->adb_bus; 957 958 adb_set_autopoll_enabled(adb_bus, true); 959 960 m->cmd = REG_EMPTY; 961 m->alt = REG_EMPTY; 962 } 963 964 static void mac_via_realize(DeviceState *dev, Error **errp) 965 { 966 MacVIAState *m = MAC_VIA(dev); 967 MOS6522Q800VIA1State *v1s = &m->mos6522_via1; 968 MOS6522State *ms; 969 ADBBusState *adb_bus = &m->adb_bus; 970 struct tm tm; 971 int ret; 972 973 /* Init VIAs 1 and 2 */ 974 object_initialize_child(OBJECT(dev), "via1", &m->mos6522_via1, 975 TYPE_MOS6522_Q800_VIA1); 976 977 object_initialize_child(OBJECT(dev), "via2", &m->mos6522_via2, 978 TYPE_MOS6522_Q800_VIA2); 979 980 /* Pass through mos6522 output IRQs */ 981 ms = MOS6522(&m->mos6522_via1); 982 object_property_add_alias(OBJECT(dev), "irq[0]", OBJECT(ms), 983 SYSBUS_DEVICE_GPIO_IRQ "[0]"); 984 ms = MOS6522(&m->mos6522_via2); 985 object_property_add_alias(OBJECT(dev), "irq[1]", OBJECT(ms), 986 SYSBUS_DEVICE_GPIO_IRQ "[0]"); 987 988 sysbus_realize(SYS_BUS_DEVICE(&m->mos6522_via1), &error_abort); 989 sysbus_realize(SYS_BUS_DEVICE(&m->mos6522_via2), &error_abort); 990 991 /* Pass through mos6522 input IRQs */ 992 qdev_pass_gpios(DEVICE(&m->mos6522_via1), dev, "via1-irq"); 993 qdev_pass_gpios(DEVICE(&m->mos6522_via2), dev, "via2-irq"); 994 995 /* VIA 1 */ 996 m->mos6522_via1.one_second_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 997 via1_one_second, 998 &m->mos6522_via1); 999 via1_one_second_update(&m->mos6522_via1); 1000 m->mos6522_via1.sixty_hz_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1001 via1_sixty_hz, 1002 &m->mos6522_via1); 1003 via1_sixty_hz_update(&m->mos6522_via1); 1004 1005 qemu_get_timedate(&tm, 0); 1006 m->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; 1007 1008 adb_register_autopoll_callback(adb_bus, adb_via_poll, m); 1009 m->adb_data_ready = qdev_get_gpio_in_named(dev, "via1-irq", 1010 VIA1_IRQ_ADB_READY_BIT); 1011 1012 if (v1s->blk) { 1013 int64_t len = blk_getlength(v1s->blk); 1014 if (len < 0) { 1015 error_setg_errno(errp, -len, 1016 "could not get length of backing image"); 1017 return; 1018 } 1019 ret = blk_set_perm(v1s->blk, 1020 BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, 1021 BLK_PERM_ALL, errp); 1022 if (ret < 0) { 1023 return; 1024 } 1025 1026 len = blk_pread(v1s->blk, 0, v1s->PRAM, sizeof(v1s->PRAM)); 1027 if (len != sizeof(v1s->PRAM)) { 1028 error_setg(errp, "can't read PRAM contents"); 1029 return; 1030 } 1031 } 1032 } 1033 1034 static void mac_via_init(Object *obj) 1035 { 1036 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1037 MacVIAState *m = MAC_VIA(obj); 1038 1039 /* MMIO */ 1040 memory_region_init(&m->mmio, obj, "mac-via", 2 * VIA_SIZE); 1041 sysbus_init_mmio(sbd, &m->mmio); 1042 1043 memory_region_init_io(&m->via1mem, obj, &mos6522_q800_via1_ops, 1044 &m->mos6522_via1, "via1", VIA_SIZE); 1045 memory_region_add_subregion(&m->mmio, 0x0, &m->via1mem); 1046 1047 memory_region_init_io(&m->via2mem, obj, &mos6522_q800_via2_ops, 1048 &m->mos6522_via2, "via2", VIA_SIZE); 1049 memory_region_add_subregion(&m->mmio, VIA_SIZE, &m->via2mem); 1050 1051 /* ADB */ 1052 qbus_create_inplace((BusState *)&m->adb_bus, sizeof(m->adb_bus), 1053 TYPE_ADB_BUS, DEVICE(obj), "adb.0"); 1054 } 1055 1056 static void via1_postload_update_cb(void *opaque, bool running, RunState state) 1057 { 1058 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 1059 1060 qemu_del_vm_change_state_handler(v1s->vmstate); 1061 v1s->vmstate = NULL; 1062 1063 pram_update(v1s); 1064 } 1065 1066 static int via1_post_load(void *opaque, int version_id) 1067 { 1068 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 1069 1070 if (v1s->blk) { 1071 v1s->vmstate = qemu_add_vm_change_state_handler( 1072 via1_postload_update_cb, v1s); 1073 } 1074 1075 return 0; 1076 } 1077 1078 static const VMStateDescription vmstate_mac_via = { 1079 .name = "mac-via", 1080 .version_id = 2, 1081 .minimum_version_id = 2, 1082 .fields = (VMStateField[]) { 1083 /* VIAs */ 1084 VMSTATE_BUFFER(mos6522_via1.PRAM, MacVIAState), 1085 VMSTATE_TIMER_PTR(mos6522_via1.one_second_timer, MacVIAState), 1086 VMSTATE_INT64(mos6522_via1.next_second, MacVIAState), 1087 VMSTATE_TIMER_PTR(mos6522_via1.sixty_hz_timer, MacVIAState), 1088 VMSTATE_INT64(mos6522_via1.next_sixty_hz, MacVIAState), 1089 /* RTC */ 1090 VMSTATE_UINT32(tick_offset, MacVIAState), 1091 VMSTATE_UINT8(data_out, MacVIAState), 1092 VMSTATE_INT32(data_out_cnt, MacVIAState), 1093 VMSTATE_UINT8(data_in, MacVIAState), 1094 VMSTATE_UINT8(data_in_cnt, MacVIAState), 1095 VMSTATE_UINT8(cmd, MacVIAState), 1096 VMSTATE_INT32(wprotect, MacVIAState), 1097 VMSTATE_INT32(alt, MacVIAState), 1098 /* ADB */ 1099 VMSTATE_INT32(adb_data_in_size, MacVIAState), 1100 VMSTATE_INT32(adb_data_in_index, MacVIAState), 1101 VMSTATE_INT32(adb_data_out_index, MacVIAState), 1102 VMSTATE_BUFFER(adb_data_in, MacVIAState), 1103 VMSTATE_BUFFER(adb_data_out, MacVIAState), 1104 VMSTATE_UINT8(adb_autopoll_cmd, MacVIAState), 1105 VMSTATE_END_OF_LIST() 1106 } 1107 }; 1108 1109 static void mac_via_class_init(ObjectClass *oc, void *data) 1110 { 1111 DeviceClass *dc = DEVICE_CLASS(oc); 1112 1113 dc->realize = mac_via_realize; 1114 dc->reset = mac_via_reset; 1115 dc->vmsd = &vmstate_mac_via; 1116 } 1117 1118 static TypeInfo mac_via_info = { 1119 .name = TYPE_MAC_VIA, 1120 .parent = TYPE_SYS_BUS_DEVICE, 1121 .instance_size = sizeof(MacVIAState), 1122 .instance_init = mac_via_init, 1123 .class_init = mac_via_class_init, 1124 }; 1125 1126 /* VIA 1 */ 1127 static void mos6522_q800_via1_reset(DeviceState *dev) 1128 { 1129 MOS6522State *ms = MOS6522(dev); 1130 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 1131 1132 mdc->parent_reset(dev); 1133 1134 ms->timers[0].frequency = VIA_TIMER_FREQ; 1135 ms->timers[1].frequency = VIA_TIMER_FREQ; 1136 1137 ms->b = VIA1B_vADB_StateMask | VIA1B_vADBInt | VIA1B_vRTCEnb; 1138 } 1139 1140 static void mos6522_q800_via1_init(Object *obj) 1141 { 1142 qdev_init_gpio_in_named(DEVICE(obj), via1_irq_request, "via1-irq", 1143 VIA1_IRQ_NB); 1144 } 1145 1146 static const VMStateDescription vmstate_q800_via1 = { 1147 .name = "q800-via1", 1148 .version_id = 0, 1149 .minimum_version_id = 0, 1150 .post_load = via1_post_load, 1151 .fields = (VMStateField[]) { 1152 VMSTATE_STRUCT(parent_obj, MOS6522Q800VIA1State, 0, vmstate_mos6522, 1153 MOS6522State), 1154 VMSTATE_UINT8(last_b, MOS6522Q800VIA1State), 1155 /* RTC */ 1156 VMSTATE_BUFFER(PRAM, MOS6522Q800VIA1State), 1157 VMSTATE_END_OF_LIST() 1158 } 1159 }; 1160 1161 static Property mos6522_q800_via1_properties[] = { 1162 DEFINE_PROP_DRIVE("drive", MOS6522Q800VIA1State, blk), 1163 DEFINE_PROP_END_OF_LIST(), 1164 }; 1165 1166 static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data) 1167 { 1168 DeviceClass *dc = DEVICE_CLASS(oc); 1169 1170 dc->reset = mos6522_q800_via1_reset; 1171 dc->vmsd = &vmstate_q800_via1; 1172 device_class_set_props(dc, mos6522_q800_via1_properties); 1173 } 1174 1175 static const TypeInfo mos6522_q800_via1_type_info = { 1176 .name = TYPE_MOS6522_Q800_VIA1, 1177 .parent = TYPE_MOS6522, 1178 .instance_size = sizeof(MOS6522Q800VIA1State), 1179 .instance_init = mos6522_q800_via1_init, 1180 .class_init = mos6522_q800_via1_class_init, 1181 }; 1182 1183 /* VIA 2 */ 1184 static void mos6522_q800_via2_portB_write(MOS6522State *s) 1185 { 1186 if (s->dirb & VIA2B_vPower && (s->b & VIA2B_vPower) == 0) { 1187 /* shutdown */ 1188 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 1189 } 1190 } 1191 1192 static void mos6522_q800_via2_reset(DeviceState *dev) 1193 { 1194 MOS6522State *ms = MOS6522(dev); 1195 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 1196 1197 mdc->parent_reset(dev); 1198 1199 ms->timers[0].frequency = VIA_TIMER_FREQ; 1200 ms->timers[1].frequency = VIA_TIMER_FREQ; 1201 1202 ms->dirb = 0; 1203 ms->b = 0; 1204 } 1205 1206 static void mos6522_q800_via2_init(Object *obj) 1207 { 1208 qdev_init_gpio_in_named(DEVICE(obj), via2_irq_request, "via2-irq", 1209 VIA2_IRQ_NB); 1210 } 1211 1212 static const VMStateDescription vmstate_q800_via2 = { 1213 .name = "q800-via2", 1214 .version_id = 0, 1215 .minimum_version_id = 0, 1216 .fields = (VMStateField[]) { 1217 VMSTATE_STRUCT(parent_obj, MOS6522Q800VIA2State, 0, vmstate_mos6522, 1218 MOS6522State), 1219 VMSTATE_END_OF_LIST() 1220 } 1221 }; 1222 1223 static void mos6522_q800_via2_class_init(ObjectClass *oc, void *data) 1224 { 1225 DeviceClass *dc = DEVICE_CLASS(oc); 1226 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); 1227 1228 dc->reset = mos6522_q800_via2_reset; 1229 dc->vmsd = &vmstate_q800_via2; 1230 mdc->portB_write = mos6522_q800_via2_portB_write; 1231 } 1232 1233 static const TypeInfo mos6522_q800_via2_type_info = { 1234 .name = TYPE_MOS6522_Q800_VIA2, 1235 .parent = TYPE_MOS6522, 1236 .instance_size = sizeof(MOS6522Q800VIA2State), 1237 .instance_init = mos6522_q800_via2_init, 1238 .class_init = mos6522_q800_via2_class_init, 1239 }; 1240 1241 static void mac_via_register_types(void) 1242 { 1243 type_register_static(&mos6522_q800_via1_type_info); 1244 type_register_static(&mos6522_q800_via2_type_info); 1245 type_register_static(&mac_via_info); 1246 } 1247 1248 type_init(mac_via_register_types); 1249