1 /* 2 * QEMU m68k Macintosh VIA device support 3 * 4 * Copyright (c) 2011-2018 Laurent Vivier 5 * Copyright (c) 2018 Mark Cave-Ayland 6 * 7 * Some parts from hw/misc/macio/cuda.c 8 * 9 * Copyright (c) 2004-2007 Fabrice Bellard 10 * Copyright (c) 2007 Jocelyn Mayer 11 * 12 * some parts from linux-2.6.29, arch/m68k/include/asm/mac_via.h 13 * 14 * This work is licensed under the terms of the GNU GPL, version 2 or later. 15 * See the COPYING file in the top-level directory. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu-common.h" 20 #include "migration/vmstate.h" 21 #include "hw/sysbus.h" 22 #include "hw/irq.h" 23 #include "qemu/timer.h" 24 #include "hw/misc/mac_via.h" 25 #include "hw/misc/mos6522.h" 26 #include "hw/input/adb.h" 27 #include "sysemu/runstate.h" 28 #include "qapi/error.h" 29 #include "qemu/cutils.h" 30 #include "hw/qdev-properties.h" 31 #include "hw/qdev-properties-system.h" 32 #include "sysemu/block-backend.h" 33 #include "trace.h" 34 #include "qemu/log.h" 35 36 /* 37 * VIAs: There are two in every machine, 38 */ 39 40 #define VIA_SIZE (0x2000) 41 42 /* 43 * Not all of these are true post MacII I think. 44 * CSA: probably the ones CHRP marks as 'unused' change purposes 45 * when the IWM becomes the SWIM. 46 * http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html 47 * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf 48 * 49 * also, http://developer.apple.com/technotes/hw/hw_09.html claims the 50 * following changes for IIfx: 51 * VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP. 52 * Also, "All of the functionality of VIA2 has been moved to other chips". 53 */ 54 55 #define VIA1A_vSccWrReq 0x80 /* 56 * SCC write. (input) 57 * [CHRP] SCC WREQ: Reflects the state of the 58 * Wait/Request pins from the SCC. 59 * [Macintosh Family Hardware] 60 * as CHRP on SE/30,II,IIx,IIcx,IIci. 61 * on IIfx, "0 means an active request" 62 */ 63 #define VIA1A_vRev8 0x40 /* 64 * Revision 8 board ??? 65 * [CHRP] En WaitReqB: Lets the WaitReq_L 66 * signal from port B of the SCC appear on 67 * the PA7 input pin. Output. 68 * [Macintosh Family] On the SE/30, this 69 * is the bit to flip screen buffers. 70 * 0=alternate, 1=main. 71 * on II,IIx,IIcx,IIci,IIfx this is a bit 72 * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx 73 */ 74 #define VIA1A_vHeadSel 0x20 /* 75 * Head select for IWM. 76 * [CHRP] unused. 77 * [Macintosh Family] "Floppy disk 78 * state-control line SEL" on all but IIfx 79 */ 80 #define VIA1A_vOverlay 0x10 /* 81 * [Macintosh Family] On SE/30,II,IIx,IIcx 82 * this bit enables the "Overlay" address 83 * map in the address decoders as it is on 84 * reset for mapping the ROM over the reset 85 * vector. 1=use overlay map. 86 * On the IIci,IIfx it is another bit of the 87 * CPU ID: 0=normal IIci, 1=IIci with parity 88 * feature or IIfx. 89 * [CHRP] En WaitReqA: Lets the WaitReq_L 90 * signal from port A of the SCC appear 91 * on the PA7 input pin (CHRP). Output. 92 * [MkLinux] "Drive Select" 93 * (with 0x20 being 'disk head select') 94 */ 95 #define VIA1A_vSync 0x08 /* 96 * [CHRP] Sync Modem: modem clock select: 97 * 1: select the external serial clock to 98 * drive the SCC's /RTxCA pin. 99 * 0: Select the 3.6864MHz clock to drive 100 * the SCC cell. 101 * [Macintosh Family] Correct on all but IIfx 102 */ 103 104 /* 105 * Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control 106 * on Macs which had the PWM sound hardware. Reserved on newer models. 107 * On IIci,IIfx, bits 1-2 are the rest of the CPU ID: 108 * bit 2: 1=IIci, 0=IIfx 109 * bit 1: 1 on both IIci and IIfx. 110 * MkLinux sez bit 0 is 'burnin flag' in this case. 111 * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as 112 * inputs, these bits will read 0. 113 */ 114 #define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */ 115 #define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */ 116 #define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */ 117 #define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */ 118 #define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */ 119 120 /* 121 * Info on VIA1B is from Macintosh Family Hardware & MkLinux. 122 * CHRP offers no info. 123 */ 124 #define VIA1B_vSound 0x80 /* 125 * Sound enable (for compatibility with 126 * PWM hardware) 0=enabled. 127 * Also, on IIci w/parity, shows parity error 128 * 0=error, 1=OK. 129 */ 130 #define VIA1B_vMystery 0x40 /* 131 * On IIci, parity enable. 0=enabled,1=disabled 132 * On SE/30, vertical sync interrupt enable. 133 * 0=enabled. This vSync interrupt shows up 134 * as a slot $E interrupt. 135 */ 136 #define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */ 137 #define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */ 138 #define VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/ 139 #define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */ 140 #define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */ 141 #define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */ 142 143 /* 144 * VIA2 A register is the interrupt lines raised off the nubus 145 * slots. 146 * The below info is from 'Macintosh Family Hardware.' 147 * MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.' 148 * It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and 149 * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike. 150 * Perhaps OSS uses vRAM1 and vRAM2 for ADB. 151 */ 152 153 #define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */ 154 #define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */ 155 #define VIA2A_vIRQE 0x20 /* IRQ from slot $E */ 156 #define VIA2A_vIRQD 0x10 /* IRQ from slot $D */ 157 #define VIA2A_vIRQC 0x08 /* IRQ from slot $C */ 158 #define VIA2A_vIRQB 0x04 /* IRQ from slot $B */ 159 #define VIA2A_vIRQA 0x02 /* IRQ from slot $A */ 160 #define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */ 161 162 /* 163 * RAM size bits decoded as follows: 164 * bit1 bit0 size of ICs in bank A 165 * 0 0 256 kbit 166 * 0 1 1 Mbit 167 * 1 0 4 Mbit 168 * 1 1 16 Mbit 169 */ 170 171 /* 172 * Register B has the fun stuff in it 173 */ 174 175 #define VIA2B_vVBL 0x80 /* 176 * VBL output to VIA1 (60.15Hz) driven by 177 * timer T1. 178 * on IIci, parity test: 0=test mode. 179 * [MkLinux] RBV_PARODD: 1=odd,0=even. 180 */ 181 #define VIA2B_vSndJck 0x40 /* 182 * External sound jack status. 183 * 0=plug is inserted. On SE/30, always 0 184 */ 185 #define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */ 186 #define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */ 187 #define VIA2B_vMode32 0x08 /* 188 * 24/32bit switch - doubles as cache flush 189 * on II, AMU/PMMU control. 190 * if AMU, 0=24bit to 32bit translation 191 * if PMMU, 1=PMMU is accessing page table. 192 * on SE/30 tied low. 193 * on IIx,IIcx,IIfx, unused. 194 * on IIci/RBV, cache control. 0=flush cache. 195 */ 196 #define VIA2B_vPower 0x04 /* 197 * Power off, 0=shut off power. 198 * on SE/30 this signal sent to PDS card. 199 */ 200 #define VIA2B_vBusLk 0x02 /* 201 * Lock NuBus transactions, 0=locked. 202 * on SE/30 sent to PDS card. 203 */ 204 #define VIA2B_vCDis 0x01 /* 205 * Cache control. On IIci, 1=disable cache card 206 * on others, 0=disable processor's instruction 207 * and data caches. 208 */ 209 210 /* interrupt flags */ 211 212 #define IRQ_SET 0x80 213 214 /* common */ 215 216 #define VIA_IRQ_TIMER1 0x40 217 #define VIA_IRQ_TIMER2 0x20 218 219 /* 220 * Apple sez: http://developer.apple.com/technotes/ov/ov_04.html 221 * Another example of a valid function that has no ROM support is the use 222 * of the alternate video page for page-flipping animation. Since there 223 * is no ROM call to flip pages, it is necessary to go play with the 224 * right bit in the VIA chip (6522 Versatile Interface Adapter). 225 * [CSA: don't know which one this is, but it's one of 'em!] 226 */ 227 228 /* 229 * 6522 registers - see databook. 230 * CSA: Assignments for VIA1 confirmed from CHRP spec. 231 */ 232 233 /* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */ 234 /* Note: 15 VIA regs, 8 RBV regs */ 235 236 #define vBufB 0x0000 /* [VIA/RBV] Register B */ 237 #define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */ 238 #define vDirB 0x0400 /* [VIA only] Data Direction Register B. */ 239 #define vDirA 0x0600 /* [VIA only] Data Direction Register A. */ 240 #define vT1CL 0x0800 /* [VIA only] Timer one counter low. */ 241 #define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */ 242 #define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */ 243 #define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */ 244 #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ 245 #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ 246 #define vSR 0x1400 /* [VIA only] Shift register. */ 247 #define vACR 0x1600 /* [VIA only] Auxilary control register. */ 248 #define vPCR 0x1800 /* [VIA only] Peripheral control register. */ 249 /* 250 * CHRP sez never ever to *write* this. 251 * Mac family says never to *change* this. 252 * In fact we need to initialize it once at start. 253 */ 254 #define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */ 255 #define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */ 256 #define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */ 257 258 /* from linux 2.6 drivers/macintosh/via-macii.c */ 259 260 /* Bits in ACR */ 261 262 #define VIA1ACR_vShiftCtrl 0x1c /* Shift register control bits */ 263 #define VIA1ACR_vShiftExtClk 0x0c /* Shift on external clock */ 264 #define VIA1ACR_vShiftOut 0x10 /* Shift out if 1 */ 265 266 /* 267 * Apple Macintosh Family Hardware Refenece 268 * Table 19-10 ADB transaction states 269 */ 270 271 #define ADB_STATE_NEW 0 272 #define ADB_STATE_EVEN 1 273 #define ADB_STATE_ODD 2 274 #define ADB_STATE_IDLE 3 275 276 #define VIA1B_vADB_StateMask (VIA1B_vADBS1 | VIA1B_vADBS2) 277 #define VIA1B_vADB_StateShift 4 278 279 #define VIA_TIMER_FREQ (783360) 280 #define VIA_ADB_POLL_FREQ 50 /* XXX: not real */ 281 282 /* VIA returns time offset from Jan 1, 1904, not 1970 */ 283 #define RTC_OFFSET 2082844800 284 285 enum { 286 REG_0, 287 REG_1, 288 REG_2, 289 REG_3, 290 REG_TEST, 291 REG_WPROTECT, 292 REG_PRAM_ADDR, 293 REG_PRAM_ADDR_LAST = REG_PRAM_ADDR + 19, 294 REG_PRAM_SECT, 295 REG_PRAM_SECT_LAST = REG_PRAM_SECT + 7, 296 REG_INVALID, 297 REG_EMPTY = 0xff, 298 }; 299 300 static void via1_sixty_hz_update(MOS6522Q800VIA1State *v1s) 301 { 302 MOS6522State *s = MOS6522(v1s); 303 304 /* 60 Hz irq */ 305 v1s->next_sixty_hz = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 16630) / 306 16630 * 16630; 307 308 if (s->ier & VIA1_IRQ_60HZ) { 309 timer_mod(v1s->sixty_hz_timer, v1s->next_sixty_hz); 310 } else { 311 timer_del(v1s->sixty_hz_timer); 312 } 313 } 314 315 static void via1_one_second_update(MOS6522Q800VIA1State *v1s) 316 { 317 MOS6522State *s = MOS6522(v1s); 318 319 v1s->next_second = (qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000) / 320 1000 * 1000; 321 if (s->ier & VIA1_IRQ_ONE_SECOND) { 322 timer_mod(v1s->one_second_timer, v1s->next_second); 323 } else { 324 timer_del(v1s->one_second_timer); 325 } 326 } 327 328 static void via1_sixty_hz(void *opaque) 329 { 330 MOS6522Q800VIA1State *v1s = opaque; 331 MOS6522State *s = MOS6522(v1s); 332 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 333 334 s->ifr |= VIA1_IRQ_60HZ; 335 mdc->update_irq(s); 336 337 via1_sixty_hz_update(v1s); 338 } 339 340 static void via1_one_second(void *opaque) 341 { 342 MOS6522Q800VIA1State *v1s = opaque; 343 MOS6522State *s = MOS6522(v1s); 344 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 345 346 s->ifr |= VIA1_IRQ_ONE_SECOND; 347 mdc->update_irq(s); 348 349 via1_one_second_update(v1s); 350 } 351 352 static void via1_irq_request(void *opaque, int irq, int level) 353 { 354 MOS6522Q800VIA1State *v1s = opaque; 355 MOS6522State *s = MOS6522(v1s); 356 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 357 358 if (level) { 359 s->ifr |= 1 << irq; 360 } else { 361 s->ifr &= ~(1 << irq); 362 } 363 364 mdc->update_irq(s); 365 } 366 367 static void via2_irq_request(void *opaque, int irq, int level) 368 { 369 MOS6522Q800VIA2State *v2s = opaque; 370 MOS6522State *s = MOS6522(v2s); 371 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); 372 373 if (level) { 374 s->ifr |= 1 << irq; 375 } else { 376 s->ifr &= ~(1 << irq); 377 } 378 379 mdc->update_irq(s); 380 } 381 382 383 static void pram_update(MacVIAState *m) 384 { 385 if (m->blk) { 386 if (blk_pwrite(m->blk, 0, m->mos6522_via1.PRAM, 387 sizeof(m->mos6522_via1.PRAM), 0) < 0) { 388 qemu_log("pram_update: cannot write to file\n"); 389 } 390 } 391 } 392 393 /* 394 * RTC Commands 395 * 396 * Command byte Register addressed by the command 397 * 398 * z0000001 Seconds register 0 (lowest-order byte) 399 * z0000101 Seconds register 1 400 * z0001001 Seconds register 2 401 * z0001101 Seconds register 3 (highest-order byte) 402 * 00110001 Test register (write-only) 403 * 00110101 Write-Protect Register (write-only) 404 * z010aa01 RAM address 100aa ($10-$13) (first 20 bytes only) 405 * z1aaaa01 RAM address 0aaaa ($00-$0F) (first 20 bytes only) 406 * z0111aaa Extended memory designator and sector number 407 * 408 * For a read request, z=1, for a write z=0 409 * The letter a indicates bits whose value depend on what parameter 410 * RAM byte you want to address 411 */ 412 static int via1_rtc_compact_cmd(uint8_t value) 413 { 414 uint8_t read = value & 0x80; 415 416 value &= 0x7f; 417 418 /* the last 2 bits of a command byte must always be 0b01 ... */ 419 if ((value & 0x78) == 0x38) { 420 /* except for the extended memory designator */ 421 return read | (REG_PRAM_SECT + (value & 0x07)); 422 } 423 if ((value & 0x03) == 0x01) { 424 value >>= 2; 425 if ((value & 0x1c) == 0) { 426 /* seconds registers */ 427 return read | (REG_0 + (value & 0x03)); 428 } else if ((value == 0x0c) && !read) { 429 return REG_TEST; 430 } else if ((value == 0x0d) && !read) { 431 return REG_WPROTECT; 432 } else if ((value & 0x1c) == 0x08) { 433 /* RAM address 0x10 to 0x13 */ 434 return read | (REG_PRAM_ADDR + 0x10 + (value & 0x03)); 435 } else if ((value & 0x43) == 0x41) { 436 /* RAM address 0x00 to 0x0f */ 437 return read | (REG_PRAM_ADDR + (value & 0x0f)); 438 } 439 } 440 return REG_INVALID; 441 } 442 443 static void via1_rtc_update(MacVIAState *m) 444 { 445 MOS6522Q800VIA1State *v1s = &m->mos6522_via1; 446 MOS6522State *s = MOS6522(v1s); 447 int cmd, sector, addr; 448 uint32_t time; 449 450 if (s->b & VIA1B_vRTCEnb) { 451 return; 452 } 453 454 if (s->dirb & VIA1B_vRTCData) { 455 /* send bits to the RTC */ 456 if (!(v1s->last_b & VIA1B_vRTCClk) && (s->b & VIA1B_vRTCClk)) { 457 m->data_out <<= 1; 458 m->data_out |= s->b & VIA1B_vRTCData; 459 m->data_out_cnt++; 460 } 461 trace_via1_rtc_update_data_out(m->data_out_cnt, m->data_out); 462 } else { 463 trace_via1_rtc_update_data_in(m->data_in_cnt, m->data_in); 464 /* receive bits from the RTC */ 465 if ((v1s->last_b & VIA1B_vRTCClk) && 466 !(s->b & VIA1B_vRTCClk) && 467 m->data_in_cnt) { 468 s->b = (s->b & ~VIA1B_vRTCData) | 469 ((m->data_in >> 7) & VIA1B_vRTCData); 470 m->data_in <<= 1; 471 m->data_in_cnt--; 472 } 473 return; 474 } 475 476 if (m->data_out_cnt != 8) { 477 return; 478 } 479 480 m->data_out_cnt = 0; 481 482 trace_via1_rtc_internal_status(m->cmd, m->alt, m->data_out); 483 /* first byte: it's a command */ 484 if (m->cmd == REG_EMPTY) { 485 486 cmd = via1_rtc_compact_cmd(m->data_out); 487 trace_via1_rtc_internal_cmd(cmd); 488 489 if (cmd == REG_INVALID) { 490 trace_via1_rtc_cmd_invalid(m->data_out); 491 return; 492 } 493 494 if (cmd & 0x80) { /* this is a read command */ 495 switch (cmd & 0x7f) { 496 case REG_0...REG_3: /* seconds registers */ 497 /* 498 * register 0 is lowest-order byte 499 * register 3 is highest-order byte 500 */ 501 502 time = m->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 503 / NANOSECONDS_PER_SECOND); 504 trace_via1_rtc_internal_time(time); 505 m->data_in = (time >> ((cmd & 0x03) << 3)) & 0xff; 506 m->data_in_cnt = 8; 507 trace_via1_rtc_cmd_seconds_read((cmd & 0x7f) - REG_0, 508 m->data_in); 509 break; 510 case REG_PRAM_ADDR...REG_PRAM_ADDR_LAST: 511 /* PRAM address 0x00 -> 0x13 */ 512 m->data_in = v1s->PRAM[(cmd & 0x7f) - REG_PRAM_ADDR]; 513 m->data_in_cnt = 8; 514 trace_via1_rtc_cmd_pram_read((cmd & 0x7f) - REG_PRAM_ADDR, 515 m->data_in); 516 break; 517 case REG_PRAM_SECT...REG_PRAM_SECT_LAST: 518 /* 519 * extended memory designator and sector number 520 * the only two-byte read command 521 */ 522 trace_via1_rtc_internal_set_cmd(cmd); 523 m->cmd = cmd; 524 break; 525 default: 526 g_assert_not_reached(); 527 break; 528 } 529 return; 530 } 531 532 /* this is a write command, needs a parameter */ 533 if (cmd == REG_WPROTECT || !m->wprotect) { 534 trace_via1_rtc_internal_set_cmd(cmd); 535 m->cmd = cmd; 536 } else { 537 trace_via1_rtc_internal_ignore_cmd(cmd); 538 } 539 return; 540 } 541 542 /* second byte: it's a parameter */ 543 if (m->alt == REG_EMPTY) { 544 switch (m->cmd & 0x7f) { 545 case REG_0...REG_3: /* seconds register */ 546 /* FIXME */ 547 trace_via1_rtc_cmd_seconds_write(m->cmd - REG_0, m->data_out); 548 m->cmd = REG_EMPTY; 549 break; 550 case REG_TEST: 551 /* device control: nothing to do */ 552 trace_via1_rtc_cmd_test_write(m->data_out); 553 m->cmd = REG_EMPTY; 554 break; 555 case REG_WPROTECT: 556 /* Write Protect register */ 557 trace_via1_rtc_cmd_wprotect_write(m->data_out); 558 m->wprotect = !!(m->data_out & 0x80); 559 m->cmd = REG_EMPTY; 560 break; 561 case REG_PRAM_ADDR...REG_PRAM_ADDR_LAST: 562 /* PRAM address 0x00 -> 0x13 */ 563 trace_via1_rtc_cmd_pram_write(m->cmd - REG_PRAM_ADDR, m->data_out); 564 v1s->PRAM[m->cmd - REG_PRAM_ADDR] = m->data_out; 565 pram_update(m); 566 m->cmd = REG_EMPTY; 567 break; 568 case REG_PRAM_SECT...REG_PRAM_SECT_LAST: 569 addr = (m->data_out >> 2) & 0x1f; 570 sector = (m->cmd & 0x7f) - REG_PRAM_SECT; 571 if (m->cmd & 0x80) { 572 /* it's a read */ 573 m->data_in = v1s->PRAM[sector * 32 + addr]; 574 m->data_in_cnt = 8; 575 trace_via1_rtc_cmd_pram_sect_read(sector, addr, 576 sector * 32 + addr, 577 m->data_in); 578 m->cmd = REG_EMPTY; 579 } else { 580 /* it's a write, we need one more parameter */ 581 trace_via1_rtc_internal_set_alt(addr, sector, addr); 582 m->alt = addr; 583 } 584 break; 585 default: 586 g_assert_not_reached(); 587 break; 588 } 589 return; 590 } 591 592 /* third byte: it's the data of a REG_PRAM_SECT write */ 593 g_assert(REG_PRAM_SECT <= m->cmd && m->cmd <= REG_PRAM_SECT_LAST); 594 sector = m->cmd - REG_PRAM_SECT; 595 v1s->PRAM[sector * 32 + m->alt] = m->data_out; 596 pram_update(m); 597 trace_via1_rtc_cmd_pram_sect_write(sector, m->alt, sector * 32 + m->alt, 598 m->data_out); 599 m->alt = REG_EMPTY; 600 m->cmd = REG_EMPTY; 601 } 602 603 static void adb_via_poll(void *opaque) 604 { 605 MacVIAState *m = opaque; 606 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&m->mos6522_via1); 607 MOS6522State *s = MOS6522(v1s); 608 ADBBusState *adb_bus = &m->adb_bus; 609 uint8_t obuf[9]; 610 uint8_t *data = &s->sr; 611 int olen; 612 613 /* 614 * Setting vADBInt below indicates that an autopoll reply has been 615 * received, however we must block autopoll until the point where 616 * the entire reply has been read back to the host 617 */ 618 adb_autopoll_block(adb_bus); 619 620 if (m->adb_data_in_size > 0 && m->adb_data_in_index == 0) { 621 /* 622 * For older Linux kernels that switch to IDLE mode after sending the 623 * ADB command, detect if there is an existing response and return that 624 * as a a "fake" autopoll reply or bus timeout accordingly 625 */ 626 *data = m->adb_data_out[0]; 627 olen = m->adb_data_in_size; 628 629 s->b &= ~VIA1B_vADBInt; 630 qemu_irq_raise(m->adb_data_ready); 631 } else { 632 /* 633 * Otherwise poll as normal 634 */ 635 m->adb_data_in_index = 0; 636 m->adb_data_out_index = 0; 637 olen = adb_poll(adb_bus, obuf, adb_bus->autopoll_mask); 638 639 if (olen > 0) { 640 /* Autopoll response */ 641 *data = obuf[0]; 642 olen--; 643 memcpy(m->adb_data_in, &obuf[1], olen); 644 m->adb_data_in_size = olen; 645 646 s->b &= ~VIA1B_vADBInt; 647 qemu_irq_raise(m->adb_data_ready); 648 } else { 649 *data = m->adb_autopoll_cmd; 650 obuf[0] = 0xff; 651 obuf[1] = 0xff; 652 olen = 2; 653 654 memcpy(m->adb_data_in, obuf, olen); 655 m->adb_data_in_size = olen; 656 657 s->b &= ~VIA1B_vADBInt; 658 qemu_irq_raise(m->adb_data_ready); 659 } 660 } 661 662 trace_via1_adb_poll(*data, (s->b & VIA1B_vADBInt) ? "+" : "-", 663 adb_bus->status, m->adb_data_in_index, olen); 664 } 665 666 static int adb_via_send_len(uint8_t data) 667 { 668 /* Determine the send length from the given ADB command */ 669 uint8_t cmd = data & 0xc; 670 uint8_t reg = data & 0x3; 671 672 switch (cmd) { 673 case 0x8: 674 /* Listen command */ 675 switch (reg) { 676 case 2: 677 /* Register 2 is only used for the keyboard */ 678 return 3; 679 case 3: 680 /* 681 * Fortunately our devices only implement writes 682 * to register 3 which is fixed at 2 bytes 683 */ 684 return 3; 685 default: 686 qemu_log_mask(LOG_UNIMP, "ADB unknown length for register %d\n", 687 reg); 688 return 1; 689 } 690 default: 691 /* Talk, BusReset */ 692 return 1; 693 } 694 } 695 696 static void adb_via_send(MacVIAState *s, int state, uint8_t data) 697 { 698 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&s->mos6522_via1); 699 MOS6522State *ms = MOS6522(v1s); 700 ADBBusState *adb_bus = &s->adb_bus; 701 uint16_t autopoll_mask; 702 703 switch (state) { 704 case ADB_STATE_NEW: 705 /* 706 * Command byte: vADBInt tells host autopoll data already present 707 * in VIA shift register and ADB transceiver 708 */ 709 adb_autopoll_block(adb_bus); 710 711 if (adb_bus->status & ADB_STATUS_POLLREPLY) { 712 /* Tell the host the existing data is from autopoll */ 713 ms->b &= ~VIA1B_vADBInt; 714 } else { 715 ms->b |= VIA1B_vADBInt; 716 s->adb_data_out_index = 0; 717 s->adb_data_out[s->adb_data_out_index++] = data; 718 } 719 720 trace_via1_adb_send(" NEW", data, (ms->b & VIA1B_vADBInt) ? "+" : "-"); 721 qemu_irq_raise(s->adb_data_ready); 722 break; 723 724 case ADB_STATE_EVEN: 725 case ADB_STATE_ODD: 726 ms->b |= VIA1B_vADBInt; 727 s->adb_data_out[s->adb_data_out_index++] = data; 728 729 trace_via1_adb_send(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 730 data, (ms->b & VIA1B_vADBInt) ? "+" : "-"); 731 qemu_irq_raise(s->adb_data_ready); 732 break; 733 734 case ADB_STATE_IDLE: 735 return; 736 } 737 738 /* If the command is complete, execute it */ 739 if (s->adb_data_out_index == adb_via_send_len(s->adb_data_out[0])) { 740 s->adb_data_in_size = adb_request(adb_bus, s->adb_data_in, 741 s->adb_data_out, 742 s->adb_data_out_index); 743 s->adb_data_in_index = 0; 744 745 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 746 /* 747 * Bus timeout (but allow first EVEN and ODD byte to indicate 748 * timeout via vADBInt and SRQ status) 749 */ 750 s->adb_data_in[0] = 0xff; 751 s->adb_data_in[1] = 0xff; 752 s->adb_data_in_size = 2; 753 } 754 755 /* 756 * If last command is TALK, store it for use by autopoll and adjust 757 * the autopoll mask accordingly 758 */ 759 if ((s->adb_data_out[0] & 0xc) == 0xc) { 760 s->adb_autopoll_cmd = s->adb_data_out[0]; 761 762 autopoll_mask = 1 << (s->adb_autopoll_cmd >> 4); 763 adb_set_autopoll_mask(adb_bus, autopoll_mask); 764 } 765 } 766 } 767 768 static void adb_via_receive(MacVIAState *s, int state, uint8_t *data) 769 { 770 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&s->mos6522_via1); 771 MOS6522State *ms = MOS6522(v1s); 772 ADBBusState *adb_bus = &s->adb_bus; 773 uint16_t pending; 774 775 switch (state) { 776 case ADB_STATE_NEW: 777 ms->b |= VIA1B_vADBInt; 778 return; 779 780 case ADB_STATE_IDLE: 781 ms->b |= VIA1B_vADBInt; 782 adb_autopoll_unblock(adb_bus); 783 784 trace_via1_adb_receive("IDLE", *data, 785 (ms->b & VIA1B_vADBInt) ? "+" : "-", adb_bus->status, 786 s->adb_data_in_index, s->adb_data_in_size); 787 788 break; 789 790 case ADB_STATE_EVEN: 791 case ADB_STATE_ODD: 792 switch (s->adb_data_in_index) { 793 case 0: 794 /* First EVEN byte: vADBInt indicates bus timeout */ 795 *data = s->adb_data_in[s->adb_data_in_index]; 796 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 797 ms->b &= ~VIA1B_vADBInt; 798 } else { 799 ms->b |= VIA1B_vADBInt; 800 } 801 802 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 803 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 804 adb_bus->status, s->adb_data_in_index, 805 s->adb_data_in_size); 806 807 s->adb_data_in_index++; 808 break; 809 810 case 1: 811 /* First ODD byte: vADBInt indicates SRQ */ 812 *data = s->adb_data_in[s->adb_data_in_index]; 813 pending = adb_bus->pending & ~(1 << (s->adb_autopoll_cmd >> 4)); 814 if (pending) { 815 ms->b &= ~VIA1B_vADBInt; 816 } else { 817 ms->b |= VIA1B_vADBInt; 818 } 819 820 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 821 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 822 adb_bus->status, s->adb_data_in_index, 823 s->adb_data_in_size); 824 825 s->adb_data_in_index++; 826 break; 827 828 default: 829 /* 830 * Otherwise vADBInt indicates end of data. Note that Linux 831 * specifically checks for the sequence 0x0 0xff to confirm the 832 * end of the poll reply, so provide these extra bytes below to 833 * keep it happy 834 */ 835 if (s->adb_data_in_index < s->adb_data_in_size) { 836 /* Next data byte */ 837 *data = s->adb_data_in[s->adb_data_in_index]; 838 ms->b |= VIA1B_vADBInt; 839 } else if (s->adb_data_in_index == s->adb_data_in_size) { 840 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) { 841 /* Bus timeout (no more data) */ 842 *data = 0xff; 843 } else { 844 /* Return 0x0 after reply */ 845 *data = 0; 846 } 847 ms->b &= ~VIA1B_vADBInt; 848 } else { 849 /* Bus timeout (no more data) */ 850 *data = 0xff; 851 ms->b &= ~VIA1B_vADBInt; 852 adb_bus->status = 0; 853 adb_autopoll_unblock(adb_bus); 854 } 855 856 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD", 857 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-", 858 adb_bus->status, s->adb_data_in_index, 859 s->adb_data_in_size); 860 861 if (s->adb_data_in_index <= s->adb_data_in_size) { 862 s->adb_data_in_index++; 863 } 864 break; 865 } 866 867 qemu_irq_raise(s->adb_data_ready); 868 break; 869 } 870 } 871 872 static void via1_adb_update(MacVIAState *m) 873 { 874 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&m->mos6522_via1); 875 MOS6522State *s = MOS6522(v1s); 876 int oldstate, state; 877 878 oldstate = (v1s->last_b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; 879 state = (s->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; 880 881 if (state != oldstate) { 882 if (s->acr & VIA1ACR_vShiftOut) { 883 /* output mode */ 884 adb_via_send(m, state, s->sr); 885 } else { 886 /* input mode */ 887 adb_via_receive(m, state, &s->sr); 888 } 889 } 890 } 891 892 static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size) 893 { 894 MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque); 895 MOS6522State *ms = MOS6522(s); 896 int64_t now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); 897 898 /* 899 * If IRQs are disabled, timers are disabled, but we need to update 900 * VIA1_IRQ_60HZ and VIA1_IRQ_ONE_SECOND bits in the IFR 901 */ 902 903 if (now >= s->next_sixty_hz) { 904 ms->ifr |= VIA1_IRQ_60HZ; 905 via1_sixty_hz_update(s); 906 } 907 if (now >= s->next_second) { 908 ms->ifr |= VIA1_IRQ_ONE_SECOND; 909 via1_one_second_update(s); 910 } 911 912 addr = (addr >> 9) & 0xf; 913 return mos6522_read(ms, addr, size); 914 } 915 916 static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val, 917 unsigned size) 918 { 919 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); 920 MacVIAState *m = container_of(v1s, MacVIAState, mos6522_via1); 921 MOS6522State *ms = MOS6522(v1s); 922 923 addr = (addr >> 9) & 0xf; 924 mos6522_write(ms, addr, val, size); 925 926 switch (addr) { 927 case VIA_REG_B: 928 via1_rtc_update(m); 929 via1_adb_update(m); 930 931 v1s->last_b = ms->b; 932 break; 933 } 934 935 via1_one_second_update(v1s); 936 via1_sixty_hz_update(v1s); 937 } 938 939 static const MemoryRegionOps mos6522_q800_via1_ops = { 940 .read = mos6522_q800_via1_read, 941 .write = mos6522_q800_via1_write, 942 .endianness = DEVICE_BIG_ENDIAN, 943 .valid = { 944 .min_access_size = 1, 945 .max_access_size = 4, 946 }, 947 }; 948 949 static uint64_t mos6522_q800_via2_read(void *opaque, hwaddr addr, unsigned size) 950 { 951 MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque); 952 MOS6522State *ms = MOS6522(s); 953 954 addr = (addr >> 9) & 0xf; 955 return mos6522_read(ms, addr, size); 956 } 957 958 static void mos6522_q800_via2_write(void *opaque, hwaddr addr, uint64_t val, 959 unsigned size) 960 { 961 MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque); 962 MOS6522State *ms = MOS6522(s); 963 964 addr = (addr >> 9) & 0xf; 965 mos6522_write(ms, addr, val, size); 966 } 967 968 static const MemoryRegionOps mos6522_q800_via2_ops = { 969 .read = mos6522_q800_via2_read, 970 .write = mos6522_q800_via2_write, 971 .endianness = DEVICE_BIG_ENDIAN, 972 .valid = { 973 .min_access_size = 1, 974 .max_access_size = 4, 975 }, 976 }; 977 978 static void mac_via_reset(DeviceState *dev) 979 { 980 MacVIAState *m = MAC_VIA(dev); 981 MOS6522Q800VIA1State *v1s = &m->mos6522_via1; 982 ADBBusState *adb_bus = &m->adb_bus; 983 984 adb_set_autopoll_enabled(adb_bus, true); 985 986 timer_del(v1s->sixty_hz_timer); 987 v1s->next_sixty_hz = 0; 988 timer_del(v1s->one_second_timer); 989 v1s->next_second = 0; 990 991 m->cmd = REG_EMPTY; 992 m->alt = REG_EMPTY; 993 } 994 995 static void mac_via_realize(DeviceState *dev, Error **errp) 996 { 997 MacVIAState *m = MAC_VIA(dev); 998 MOS6522State *ms; 999 ADBBusState *adb_bus = &m->adb_bus; 1000 struct tm tm; 1001 int ret; 1002 1003 /* Init VIAs 1 and 2 */ 1004 object_initialize_child(OBJECT(dev), "via1", &m->mos6522_via1, 1005 TYPE_MOS6522_Q800_VIA1); 1006 1007 object_initialize_child(OBJECT(dev), "via2", &m->mos6522_via2, 1008 TYPE_MOS6522_Q800_VIA2); 1009 1010 /* Pass through mos6522 output IRQs */ 1011 ms = MOS6522(&m->mos6522_via1); 1012 object_property_add_alias(OBJECT(dev), "irq[0]", OBJECT(ms), 1013 SYSBUS_DEVICE_GPIO_IRQ "[0]"); 1014 ms = MOS6522(&m->mos6522_via2); 1015 object_property_add_alias(OBJECT(dev), "irq[1]", OBJECT(ms), 1016 SYSBUS_DEVICE_GPIO_IRQ "[0]"); 1017 1018 sysbus_realize(SYS_BUS_DEVICE(&m->mos6522_via1), &error_abort); 1019 sysbus_realize(SYS_BUS_DEVICE(&m->mos6522_via2), &error_abort); 1020 1021 /* Pass through mos6522 input IRQs */ 1022 qdev_pass_gpios(DEVICE(&m->mos6522_via1), dev, "via1-irq"); 1023 qdev_pass_gpios(DEVICE(&m->mos6522_via2), dev, "via2-irq"); 1024 1025 /* VIA 1 */ 1026 m->mos6522_via1.one_second_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 1027 via1_one_second, 1028 &m->mos6522_via1); 1029 m->mos6522_via1.sixty_hz_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1030 via1_sixty_hz, 1031 &m->mos6522_via1); 1032 1033 qemu_get_timedate(&tm, 0); 1034 m->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; 1035 1036 adb_register_autopoll_callback(adb_bus, adb_via_poll, m); 1037 m->adb_data_ready = qdev_get_gpio_in_named(dev, "via1-irq", 1038 VIA1_IRQ_ADB_READY_BIT); 1039 1040 if (m->blk) { 1041 int64_t len = blk_getlength(m->blk); 1042 if (len < 0) { 1043 error_setg_errno(errp, -len, 1044 "could not get length of backing image"); 1045 return; 1046 } 1047 ret = blk_set_perm(m->blk, 1048 BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, 1049 BLK_PERM_ALL, errp); 1050 if (ret < 0) { 1051 return; 1052 } 1053 1054 len = blk_pread(m->blk, 0, m->mos6522_via1.PRAM, 1055 sizeof(m->mos6522_via1.PRAM)); 1056 if (len != sizeof(m->mos6522_via1.PRAM)) { 1057 error_setg(errp, "can't read PRAM contents"); 1058 return; 1059 } 1060 } 1061 } 1062 1063 static void mac_via_init(Object *obj) 1064 { 1065 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1066 MacVIAState *m = MAC_VIA(obj); 1067 1068 /* MMIO */ 1069 memory_region_init(&m->mmio, obj, "mac-via", 2 * VIA_SIZE); 1070 sysbus_init_mmio(sbd, &m->mmio); 1071 1072 memory_region_init_io(&m->via1mem, obj, &mos6522_q800_via1_ops, 1073 &m->mos6522_via1, "via1", VIA_SIZE); 1074 memory_region_add_subregion(&m->mmio, 0x0, &m->via1mem); 1075 1076 memory_region_init_io(&m->via2mem, obj, &mos6522_q800_via2_ops, 1077 &m->mos6522_via2, "via2", VIA_SIZE); 1078 memory_region_add_subregion(&m->mmio, VIA_SIZE, &m->via2mem); 1079 1080 /* ADB */ 1081 qbus_create_inplace((BusState *)&m->adb_bus, sizeof(m->adb_bus), 1082 TYPE_ADB_BUS, DEVICE(obj), "adb.0"); 1083 } 1084 1085 static void postload_update_cb(void *opaque, bool running, RunState state) 1086 { 1087 MacVIAState *m = MAC_VIA(opaque); 1088 1089 qemu_del_vm_change_state_handler(m->vmstate); 1090 m->vmstate = NULL; 1091 1092 pram_update(m); 1093 } 1094 1095 static int mac_via_post_load(void *opaque, int version_id) 1096 { 1097 MacVIAState *m = MAC_VIA(opaque); 1098 1099 if (m->blk) { 1100 m->vmstate = qemu_add_vm_change_state_handler(postload_update_cb, 1101 m); 1102 } 1103 1104 return 0; 1105 } 1106 1107 static const VMStateDescription vmstate_mac_via = { 1108 .name = "mac-via", 1109 .version_id = 2, 1110 .minimum_version_id = 2, 1111 .post_load = mac_via_post_load, 1112 .fields = (VMStateField[]) { 1113 /* VIAs */ 1114 VMSTATE_STRUCT(mos6522_via1.parent_obj, MacVIAState, 0, vmstate_mos6522, 1115 MOS6522State), 1116 VMSTATE_UINT8(mos6522_via1.last_b, MacVIAState), 1117 VMSTATE_BUFFER(mos6522_via1.PRAM, MacVIAState), 1118 VMSTATE_TIMER_PTR(mos6522_via1.one_second_timer, MacVIAState), 1119 VMSTATE_INT64(mos6522_via1.next_second, MacVIAState), 1120 VMSTATE_TIMER_PTR(mos6522_via1.sixty_hz_timer, MacVIAState), 1121 VMSTATE_INT64(mos6522_via1.next_sixty_hz, MacVIAState), 1122 VMSTATE_STRUCT(mos6522_via2.parent_obj, MacVIAState, 0, vmstate_mos6522, 1123 MOS6522State), 1124 /* RTC */ 1125 VMSTATE_UINT32(tick_offset, MacVIAState), 1126 VMSTATE_UINT8(data_out, MacVIAState), 1127 VMSTATE_INT32(data_out_cnt, MacVIAState), 1128 VMSTATE_UINT8(data_in, MacVIAState), 1129 VMSTATE_UINT8(data_in_cnt, MacVIAState), 1130 VMSTATE_UINT8(cmd, MacVIAState), 1131 VMSTATE_INT32(wprotect, MacVIAState), 1132 VMSTATE_INT32(alt, MacVIAState), 1133 /* ADB */ 1134 VMSTATE_INT32(adb_data_in_size, MacVIAState), 1135 VMSTATE_INT32(adb_data_in_index, MacVIAState), 1136 VMSTATE_INT32(adb_data_out_index, MacVIAState), 1137 VMSTATE_BUFFER(adb_data_in, MacVIAState), 1138 VMSTATE_BUFFER(adb_data_out, MacVIAState), 1139 VMSTATE_UINT8(adb_autopoll_cmd, MacVIAState), 1140 VMSTATE_END_OF_LIST() 1141 } 1142 }; 1143 1144 static Property mac_via_properties[] = { 1145 DEFINE_PROP_DRIVE("drive", MacVIAState, blk), 1146 DEFINE_PROP_END_OF_LIST(), 1147 }; 1148 1149 static void mac_via_class_init(ObjectClass *oc, void *data) 1150 { 1151 DeviceClass *dc = DEVICE_CLASS(oc); 1152 1153 dc->realize = mac_via_realize; 1154 dc->reset = mac_via_reset; 1155 dc->vmsd = &vmstate_mac_via; 1156 device_class_set_props(dc, mac_via_properties); 1157 } 1158 1159 static TypeInfo mac_via_info = { 1160 .name = TYPE_MAC_VIA, 1161 .parent = TYPE_SYS_BUS_DEVICE, 1162 .instance_size = sizeof(MacVIAState), 1163 .instance_init = mac_via_init, 1164 .class_init = mac_via_class_init, 1165 }; 1166 1167 /* VIA 1 */ 1168 static void mos6522_q800_via1_reset(DeviceState *dev) 1169 { 1170 MOS6522State *ms = MOS6522(dev); 1171 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 1172 1173 mdc->parent_reset(dev); 1174 1175 ms->timers[0].frequency = VIA_TIMER_FREQ; 1176 ms->timers[1].frequency = VIA_TIMER_FREQ; 1177 1178 ms->b = VIA1B_vADB_StateMask | VIA1B_vADBInt | VIA1B_vRTCEnb; 1179 } 1180 1181 static void mos6522_q800_via1_init(Object *obj) 1182 { 1183 qdev_init_gpio_in_named(DEVICE(obj), via1_irq_request, "via1-irq", 1184 VIA1_IRQ_NB); 1185 } 1186 1187 static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data) 1188 { 1189 DeviceClass *dc = DEVICE_CLASS(oc); 1190 1191 dc->reset = mos6522_q800_via1_reset; 1192 } 1193 1194 static const TypeInfo mos6522_q800_via1_type_info = { 1195 .name = TYPE_MOS6522_Q800_VIA1, 1196 .parent = TYPE_MOS6522, 1197 .instance_size = sizeof(MOS6522Q800VIA1State), 1198 .instance_init = mos6522_q800_via1_init, 1199 .class_init = mos6522_q800_via1_class_init, 1200 }; 1201 1202 /* VIA 2 */ 1203 static void mos6522_q800_via2_portB_write(MOS6522State *s) 1204 { 1205 if (s->dirb & VIA2B_vPower && (s->b & VIA2B_vPower) == 0) { 1206 /* shutdown */ 1207 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 1208 } 1209 } 1210 1211 static void mos6522_q800_via2_reset(DeviceState *dev) 1212 { 1213 MOS6522State *ms = MOS6522(dev); 1214 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); 1215 1216 mdc->parent_reset(dev); 1217 1218 ms->timers[0].frequency = VIA_TIMER_FREQ; 1219 ms->timers[1].frequency = VIA_TIMER_FREQ; 1220 1221 ms->dirb = 0; 1222 ms->b = 0; 1223 } 1224 1225 static void mos6522_q800_via2_init(Object *obj) 1226 { 1227 qdev_init_gpio_in_named(DEVICE(obj), via2_irq_request, "via2-irq", 1228 VIA2_IRQ_NB); 1229 } 1230 1231 static void mos6522_q800_via2_class_init(ObjectClass *oc, void *data) 1232 { 1233 DeviceClass *dc = DEVICE_CLASS(oc); 1234 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc); 1235 1236 dc->reset = mos6522_q800_via2_reset; 1237 mdc->portB_write = mos6522_q800_via2_portB_write; 1238 } 1239 1240 static const TypeInfo mos6522_q800_via2_type_info = { 1241 .name = TYPE_MOS6522_Q800_VIA2, 1242 .parent = TYPE_MOS6522, 1243 .instance_size = sizeof(MOS6522Q800VIA2State), 1244 .instance_init = mos6522_q800_via2_init, 1245 .class_init = mos6522_q800_via2_class_init, 1246 }; 1247 1248 static void mac_via_register_types(void) 1249 { 1250 type_register_static(&mos6522_q800_via1_type_info); 1251 type_register_static(&mos6522_q800_via2_type_info); 1252 type_register_static(&mac_via_info); 1253 } 1254 1255 type_init(mac_via_register_types); 1256