1 /* 2 * ARM IoTKit system control element 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* 13 * This is a model of the "system control element" which is part of the 14 * Arm IoTKit and documented in 15 * https://developer.arm.com/documentation/ecm0601256/latest 16 * Specifically, it implements the "system control register" blocks. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/bitops.h" 21 #include "qemu/log.h" 22 #include "qemu/module.h" 23 #include "sysemu/runstate.h" 24 #include "trace.h" 25 #include "qapi/error.h" 26 #include "hw/sysbus.h" 27 #include "migration/vmstate.h" 28 #include "hw/registerfields.h" 29 #include "hw/misc/iotkit-sysctl.h" 30 #include "hw/qdev-properties.h" 31 #include "hw/arm/armsse-version.h" 32 #include "target/arm/arm-powerctl.h" 33 #include "target/arm/cpu.h" 34 35 REG32(SECDBGSTAT, 0x0) 36 REG32(SECDBGSET, 0x4) 37 REG32(SECDBGCLR, 0x8) 38 REG32(SCSECCTRL, 0xc) 39 REG32(FCLK_DIV, 0x10) 40 REG32(SYSCLK_DIV, 0x14) 41 REG32(CLOCK_FORCE, 0x18) 42 REG32(RESET_SYNDROME, 0x100) 43 REG32(RESET_MASK, 0x104) 44 REG32(SWRESET, 0x108) 45 FIELD(SWRESET, SWRESETREQ, 9, 1) 46 REG32(GRETREG, 0x10c) 47 REG32(INITSVTOR0, 0x110) 48 FIELD(INITSVTOR0, LOCK, 0, 1) 49 FIELD(INITSVTOR0, VTOR, 7, 25) 50 REG32(INITSVTOR1, 0x114) 51 REG32(CPUWAIT, 0x118) 52 REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */ 53 REG32(WICCTRL, 0x120) 54 REG32(EWCTRL, 0x124) 55 REG32(PWRCTRL, 0x1fc) 56 FIELD(PWRCTRL, PPU_ACCESS_UNLOCK, 0, 1) 57 FIELD(PWRCTRL, PPU_ACCESS_FILTER, 1, 1) 58 REG32(PDCM_PD_SYS_SENSE, 0x200) 59 REG32(PDCM_PD_CPU0_SENSE, 0x204) 60 REG32(PDCM_PD_SRAM0_SENSE, 0x20c) 61 REG32(PDCM_PD_SRAM1_SENSE, 0x210) 62 REG32(PDCM_PD_SRAM2_SENSE, 0x214) /* PDCM_PD_VMR0_SENSE on SSE300 */ 63 REG32(PDCM_PD_SRAM3_SENSE, 0x218) /* PDCM_PD_VMR1_SENSE on SSE300 */ 64 REG32(PID4, 0xfd0) 65 REG32(PID5, 0xfd4) 66 REG32(PID6, 0xfd8) 67 REG32(PID7, 0xfdc) 68 REG32(PID0, 0xfe0) 69 REG32(PID1, 0xfe4) 70 REG32(PID2, 0xfe8) 71 REG32(PID3, 0xfec) 72 REG32(CID0, 0xff0) 73 REG32(CID1, 0xff4) 74 REG32(CID2, 0xff8) 75 REG32(CID3, 0xffc) 76 77 /* PID/CID values */ 78 static const int sysctl_id[] = { 79 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ 80 0x54, 0xb8, 0x0b, 0x00, /* PID0..PID3 */ 81 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ 82 }; 83 84 /* 85 * Set the initial secure vector table offset address for the core. 86 * This will take effect when the CPU next resets. 87 */ 88 static void set_init_vtor(uint64_t cpuid, uint32_t vtor) 89 { 90 Object *cpuobj = OBJECT(arm_get_cpu_by_id(cpuid)); 91 92 if (cpuobj) { 93 if (object_property_find(cpuobj, "init-svtor")) { 94 object_property_set_uint(cpuobj, "init-svtor", vtor, &error_abort); 95 } 96 } 97 } 98 99 static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset, 100 unsigned size) 101 { 102 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque); 103 uint64_t r; 104 105 switch (offset) { 106 case A_SECDBGSTAT: 107 r = s->secure_debug; 108 break; 109 case A_SCSECCTRL: 110 switch (s->sse_version) { 111 case ARMSSE_IOTKIT: 112 goto bad_offset; 113 case ARMSSE_SSE200: 114 case ARMSSE_SSE300: 115 r = s->scsecctrl; 116 break; 117 default: 118 g_assert_not_reached(); 119 } 120 break; 121 case A_FCLK_DIV: 122 switch (s->sse_version) { 123 case ARMSSE_IOTKIT: 124 goto bad_offset; 125 case ARMSSE_SSE200: 126 case ARMSSE_SSE300: 127 r = s->fclk_div; 128 break; 129 default: 130 g_assert_not_reached(); 131 } 132 break; 133 case A_SYSCLK_DIV: 134 switch (s->sse_version) { 135 case ARMSSE_IOTKIT: 136 goto bad_offset; 137 case ARMSSE_SSE200: 138 case ARMSSE_SSE300: 139 r = s->sysclk_div; 140 break; 141 default: 142 g_assert_not_reached(); 143 } 144 break; 145 case A_CLOCK_FORCE: 146 switch (s->sse_version) { 147 case ARMSSE_IOTKIT: 148 goto bad_offset; 149 case ARMSSE_SSE200: 150 case ARMSSE_SSE300: 151 r = s->clock_force; 152 break; 153 default: 154 g_assert_not_reached(); 155 } 156 break; 157 case A_RESET_SYNDROME: 158 r = s->reset_syndrome; 159 break; 160 case A_RESET_MASK: 161 r = s->reset_mask; 162 break; 163 case A_GRETREG: 164 r = s->gretreg; 165 break; 166 case A_INITSVTOR0: 167 r = s->initsvtor0; 168 break; 169 case A_INITSVTOR1: 170 switch (s->sse_version) { 171 case ARMSSE_IOTKIT: 172 goto bad_offset; 173 case ARMSSE_SSE200: 174 r = s->initsvtor1; 175 break; 176 case ARMSSE_SSE300: 177 goto bad_offset; 178 default: 179 g_assert_not_reached(); 180 } 181 break; 182 case A_CPUWAIT: 183 switch (s->sse_version) { 184 case ARMSSE_IOTKIT: 185 case ARMSSE_SSE200: 186 r = s->cpuwait; 187 break; 188 case ARMSSE_SSE300: 189 /* In SSE300 this is reserved (for INITSVTOR2) */ 190 goto bad_offset; 191 default: 192 g_assert_not_reached(); 193 } 194 break; 195 case A_NMI_ENABLE: 196 switch (s->sse_version) { 197 case ARMSSE_IOTKIT: 198 /* In IoTKit this is named BUSWAIT but marked reserved, R/O, zero */ 199 r = 0; 200 break; 201 case ARMSSE_SSE200: 202 r = s->nmi_enable; 203 break; 204 case ARMSSE_SSE300: 205 /* In SSE300 this is reserved (for INITSVTOR3) */ 206 goto bad_offset; 207 default: 208 g_assert_not_reached(); 209 } 210 break; 211 case A_WICCTRL: 212 switch (s->sse_version) { 213 case ARMSSE_IOTKIT: 214 case ARMSSE_SSE200: 215 r = s->wicctrl; 216 break; 217 case ARMSSE_SSE300: 218 /* In SSE300 this offset is CPUWAIT */ 219 r = s->cpuwait; 220 break; 221 default: 222 g_assert_not_reached(); 223 } 224 break; 225 case A_EWCTRL: 226 switch (s->sse_version) { 227 case ARMSSE_IOTKIT: 228 goto bad_offset; 229 case ARMSSE_SSE200: 230 r = s->ewctrl; 231 break; 232 case ARMSSE_SSE300: 233 /* In SSE300 this offset is is NMI_ENABLE */ 234 r = s->nmi_enable; 235 break; 236 default: 237 g_assert_not_reached(); 238 } 239 break; 240 case A_PWRCTRL: 241 switch (s->sse_version) { 242 case ARMSSE_IOTKIT: 243 case ARMSSE_SSE200: 244 goto bad_offset; 245 case ARMSSE_SSE300: 246 r = s->pwrctrl; 247 break; 248 default: 249 g_assert_not_reached(); 250 } 251 break; 252 case A_PDCM_PD_SYS_SENSE: 253 switch (s->sse_version) { 254 case ARMSSE_IOTKIT: 255 goto bad_offset; 256 case ARMSSE_SSE200: 257 case ARMSSE_SSE300: 258 r = s->pdcm_pd_sys_sense; 259 break; 260 default: 261 g_assert_not_reached(); 262 } 263 break; 264 case A_PDCM_PD_CPU0_SENSE: 265 switch (s->sse_version) { 266 case ARMSSE_IOTKIT: 267 case ARMSSE_SSE200: 268 goto bad_offset; 269 case ARMSSE_SSE300: 270 r = s->pdcm_pd_cpu0_sense; 271 break; 272 default: 273 g_assert_not_reached(); 274 } 275 break; 276 case A_PDCM_PD_SRAM0_SENSE: 277 switch (s->sse_version) { 278 case ARMSSE_IOTKIT: 279 goto bad_offset; 280 case ARMSSE_SSE200: 281 r = s->pdcm_pd_sram0_sense; 282 break; 283 case ARMSSE_SSE300: 284 goto bad_offset; 285 default: 286 g_assert_not_reached(); 287 } 288 break; 289 case A_PDCM_PD_SRAM1_SENSE: 290 switch (s->sse_version) { 291 case ARMSSE_IOTKIT: 292 goto bad_offset; 293 case ARMSSE_SSE200: 294 r = s->pdcm_pd_sram1_sense; 295 break; 296 case ARMSSE_SSE300: 297 goto bad_offset; 298 default: 299 g_assert_not_reached(); 300 } 301 break; 302 case A_PDCM_PD_SRAM2_SENSE: 303 switch (s->sse_version) { 304 case ARMSSE_IOTKIT: 305 goto bad_offset; 306 case ARMSSE_SSE200: 307 r = s->pdcm_pd_sram2_sense; 308 break; 309 case ARMSSE_SSE300: 310 r = s->pdcm_pd_vmr0_sense; 311 break; 312 default: 313 g_assert_not_reached(); 314 } 315 break; 316 case A_PDCM_PD_SRAM3_SENSE: 317 switch (s->sse_version) { 318 case ARMSSE_IOTKIT: 319 goto bad_offset; 320 case ARMSSE_SSE200: 321 r = s->pdcm_pd_sram3_sense; 322 break; 323 case ARMSSE_SSE300: 324 r = s->pdcm_pd_vmr1_sense; 325 break; 326 default: 327 g_assert_not_reached(); 328 } 329 break; 330 case A_PID4 ... A_CID3: 331 r = sysctl_id[(offset - A_PID4) / 4]; 332 break; 333 case A_SECDBGSET: 334 case A_SECDBGCLR: 335 case A_SWRESET: 336 qemu_log_mask(LOG_GUEST_ERROR, 337 "IoTKit SysCtl read: read of WO offset %x\n", 338 (int)offset); 339 r = 0; 340 break; 341 default: 342 bad_offset: 343 qemu_log_mask(LOG_GUEST_ERROR, 344 "IoTKit SysCtl read: bad offset %x\n", (int)offset); 345 r = 0; 346 break; 347 } 348 trace_iotkit_sysctl_read(offset, r, size); 349 return r; 350 } 351 352 static void cpuwait_write(IoTKitSysCtl *s, uint32_t value) 353 { 354 int num_cpus = (s->sse_version == ARMSSE_SSE300) ? 1 : 2; 355 int i; 356 357 for (i = 0; i < num_cpus; i++) { 358 uint32_t mask = 1 << i; 359 if ((s->cpuwait & mask) && !(value & mask)) { 360 /* Powering up CPU 0 */ 361 arm_set_cpu_on_and_reset(i); 362 } 363 } 364 s->cpuwait = value; 365 } 366 367 static void iotkit_sysctl_write(void *opaque, hwaddr offset, 368 uint64_t value, unsigned size) 369 { 370 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque); 371 372 trace_iotkit_sysctl_write(offset, value, size); 373 374 /* 375 * Most of the state here has to do with control of reset and 376 * similar kinds of power up -- for instance the guest can ask 377 * what the reason for the last reset was, or forbid reset for 378 * some causes (like the non-secure watchdog). Most of this is 379 * not relevant to QEMU, which doesn't really model anything other 380 * than a full power-on reset. 381 * We just model the registers as reads-as-written. 382 */ 383 384 switch (offset) { 385 case A_RESET_SYNDROME: 386 qemu_log_mask(LOG_UNIMP, 387 "IoTKit SysCtl RESET_SYNDROME unimplemented\n"); 388 s->reset_syndrome = value; 389 break; 390 case A_RESET_MASK: 391 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl RESET_MASK unimplemented\n"); 392 s->reset_mask = value; 393 break; 394 case A_GRETREG: 395 /* 396 * General retention register, which is only reset by a power-on 397 * reset. Technically this implementation is complete, since 398 * QEMU only supports power-on resets... 399 */ 400 s->gretreg = value; 401 break; 402 case A_INITSVTOR0: 403 switch (s->sse_version) { 404 case ARMSSE_SSE300: 405 /* SSE300 has a LOCK bit which prevents further writes when set */ 406 if (s->initsvtor0 & R_INITSVTOR0_LOCK_MASK) { 407 qemu_log_mask(LOG_GUEST_ERROR, 408 "IoTKit INITSVTOR0 write when register locked\n"); 409 break; 410 } 411 s->initsvtor0 = value; 412 set_init_vtor(0, s->initsvtor0 & R_INITSVTOR0_VTOR_MASK); 413 break; 414 case ARMSSE_IOTKIT: 415 case ARMSSE_SSE200: 416 s->initsvtor0 = value; 417 set_init_vtor(0, s->initsvtor0); 418 break; 419 default: 420 g_assert_not_reached(); 421 } 422 break; 423 case A_CPUWAIT: 424 switch (s->sse_version) { 425 case ARMSSE_IOTKIT: 426 case ARMSSE_SSE200: 427 cpuwait_write(s, value); 428 break; 429 case ARMSSE_SSE300: 430 /* In SSE300 this is reserved (for INITSVTOR2) */ 431 goto bad_offset; 432 default: 433 g_assert_not_reached(); 434 } 435 break; 436 case A_WICCTRL: 437 switch (s->sse_version) { 438 case ARMSSE_IOTKIT: 439 case ARMSSE_SSE200: 440 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl WICCTRL unimplemented\n"); 441 s->wicctrl = value; 442 break; 443 case ARMSSE_SSE300: 444 /* In SSE300 this offset is CPUWAIT */ 445 cpuwait_write(s, value); 446 break; 447 default: 448 g_assert_not_reached(); 449 } 450 break; 451 case A_SECDBGSET: 452 /* write-1-to-set */ 453 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SECDBGSET unimplemented\n"); 454 s->secure_debug |= value; 455 break; 456 case A_SECDBGCLR: 457 /* write-1-to-clear */ 458 s->secure_debug &= ~value; 459 break; 460 case A_SWRESET: 461 /* One w/o bit to request a reset; all other bits reserved */ 462 if (value & R_SWRESET_SWRESETREQ_MASK) { 463 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 464 } 465 break; 466 case A_SCSECCTRL: 467 switch (s->sse_version) { 468 case ARMSSE_IOTKIT: 469 goto bad_offset; 470 case ARMSSE_SSE200: 471 case ARMSSE_SSE300: 472 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n"); 473 s->scsecctrl = value; 474 break; 475 default: 476 g_assert_not_reached(); 477 } 478 break; 479 case A_FCLK_DIV: 480 switch (s->sse_version) { 481 case ARMSSE_IOTKIT: 482 goto bad_offset; 483 case ARMSSE_SSE200: 484 case ARMSSE_SSE300: 485 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n"); 486 s->fclk_div = value; 487 break; 488 default: 489 g_assert_not_reached(); 490 } 491 break; 492 case A_SYSCLK_DIV: 493 switch (s->sse_version) { 494 case ARMSSE_IOTKIT: 495 goto bad_offset; 496 case ARMSSE_SSE200: 497 case ARMSSE_SSE300: 498 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n"); 499 s->sysclk_div = value; 500 break; 501 default: 502 g_assert_not_reached(); 503 } 504 break; 505 case A_CLOCK_FORCE: 506 switch (s->sse_version) { 507 case ARMSSE_IOTKIT: 508 goto bad_offset; 509 case ARMSSE_SSE200: 510 case ARMSSE_SSE300: 511 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\n"); 512 s->clock_force = value; 513 break; 514 default: 515 g_assert_not_reached(); 516 } 517 break; 518 case A_INITSVTOR1: 519 switch (s->sse_version) { 520 case ARMSSE_IOTKIT: 521 goto bad_offset; 522 case ARMSSE_SSE200: 523 s->initsvtor1 = value; 524 set_init_vtor(1, s->initsvtor1); 525 break; 526 case ARMSSE_SSE300: 527 goto bad_offset; 528 default: 529 g_assert_not_reached(); 530 } 531 break; 532 case A_EWCTRL: 533 switch (s->sse_version) { 534 case ARMSSE_IOTKIT: 535 goto bad_offset; 536 case ARMSSE_SSE200: 537 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n"); 538 s->ewctrl = value; 539 break; 540 case ARMSSE_SSE300: 541 /* In SSE300 this offset is is NMI_ENABLE */ 542 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n"); 543 s->nmi_enable = value; 544 break; 545 default: 546 g_assert_not_reached(); 547 } 548 break; 549 case A_PWRCTRL: 550 switch (s->sse_version) { 551 case ARMSSE_IOTKIT: 552 case ARMSSE_SSE200: 553 goto bad_offset; 554 case ARMSSE_SSE300: 555 if (!(s->pwrctrl & R_PWRCTRL_PPU_ACCESS_UNLOCK_MASK)) { 556 qemu_log_mask(LOG_GUEST_ERROR, 557 "IoTKit PWRCTRL write when register locked\n"); 558 break; 559 } 560 s->pwrctrl = value; 561 break; 562 default: 563 g_assert_not_reached(); 564 } 565 break; 566 case A_PDCM_PD_SYS_SENSE: 567 switch (s->sse_version) { 568 case ARMSSE_IOTKIT: 569 goto bad_offset; 570 case ARMSSE_SSE200: 571 case ARMSSE_SSE300: 572 qemu_log_mask(LOG_UNIMP, 573 "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n"); 574 s->pdcm_pd_sys_sense = value; 575 break; 576 default: 577 g_assert_not_reached(); 578 } 579 break; 580 case A_PDCM_PD_CPU0_SENSE: 581 switch (s->sse_version) { 582 case ARMSSE_IOTKIT: 583 case ARMSSE_SSE200: 584 goto bad_offset; 585 case ARMSSE_SSE300: 586 qemu_log_mask(LOG_UNIMP, 587 "IoTKit SysCtl PDCM_PD_CPU0_SENSE unimplemented\n"); 588 s->pdcm_pd_cpu0_sense = value; 589 break; 590 default: 591 g_assert_not_reached(); 592 } 593 break; 594 case A_PDCM_PD_SRAM0_SENSE: 595 switch (s->sse_version) { 596 case ARMSSE_IOTKIT: 597 goto bad_offset; 598 case ARMSSE_SSE200: 599 qemu_log_mask(LOG_UNIMP, 600 "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n"); 601 s->pdcm_pd_sram0_sense = value; 602 break; 603 case ARMSSE_SSE300: 604 goto bad_offset; 605 default: 606 g_assert_not_reached(); 607 } 608 break; 609 case A_PDCM_PD_SRAM1_SENSE: 610 switch (s->sse_version) { 611 case ARMSSE_IOTKIT: 612 goto bad_offset; 613 case ARMSSE_SSE200: 614 qemu_log_mask(LOG_UNIMP, 615 "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n"); 616 s->pdcm_pd_sram1_sense = value; 617 break; 618 case ARMSSE_SSE300: 619 goto bad_offset; 620 default: 621 g_assert_not_reached(); 622 } 623 break; 624 case A_PDCM_PD_SRAM2_SENSE: 625 switch (s->sse_version) { 626 case ARMSSE_IOTKIT: 627 goto bad_offset; 628 case ARMSSE_SSE200: 629 qemu_log_mask(LOG_UNIMP, 630 "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n"); 631 s->pdcm_pd_sram2_sense = value; 632 break; 633 case ARMSSE_SSE300: 634 qemu_log_mask(LOG_UNIMP, 635 "IoTKit SysCtl PDCM_PD_VMR0_SENSE unimplemented\n"); 636 s->pdcm_pd_vmr0_sense = value; 637 break; 638 default: 639 g_assert_not_reached(); 640 } 641 break; 642 case A_PDCM_PD_SRAM3_SENSE: 643 switch (s->sse_version) { 644 case ARMSSE_IOTKIT: 645 goto bad_offset; 646 case ARMSSE_SSE200: 647 qemu_log_mask(LOG_UNIMP, 648 "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n"); 649 s->pdcm_pd_sram3_sense = value; 650 break; 651 case ARMSSE_SSE300: 652 qemu_log_mask(LOG_UNIMP, 653 "IoTKit SysCtl PDCM_PD_VMR1_SENSE unimplemented\n"); 654 s->pdcm_pd_vmr1_sense = value; 655 break; 656 default: 657 g_assert_not_reached(); 658 } 659 break; 660 case A_NMI_ENABLE: 661 /* In IoTKit this is BUSWAIT: reserved, R/O, zero */ 662 switch (s->sse_version) { 663 case ARMSSE_IOTKIT: 664 goto ro_offset; 665 case ARMSSE_SSE200: 666 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n"); 667 s->nmi_enable = value; 668 break; 669 case ARMSSE_SSE300: 670 /* In SSE300 this is reserved (for INITSVTOR3) */ 671 goto bad_offset; 672 default: 673 g_assert_not_reached(); 674 } 675 break; 676 case A_SECDBGSTAT: 677 case A_PID4 ... A_CID3: 678 ro_offset: 679 qemu_log_mask(LOG_GUEST_ERROR, 680 "IoTKit SysCtl write: write of RO offset %x\n", 681 (int)offset); 682 break; 683 default: 684 bad_offset: 685 qemu_log_mask(LOG_GUEST_ERROR, 686 "IoTKit SysCtl write: bad offset %x\n", (int)offset); 687 break; 688 } 689 } 690 691 static const MemoryRegionOps iotkit_sysctl_ops = { 692 .read = iotkit_sysctl_read, 693 .write = iotkit_sysctl_write, 694 .endianness = DEVICE_LITTLE_ENDIAN, 695 /* byte/halfword accesses are just zero-padded on reads and writes */ 696 .impl.min_access_size = 4, 697 .impl.max_access_size = 4, 698 .valid.min_access_size = 1, 699 .valid.max_access_size = 4, 700 }; 701 702 static void iotkit_sysctl_reset(DeviceState *dev) 703 { 704 IoTKitSysCtl *s = IOTKIT_SYSCTL(dev); 705 706 trace_iotkit_sysctl_reset(); 707 s->secure_debug = 0; 708 s->reset_syndrome = 1; 709 s->reset_mask = 0; 710 s->gretreg = 0; 711 s->initsvtor0 = s->initsvtor0_rst; 712 s->initsvtor1 = s->initsvtor1_rst; 713 s->cpuwait = s->cpuwait_rst; 714 s->wicctrl = 0; 715 s->scsecctrl = 0; 716 s->fclk_div = 0; 717 s->sysclk_div = 0; 718 s->clock_force = 0; 719 s->nmi_enable = 0; 720 s->ewctrl = 0; 721 s->pwrctrl = 0x3; 722 s->pdcm_pd_sys_sense = 0x7f; 723 s->pdcm_pd_sram0_sense = 0; 724 s->pdcm_pd_sram1_sense = 0; 725 s->pdcm_pd_sram2_sense = 0; 726 s->pdcm_pd_sram3_sense = 0; 727 s->pdcm_pd_cpu0_sense = 0; 728 s->pdcm_pd_vmr0_sense = 0; 729 s->pdcm_pd_vmr1_sense = 0; 730 } 731 732 static void iotkit_sysctl_init(Object *obj) 733 { 734 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 735 IoTKitSysCtl *s = IOTKIT_SYSCTL(obj); 736 737 memory_region_init_io(&s->iomem, obj, &iotkit_sysctl_ops, 738 s, "iotkit-sysctl", 0x1000); 739 sysbus_init_mmio(sbd, &s->iomem); 740 } 741 742 static void iotkit_sysctl_realize(DeviceState *dev, Error **errp) 743 { 744 IoTKitSysCtl *s = IOTKIT_SYSCTL(dev); 745 746 if (!armsse_version_valid(s->sse_version)) { 747 error_setg(errp, "invalid sse-version value %d", s->sse_version); 748 return; 749 } 750 } 751 752 static bool sse300_needed(void *opaque) 753 { 754 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque); 755 756 return s->sse_version == ARMSSE_SSE300; 757 } 758 759 static const VMStateDescription iotkit_sysctl_sse300_vmstate = { 760 .name = "iotkit-sysctl/sse-300", 761 .version_id = 1, 762 .minimum_version_id = 1, 763 .needed = sse300_needed, 764 .fields = (VMStateField[]) { 765 VMSTATE_UINT32(pwrctrl, IoTKitSysCtl), 766 VMSTATE_UINT32(pdcm_pd_cpu0_sense, IoTKitSysCtl), 767 VMSTATE_UINT32(pdcm_pd_vmr0_sense, IoTKitSysCtl), 768 VMSTATE_UINT32(pdcm_pd_vmr1_sense, IoTKitSysCtl), 769 VMSTATE_END_OF_LIST() 770 } 771 }; 772 773 static bool sse200_needed(void *opaque) 774 { 775 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque); 776 777 return s->sse_version != ARMSSE_IOTKIT; 778 } 779 780 static const VMStateDescription iotkit_sysctl_sse200_vmstate = { 781 .name = "iotkit-sysctl/sse-200", 782 .version_id = 1, 783 .minimum_version_id = 1, 784 .needed = sse200_needed, 785 .fields = (VMStateField[]) { 786 VMSTATE_UINT32(scsecctrl, IoTKitSysCtl), 787 VMSTATE_UINT32(fclk_div, IoTKitSysCtl), 788 VMSTATE_UINT32(sysclk_div, IoTKitSysCtl), 789 VMSTATE_UINT32(clock_force, IoTKitSysCtl), 790 VMSTATE_UINT32(initsvtor1, IoTKitSysCtl), 791 VMSTATE_UINT32(nmi_enable, IoTKitSysCtl), 792 VMSTATE_UINT32(pdcm_pd_sys_sense, IoTKitSysCtl), 793 VMSTATE_UINT32(pdcm_pd_sram0_sense, IoTKitSysCtl), 794 VMSTATE_UINT32(pdcm_pd_sram1_sense, IoTKitSysCtl), 795 VMSTATE_UINT32(pdcm_pd_sram2_sense, IoTKitSysCtl), 796 VMSTATE_UINT32(pdcm_pd_sram3_sense, IoTKitSysCtl), 797 VMSTATE_END_OF_LIST() 798 } 799 }; 800 801 static const VMStateDescription iotkit_sysctl_vmstate = { 802 .name = "iotkit-sysctl", 803 .version_id = 1, 804 .minimum_version_id = 1, 805 .fields = (VMStateField[]) { 806 VMSTATE_UINT32(secure_debug, IoTKitSysCtl), 807 VMSTATE_UINT32(reset_syndrome, IoTKitSysCtl), 808 VMSTATE_UINT32(reset_mask, IoTKitSysCtl), 809 VMSTATE_UINT32(gretreg, IoTKitSysCtl), 810 VMSTATE_UINT32(initsvtor0, IoTKitSysCtl), 811 VMSTATE_UINT32(cpuwait, IoTKitSysCtl), 812 VMSTATE_UINT32(wicctrl, IoTKitSysCtl), 813 VMSTATE_END_OF_LIST() 814 }, 815 .subsections = (const VMStateDescription*[]) { 816 &iotkit_sysctl_sse200_vmstate, 817 &iotkit_sysctl_sse300_vmstate, 818 NULL 819 } 820 }; 821 822 static Property iotkit_sysctl_props[] = { 823 DEFINE_PROP_UINT32("sse-version", IoTKitSysCtl, sse_version, 0), 824 DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl, cpuwait_rst, 0), 825 DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl, initsvtor0_rst, 826 0x10000000), 827 DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl, initsvtor1_rst, 828 0x10000000), 829 DEFINE_PROP_END_OF_LIST() 830 }; 831 832 static void iotkit_sysctl_class_init(ObjectClass *klass, void *data) 833 { 834 DeviceClass *dc = DEVICE_CLASS(klass); 835 836 dc->vmsd = &iotkit_sysctl_vmstate; 837 dc->reset = iotkit_sysctl_reset; 838 device_class_set_props(dc, iotkit_sysctl_props); 839 dc->realize = iotkit_sysctl_realize; 840 } 841 842 static const TypeInfo iotkit_sysctl_info = { 843 .name = TYPE_IOTKIT_SYSCTL, 844 .parent = TYPE_SYS_BUS_DEVICE, 845 .instance_size = sizeof(IoTKitSysCtl), 846 .instance_init = iotkit_sysctl_init, 847 .class_init = iotkit_sysctl_class_init, 848 }; 849 850 static void iotkit_sysctl_register_types(void) 851 { 852 type_register_static(&iotkit_sysctl_info); 853 } 854 855 type_init(iotkit_sysctl_register_types); 856