1 /* 2 * ARM IoTKit system control element 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* 13 * This is a model of the "system control element" which is part of the 14 * Arm IoTKit and documented in 15 * https://developer.arm.com/documentation/ecm0601256/latest 16 * Specifically, it implements the "system control register" blocks. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/bitops.h" 21 #include "qemu/log.h" 22 #include "qemu/module.h" 23 #include "sysemu/runstate.h" 24 #include "trace.h" 25 #include "qapi/error.h" 26 #include "hw/sysbus.h" 27 #include "migration/vmstate.h" 28 #include "hw/registerfields.h" 29 #include "hw/misc/iotkit-sysctl.h" 30 #include "hw/qdev-properties.h" 31 #include "hw/arm/armsse-version.h" 32 #include "target/arm/arm-powerctl.h" 33 #include "target/arm/cpu.h" 34 35 REG32(SECDBGSTAT, 0x0) 36 REG32(SECDBGSET, 0x4) 37 REG32(SECDBGCLR, 0x8) 38 REG32(SCSECCTRL, 0xc) 39 REG32(FCLK_DIV, 0x10) 40 REG32(SYSCLK_DIV, 0x14) 41 REG32(CLOCK_FORCE, 0x18) 42 REG32(RESET_SYNDROME, 0x100) 43 REG32(RESET_MASK, 0x104) 44 REG32(SWRESET, 0x108) 45 FIELD(SWRESET, SWRESETREQ, 9, 1) 46 REG32(GRETREG, 0x10c) 47 REG32(INITSVTOR0, 0x110) 48 FIELD(INITSVTOR0, LOCK, 0, 1) 49 FIELD(INITSVTOR0, VTOR, 7, 25) 50 REG32(INITSVTOR1, 0x114) 51 REG32(CPUWAIT, 0x118) 52 REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */ 53 REG32(WICCTRL, 0x120) 54 REG32(EWCTRL, 0x124) 55 REG32(PWRCTRL, 0x1fc) 56 FIELD(PWRCTRL, PPU_ACCESS_UNLOCK, 0, 1) 57 FIELD(PWRCTRL, PPU_ACCESS_FILTER, 1, 1) 58 REG32(PDCM_PD_SYS_SENSE, 0x200) 59 REG32(PDCM_PD_SRAM0_SENSE, 0x20c) 60 REG32(PDCM_PD_SRAM1_SENSE, 0x210) 61 REG32(PDCM_PD_SRAM2_SENSE, 0x214) 62 REG32(PDCM_PD_SRAM3_SENSE, 0x218) 63 REG32(PID4, 0xfd0) 64 REG32(PID5, 0xfd4) 65 REG32(PID6, 0xfd8) 66 REG32(PID7, 0xfdc) 67 REG32(PID0, 0xfe0) 68 REG32(PID1, 0xfe4) 69 REG32(PID2, 0xfe8) 70 REG32(PID3, 0xfec) 71 REG32(CID0, 0xff0) 72 REG32(CID1, 0xff4) 73 REG32(CID2, 0xff8) 74 REG32(CID3, 0xffc) 75 76 /* PID/CID values */ 77 static const int sysctl_id[] = { 78 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ 79 0x54, 0xb8, 0x0b, 0x00, /* PID0..PID3 */ 80 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ 81 }; 82 83 /* 84 * Set the initial secure vector table offset address for the core. 85 * This will take effect when the CPU next resets. 86 */ 87 static void set_init_vtor(uint64_t cpuid, uint32_t vtor) 88 { 89 Object *cpuobj = OBJECT(arm_get_cpu_by_id(cpuid)); 90 91 if (cpuobj) { 92 if (object_property_find(cpuobj, "init-svtor")) { 93 object_property_set_uint(cpuobj, "init-svtor", vtor, &error_abort); 94 } 95 } 96 } 97 98 static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset, 99 unsigned size) 100 { 101 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque); 102 uint64_t r; 103 104 switch (offset) { 105 case A_SECDBGSTAT: 106 r = s->secure_debug; 107 break; 108 case A_SCSECCTRL: 109 switch (s->sse_version) { 110 case ARMSSE_IOTKIT: 111 goto bad_offset; 112 case ARMSSE_SSE200: 113 case ARMSSE_SSE300: 114 r = s->scsecctrl; 115 break; 116 default: 117 g_assert_not_reached(); 118 } 119 break; 120 case A_FCLK_DIV: 121 switch (s->sse_version) { 122 case ARMSSE_IOTKIT: 123 goto bad_offset; 124 case ARMSSE_SSE200: 125 case ARMSSE_SSE300: 126 r = s->fclk_div; 127 break; 128 default: 129 g_assert_not_reached(); 130 } 131 break; 132 case A_SYSCLK_DIV: 133 switch (s->sse_version) { 134 case ARMSSE_IOTKIT: 135 goto bad_offset; 136 case ARMSSE_SSE200: 137 case ARMSSE_SSE300: 138 r = s->sysclk_div; 139 break; 140 default: 141 g_assert_not_reached(); 142 } 143 break; 144 case A_CLOCK_FORCE: 145 switch (s->sse_version) { 146 case ARMSSE_IOTKIT: 147 goto bad_offset; 148 case ARMSSE_SSE200: 149 case ARMSSE_SSE300: 150 r = s->clock_force; 151 break; 152 default: 153 g_assert_not_reached(); 154 } 155 break; 156 case A_RESET_SYNDROME: 157 r = s->reset_syndrome; 158 break; 159 case A_RESET_MASK: 160 r = s->reset_mask; 161 break; 162 case A_GRETREG: 163 r = s->gretreg; 164 break; 165 case A_INITSVTOR0: 166 r = s->initsvtor0; 167 break; 168 case A_INITSVTOR1: 169 switch (s->sse_version) { 170 case ARMSSE_IOTKIT: 171 goto bad_offset; 172 case ARMSSE_SSE200: 173 r = s->initsvtor1; 174 break; 175 case ARMSSE_SSE300: 176 goto bad_offset; 177 default: 178 g_assert_not_reached(); 179 } 180 break; 181 case A_CPUWAIT: 182 switch (s->sse_version) { 183 case ARMSSE_IOTKIT: 184 case ARMSSE_SSE200: 185 r = s->cpuwait; 186 break; 187 case ARMSSE_SSE300: 188 /* In SSE300 this is reserved (for INITSVTOR2) */ 189 goto bad_offset; 190 default: 191 g_assert_not_reached(); 192 } 193 break; 194 case A_NMI_ENABLE: 195 switch (s->sse_version) { 196 case ARMSSE_IOTKIT: 197 /* In IoTKit this is named BUSWAIT but marked reserved, R/O, zero */ 198 r = 0; 199 break; 200 case ARMSSE_SSE200: 201 r = s->nmi_enable; 202 break; 203 case ARMSSE_SSE300: 204 /* In SSE300 this is reserved (for INITSVTOR3) */ 205 goto bad_offset; 206 default: 207 g_assert_not_reached(); 208 } 209 break; 210 case A_WICCTRL: 211 switch (s->sse_version) { 212 case ARMSSE_IOTKIT: 213 case ARMSSE_SSE200: 214 r = s->wicctrl; 215 break; 216 case ARMSSE_SSE300: 217 /* In SSE300 this offset is CPUWAIT */ 218 r = s->cpuwait; 219 break; 220 default: 221 g_assert_not_reached(); 222 } 223 break; 224 case A_EWCTRL: 225 switch (s->sse_version) { 226 case ARMSSE_IOTKIT: 227 goto bad_offset; 228 case ARMSSE_SSE200: 229 r = s->ewctrl; 230 break; 231 case ARMSSE_SSE300: 232 /* In SSE300 this offset is is NMI_ENABLE */ 233 r = s->nmi_enable; 234 break; 235 default: 236 g_assert_not_reached(); 237 } 238 break; 239 case A_PWRCTRL: 240 switch (s->sse_version) { 241 case ARMSSE_IOTKIT: 242 case ARMSSE_SSE200: 243 goto bad_offset; 244 case ARMSSE_SSE300: 245 r = s->pwrctrl; 246 break; 247 default: 248 g_assert_not_reached(); 249 } 250 break; 251 case A_PDCM_PD_SYS_SENSE: 252 switch (s->sse_version) { 253 case ARMSSE_IOTKIT: 254 goto bad_offset; 255 case ARMSSE_SSE200: 256 case ARMSSE_SSE300: 257 r = s->pdcm_pd_sys_sense; 258 break; 259 default: 260 g_assert_not_reached(); 261 } 262 break; 263 case A_PDCM_PD_SRAM0_SENSE: 264 switch (s->sse_version) { 265 case ARMSSE_IOTKIT: 266 goto bad_offset; 267 case ARMSSE_SSE200: 268 r = s->pdcm_pd_sram0_sense; 269 break; 270 default: 271 g_assert_not_reached(); 272 } 273 break; 274 case A_PDCM_PD_SRAM1_SENSE: 275 switch (s->sse_version) { 276 case ARMSSE_IOTKIT: 277 goto bad_offset; 278 case ARMSSE_SSE200: 279 r = s->pdcm_pd_sram1_sense; 280 break; 281 default: 282 g_assert_not_reached(); 283 } 284 break; 285 case A_PDCM_PD_SRAM2_SENSE: 286 switch (s->sse_version) { 287 case ARMSSE_IOTKIT: 288 goto bad_offset; 289 case ARMSSE_SSE200: 290 r = s->pdcm_pd_sram2_sense; 291 break; 292 default: 293 g_assert_not_reached(); 294 } 295 break; 296 case A_PDCM_PD_SRAM3_SENSE: 297 switch (s->sse_version) { 298 case ARMSSE_IOTKIT: 299 goto bad_offset; 300 case ARMSSE_SSE200: 301 r = s->pdcm_pd_sram3_sense; 302 break; 303 default: 304 g_assert_not_reached(); 305 } 306 break; 307 case A_PID4 ... A_CID3: 308 r = sysctl_id[(offset - A_PID4) / 4]; 309 break; 310 case A_SECDBGSET: 311 case A_SECDBGCLR: 312 case A_SWRESET: 313 qemu_log_mask(LOG_GUEST_ERROR, 314 "IoTKit SysCtl read: read of WO offset %x\n", 315 (int)offset); 316 r = 0; 317 break; 318 default: 319 bad_offset: 320 qemu_log_mask(LOG_GUEST_ERROR, 321 "IoTKit SysCtl read: bad offset %x\n", (int)offset); 322 r = 0; 323 break; 324 } 325 trace_iotkit_sysctl_read(offset, r, size); 326 return r; 327 } 328 329 static void cpuwait_write(IoTKitSysCtl *s, uint32_t value) 330 { 331 int num_cpus = (s->sse_version == ARMSSE_SSE300) ? 1 : 2; 332 int i; 333 334 for (i = 0; i < num_cpus; i++) { 335 uint32_t mask = 1 << i; 336 if ((s->cpuwait & mask) && !(value & mask)) { 337 /* Powering up CPU 0 */ 338 arm_set_cpu_on_and_reset(i); 339 } 340 } 341 s->cpuwait = value; 342 } 343 344 static void iotkit_sysctl_write(void *opaque, hwaddr offset, 345 uint64_t value, unsigned size) 346 { 347 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque); 348 349 trace_iotkit_sysctl_write(offset, value, size); 350 351 /* 352 * Most of the state here has to do with control of reset and 353 * similar kinds of power up -- for instance the guest can ask 354 * what the reason for the last reset was, or forbid reset for 355 * some causes (like the non-secure watchdog). Most of this is 356 * not relevant to QEMU, which doesn't really model anything other 357 * than a full power-on reset. 358 * We just model the registers as reads-as-written. 359 */ 360 361 switch (offset) { 362 case A_RESET_SYNDROME: 363 qemu_log_mask(LOG_UNIMP, 364 "IoTKit SysCtl RESET_SYNDROME unimplemented\n"); 365 s->reset_syndrome = value; 366 break; 367 case A_RESET_MASK: 368 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl RESET_MASK unimplemented\n"); 369 s->reset_mask = value; 370 break; 371 case A_GRETREG: 372 /* 373 * General retention register, which is only reset by a power-on 374 * reset. Technically this implementation is complete, since 375 * QEMU only supports power-on resets... 376 */ 377 s->gretreg = value; 378 break; 379 case A_INITSVTOR0: 380 switch (s->sse_version) { 381 case ARMSSE_SSE300: 382 /* SSE300 has a LOCK bit which prevents further writes when set */ 383 if (s->initsvtor0 & R_INITSVTOR0_LOCK_MASK) { 384 qemu_log_mask(LOG_GUEST_ERROR, 385 "IoTKit INITSVTOR0 write when register locked\n"); 386 break; 387 } 388 s->initsvtor0 = value; 389 set_init_vtor(0, s->initsvtor0 & R_INITSVTOR0_VTOR_MASK); 390 break; 391 case ARMSSE_IOTKIT: 392 case ARMSSE_SSE200: 393 s->initsvtor0 = value; 394 set_init_vtor(0, s->initsvtor0); 395 break; 396 default: 397 g_assert_not_reached(); 398 } 399 break; 400 case A_CPUWAIT: 401 switch (s->sse_version) { 402 case ARMSSE_IOTKIT: 403 case ARMSSE_SSE200: 404 cpuwait_write(s, value); 405 break; 406 case ARMSSE_SSE300: 407 /* In SSE300 this is reserved (for INITSVTOR2) */ 408 goto bad_offset; 409 default: 410 g_assert_not_reached(); 411 } 412 break; 413 case A_WICCTRL: 414 switch (s->sse_version) { 415 case ARMSSE_IOTKIT: 416 case ARMSSE_SSE200: 417 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl WICCTRL unimplemented\n"); 418 s->wicctrl = value; 419 break; 420 case ARMSSE_SSE300: 421 /* In SSE300 this offset is CPUWAIT */ 422 cpuwait_write(s, value); 423 break; 424 default: 425 g_assert_not_reached(); 426 } 427 break; 428 case A_SECDBGSET: 429 /* write-1-to-set */ 430 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SECDBGSET unimplemented\n"); 431 s->secure_debug |= value; 432 break; 433 case A_SECDBGCLR: 434 /* write-1-to-clear */ 435 s->secure_debug &= ~value; 436 break; 437 case A_SWRESET: 438 /* One w/o bit to request a reset; all other bits reserved */ 439 if (value & R_SWRESET_SWRESETREQ_MASK) { 440 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 441 } 442 break; 443 case A_SCSECCTRL: 444 switch (s->sse_version) { 445 case ARMSSE_IOTKIT: 446 goto bad_offset; 447 case ARMSSE_SSE200: 448 case ARMSSE_SSE300: 449 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n"); 450 s->scsecctrl = value; 451 break; 452 default: 453 g_assert_not_reached(); 454 } 455 break; 456 case A_FCLK_DIV: 457 switch (s->sse_version) { 458 case ARMSSE_IOTKIT: 459 goto bad_offset; 460 case ARMSSE_SSE200: 461 case ARMSSE_SSE300: 462 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n"); 463 s->fclk_div = value; 464 break; 465 default: 466 g_assert_not_reached(); 467 } 468 break; 469 case A_SYSCLK_DIV: 470 switch (s->sse_version) { 471 case ARMSSE_IOTKIT: 472 goto bad_offset; 473 case ARMSSE_SSE200: 474 case ARMSSE_SSE300: 475 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n"); 476 s->sysclk_div = value; 477 break; 478 default: 479 g_assert_not_reached(); 480 } 481 break; 482 case A_CLOCK_FORCE: 483 switch (s->sse_version) { 484 case ARMSSE_IOTKIT: 485 goto bad_offset; 486 case ARMSSE_SSE200: 487 case ARMSSE_SSE300: 488 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\n"); 489 s->clock_force = value; 490 break; 491 default: 492 g_assert_not_reached(); 493 } 494 break; 495 case A_INITSVTOR1: 496 switch (s->sse_version) { 497 case ARMSSE_IOTKIT: 498 goto bad_offset; 499 case ARMSSE_SSE200: 500 s->initsvtor1 = value; 501 set_init_vtor(1, s->initsvtor1); 502 break; 503 case ARMSSE_SSE300: 504 goto bad_offset; 505 default: 506 g_assert_not_reached(); 507 } 508 break; 509 case A_EWCTRL: 510 switch (s->sse_version) { 511 case ARMSSE_IOTKIT: 512 goto bad_offset; 513 case ARMSSE_SSE200: 514 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n"); 515 s->ewctrl = value; 516 break; 517 case ARMSSE_SSE300: 518 /* In SSE300 this offset is is NMI_ENABLE */ 519 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n"); 520 s->nmi_enable = value; 521 break; 522 default: 523 g_assert_not_reached(); 524 } 525 break; 526 case A_PWRCTRL: 527 switch (s->sse_version) { 528 case ARMSSE_IOTKIT: 529 case ARMSSE_SSE200: 530 goto bad_offset; 531 case ARMSSE_SSE300: 532 if (!(s->pwrctrl & R_PWRCTRL_PPU_ACCESS_UNLOCK_MASK)) { 533 qemu_log_mask(LOG_GUEST_ERROR, 534 "IoTKit PWRCTRL write when register locked\n"); 535 break; 536 } 537 s->pwrctrl = value; 538 break; 539 default: 540 g_assert_not_reached(); 541 } 542 break; 543 case A_PDCM_PD_SYS_SENSE: 544 switch (s->sse_version) { 545 case ARMSSE_IOTKIT: 546 goto bad_offset; 547 case ARMSSE_SSE200: 548 case ARMSSE_SSE300: 549 qemu_log_mask(LOG_UNIMP, 550 "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n"); 551 s->pdcm_pd_sys_sense = value; 552 break; 553 default: 554 g_assert_not_reached(); 555 } 556 break; 557 case A_PDCM_PD_SRAM0_SENSE: 558 switch (s->sse_version) { 559 case ARMSSE_IOTKIT: 560 goto bad_offset; 561 case ARMSSE_SSE200: 562 qemu_log_mask(LOG_UNIMP, 563 "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n"); 564 s->pdcm_pd_sram0_sense = value; 565 break; 566 default: 567 g_assert_not_reached(); 568 } 569 break; 570 case A_PDCM_PD_SRAM1_SENSE: 571 switch (s->sse_version) { 572 case ARMSSE_IOTKIT: 573 goto bad_offset; 574 case ARMSSE_SSE200: 575 qemu_log_mask(LOG_UNIMP, 576 "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n"); 577 s->pdcm_pd_sram1_sense = value; 578 break; 579 default: 580 g_assert_not_reached(); 581 } 582 break; 583 case A_PDCM_PD_SRAM2_SENSE: 584 switch (s->sse_version) { 585 case ARMSSE_IOTKIT: 586 goto bad_offset; 587 case ARMSSE_SSE200: 588 qemu_log_mask(LOG_UNIMP, 589 "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n"); 590 s->pdcm_pd_sram2_sense = value; 591 break; 592 default: 593 g_assert_not_reached(); 594 } 595 break; 596 case A_PDCM_PD_SRAM3_SENSE: 597 switch (s->sse_version) { 598 case ARMSSE_IOTKIT: 599 goto bad_offset; 600 case ARMSSE_SSE200: 601 qemu_log_mask(LOG_UNIMP, 602 "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n"); 603 s->pdcm_pd_sram3_sense = value; 604 break; 605 default: 606 g_assert_not_reached(); 607 } 608 break; 609 case A_NMI_ENABLE: 610 /* In IoTKit this is BUSWAIT: reserved, R/O, zero */ 611 switch (s->sse_version) { 612 case ARMSSE_IOTKIT: 613 goto ro_offset; 614 case ARMSSE_SSE200: 615 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n"); 616 s->nmi_enable = value; 617 break; 618 case ARMSSE_SSE300: 619 /* In SSE300 this is reserved (for INITSVTOR3) */ 620 goto bad_offset; 621 default: 622 g_assert_not_reached(); 623 } 624 break; 625 case A_SECDBGSTAT: 626 case A_PID4 ... A_CID3: 627 ro_offset: 628 qemu_log_mask(LOG_GUEST_ERROR, 629 "IoTKit SysCtl write: write of RO offset %x\n", 630 (int)offset); 631 break; 632 default: 633 bad_offset: 634 qemu_log_mask(LOG_GUEST_ERROR, 635 "IoTKit SysCtl write: bad offset %x\n", (int)offset); 636 break; 637 } 638 } 639 640 static const MemoryRegionOps iotkit_sysctl_ops = { 641 .read = iotkit_sysctl_read, 642 .write = iotkit_sysctl_write, 643 .endianness = DEVICE_LITTLE_ENDIAN, 644 /* byte/halfword accesses are just zero-padded on reads and writes */ 645 .impl.min_access_size = 4, 646 .impl.max_access_size = 4, 647 .valid.min_access_size = 1, 648 .valid.max_access_size = 4, 649 }; 650 651 static void iotkit_sysctl_reset(DeviceState *dev) 652 { 653 IoTKitSysCtl *s = IOTKIT_SYSCTL(dev); 654 655 trace_iotkit_sysctl_reset(); 656 s->secure_debug = 0; 657 s->reset_syndrome = 1; 658 s->reset_mask = 0; 659 s->gretreg = 0; 660 s->initsvtor0 = s->initsvtor0_rst; 661 s->initsvtor1 = s->initsvtor1_rst; 662 s->cpuwait = s->cpuwait_rst; 663 s->wicctrl = 0; 664 s->scsecctrl = 0; 665 s->fclk_div = 0; 666 s->sysclk_div = 0; 667 s->clock_force = 0; 668 s->nmi_enable = 0; 669 s->ewctrl = 0; 670 s->pwrctrl = 0x3; 671 s->pdcm_pd_sys_sense = 0x7f; 672 s->pdcm_pd_sram0_sense = 0; 673 s->pdcm_pd_sram1_sense = 0; 674 s->pdcm_pd_sram2_sense = 0; 675 s->pdcm_pd_sram3_sense = 0; 676 } 677 678 static void iotkit_sysctl_init(Object *obj) 679 { 680 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 681 IoTKitSysCtl *s = IOTKIT_SYSCTL(obj); 682 683 memory_region_init_io(&s->iomem, obj, &iotkit_sysctl_ops, 684 s, "iotkit-sysctl", 0x1000); 685 sysbus_init_mmio(sbd, &s->iomem); 686 } 687 688 static void iotkit_sysctl_realize(DeviceState *dev, Error **errp) 689 { 690 IoTKitSysCtl *s = IOTKIT_SYSCTL(dev); 691 692 if (!armsse_version_valid(s->sse_version)) { 693 error_setg(errp, "invalid sse-version value %d", s->sse_version); 694 return; 695 } 696 } 697 698 static bool sse300_needed(void *opaque) 699 { 700 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque); 701 702 return s->sse_version == ARMSSE_SSE300; 703 } 704 705 static const VMStateDescription iotkit_sysctl_sse300_vmstate = { 706 .name = "iotkit-sysctl/sse-300", 707 .version_id = 1, 708 .minimum_version_id = 1, 709 .needed = sse300_needed, 710 .fields = (VMStateField[]) { 711 VMSTATE_UINT32(pwrctrl, IoTKitSysCtl), 712 VMSTATE_END_OF_LIST() 713 } 714 }; 715 716 static bool sse200_needed(void *opaque) 717 { 718 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque); 719 720 return s->sse_version != ARMSSE_IOTKIT; 721 } 722 723 static const VMStateDescription iotkit_sysctl_sse200_vmstate = { 724 .name = "iotkit-sysctl/sse-200", 725 .version_id = 1, 726 .minimum_version_id = 1, 727 .needed = sse200_needed, 728 .fields = (VMStateField[]) { 729 VMSTATE_UINT32(scsecctrl, IoTKitSysCtl), 730 VMSTATE_UINT32(fclk_div, IoTKitSysCtl), 731 VMSTATE_UINT32(sysclk_div, IoTKitSysCtl), 732 VMSTATE_UINT32(clock_force, IoTKitSysCtl), 733 VMSTATE_UINT32(initsvtor1, IoTKitSysCtl), 734 VMSTATE_UINT32(nmi_enable, IoTKitSysCtl), 735 VMSTATE_UINT32(pdcm_pd_sys_sense, IoTKitSysCtl), 736 VMSTATE_UINT32(pdcm_pd_sram0_sense, IoTKitSysCtl), 737 VMSTATE_UINT32(pdcm_pd_sram1_sense, IoTKitSysCtl), 738 VMSTATE_UINT32(pdcm_pd_sram2_sense, IoTKitSysCtl), 739 VMSTATE_UINT32(pdcm_pd_sram3_sense, IoTKitSysCtl), 740 VMSTATE_END_OF_LIST() 741 } 742 }; 743 744 static const VMStateDescription iotkit_sysctl_vmstate = { 745 .name = "iotkit-sysctl", 746 .version_id = 1, 747 .minimum_version_id = 1, 748 .fields = (VMStateField[]) { 749 VMSTATE_UINT32(secure_debug, IoTKitSysCtl), 750 VMSTATE_UINT32(reset_syndrome, IoTKitSysCtl), 751 VMSTATE_UINT32(reset_mask, IoTKitSysCtl), 752 VMSTATE_UINT32(gretreg, IoTKitSysCtl), 753 VMSTATE_UINT32(initsvtor0, IoTKitSysCtl), 754 VMSTATE_UINT32(cpuwait, IoTKitSysCtl), 755 VMSTATE_UINT32(wicctrl, IoTKitSysCtl), 756 VMSTATE_END_OF_LIST() 757 }, 758 .subsections = (const VMStateDescription*[]) { 759 &iotkit_sysctl_sse200_vmstate, 760 &iotkit_sysctl_sse300_vmstate, 761 NULL 762 } 763 }; 764 765 static Property iotkit_sysctl_props[] = { 766 DEFINE_PROP_UINT32("sse-version", IoTKitSysCtl, sse_version, 0), 767 DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl, cpuwait_rst, 0), 768 DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl, initsvtor0_rst, 769 0x10000000), 770 DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl, initsvtor1_rst, 771 0x10000000), 772 DEFINE_PROP_END_OF_LIST() 773 }; 774 775 static void iotkit_sysctl_class_init(ObjectClass *klass, void *data) 776 { 777 DeviceClass *dc = DEVICE_CLASS(klass); 778 779 dc->vmsd = &iotkit_sysctl_vmstate; 780 dc->reset = iotkit_sysctl_reset; 781 device_class_set_props(dc, iotkit_sysctl_props); 782 dc->realize = iotkit_sysctl_realize; 783 } 784 785 static const TypeInfo iotkit_sysctl_info = { 786 .name = TYPE_IOTKIT_SYSCTL, 787 .parent = TYPE_SYS_BUS_DEVICE, 788 .instance_size = sizeof(IoTKitSysCtl), 789 .instance_init = iotkit_sysctl_init, 790 .class_init = iotkit_sysctl_class_init, 791 }; 792 793 static void iotkit_sysctl_register_types(void) 794 { 795 type_register_static(&iotkit_sysctl_info); 796 } 797 798 type_init(iotkit_sysctl_register_types); 799