1 /* 2 * ARM IoTKit system control element 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* 13 * This is a model of the "system control element" which is part of the 14 * Arm IoTKit and documented in 15 * https://developer.arm.com/documentation/ecm0601256/latest 16 * Specifically, it implements the "system control register" blocks. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/bitops.h" 21 #include "qemu/log.h" 22 #include "qemu/module.h" 23 #include "sysemu/runstate.h" 24 #include "trace.h" 25 #include "qapi/error.h" 26 #include "hw/sysbus.h" 27 #include "migration/vmstate.h" 28 #include "hw/registerfields.h" 29 #include "hw/misc/iotkit-sysctl.h" 30 #include "hw/qdev-properties.h" 31 #include "hw/arm/armsse-version.h" 32 #include "target/arm/arm-powerctl.h" 33 #include "target/arm/cpu.h" 34 35 REG32(SECDBGSTAT, 0x0) 36 REG32(SECDBGSET, 0x4) 37 REG32(SECDBGCLR, 0x8) 38 REG32(SCSECCTRL, 0xc) 39 REG32(FCLK_DIV, 0x10) 40 REG32(SYSCLK_DIV, 0x14) 41 REG32(CLOCK_FORCE, 0x18) 42 REG32(RESET_SYNDROME, 0x100) 43 REG32(RESET_MASK, 0x104) 44 REG32(SWRESET, 0x108) 45 FIELD(SWRESET, SWRESETREQ, 9, 1) 46 REG32(GRETREG, 0x10c) 47 REG32(INITSVTOR0, 0x110) 48 FIELD(INITSVTOR0, LOCK, 0, 1) 49 FIELD(INITSVTOR0, VTOR, 7, 25) 50 REG32(INITSVTOR1, 0x114) 51 REG32(CPUWAIT, 0x118) 52 REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */ 53 REG32(WICCTRL, 0x120) 54 REG32(EWCTRL, 0x124) 55 REG32(PDCM_PD_SYS_SENSE, 0x200) 56 REG32(PDCM_PD_SRAM0_SENSE, 0x20c) 57 REG32(PDCM_PD_SRAM1_SENSE, 0x210) 58 REG32(PDCM_PD_SRAM2_SENSE, 0x214) 59 REG32(PDCM_PD_SRAM3_SENSE, 0x218) 60 REG32(PID4, 0xfd0) 61 REG32(PID5, 0xfd4) 62 REG32(PID6, 0xfd8) 63 REG32(PID7, 0xfdc) 64 REG32(PID0, 0xfe0) 65 REG32(PID1, 0xfe4) 66 REG32(PID2, 0xfe8) 67 REG32(PID3, 0xfec) 68 REG32(CID0, 0xff0) 69 REG32(CID1, 0xff4) 70 REG32(CID2, 0xff8) 71 REG32(CID3, 0xffc) 72 73 /* PID/CID values */ 74 static const int sysctl_id[] = { 75 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ 76 0x54, 0xb8, 0x0b, 0x00, /* PID0..PID3 */ 77 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ 78 }; 79 80 /* 81 * Set the initial secure vector table offset address for the core. 82 * This will take effect when the CPU next resets. 83 */ 84 static void set_init_vtor(uint64_t cpuid, uint32_t vtor) 85 { 86 Object *cpuobj = OBJECT(arm_get_cpu_by_id(cpuid)); 87 88 if (cpuobj) { 89 if (object_property_find(cpuobj, "init-svtor")) { 90 object_property_set_uint(cpuobj, "init-svtor", vtor, &error_abort); 91 } 92 } 93 } 94 95 static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset, 96 unsigned size) 97 { 98 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque); 99 uint64_t r; 100 101 switch (offset) { 102 case A_SECDBGSTAT: 103 r = s->secure_debug; 104 break; 105 case A_SCSECCTRL: 106 switch (s->sse_version) { 107 case ARMSSE_IOTKIT: 108 goto bad_offset; 109 case ARMSSE_SSE200: 110 case ARMSSE_SSE300: 111 r = s->scsecctrl; 112 break; 113 default: 114 g_assert_not_reached(); 115 } 116 break; 117 case A_FCLK_DIV: 118 switch (s->sse_version) { 119 case ARMSSE_IOTKIT: 120 goto bad_offset; 121 case ARMSSE_SSE200: 122 case ARMSSE_SSE300: 123 r = s->fclk_div; 124 break; 125 default: 126 g_assert_not_reached(); 127 } 128 break; 129 case A_SYSCLK_DIV: 130 switch (s->sse_version) { 131 case ARMSSE_IOTKIT: 132 goto bad_offset; 133 case ARMSSE_SSE200: 134 case ARMSSE_SSE300: 135 r = s->sysclk_div; 136 break; 137 default: 138 g_assert_not_reached(); 139 } 140 break; 141 case A_CLOCK_FORCE: 142 switch (s->sse_version) { 143 case ARMSSE_IOTKIT: 144 goto bad_offset; 145 case ARMSSE_SSE200: 146 case ARMSSE_SSE300: 147 r = s->clock_force; 148 break; 149 default: 150 g_assert_not_reached(); 151 } 152 break; 153 case A_RESET_SYNDROME: 154 r = s->reset_syndrome; 155 break; 156 case A_RESET_MASK: 157 r = s->reset_mask; 158 break; 159 case A_GRETREG: 160 r = s->gretreg; 161 break; 162 case A_INITSVTOR0: 163 r = s->initsvtor0; 164 break; 165 case A_INITSVTOR1: 166 switch (s->sse_version) { 167 case ARMSSE_IOTKIT: 168 goto bad_offset; 169 case ARMSSE_SSE200: 170 r = s->initsvtor1; 171 break; 172 case ARMSSE_SSE300: 173 goto bad_offset; 174 default: 175 g_assert_not_reached(); 176 } 177 break; 178 case A_CPUWAIT: 179 switch (s->sse_version) { 180 case ARMSSE_IOTKIT: 181 case ARMSSE_SSE200: 182 r = s->cpuwait; 183 break; 184 case ARMSSE_SSE300: 185 /* In SSE300 this is reserved (for INITSVTOR2) */ 186 goto bad_offset; 187 default: 188 g_assert_not_reached(); 189 } 190 break; 191 case A_NMI_ENABLE: 192 switch (s->sse_version) { 193 case ARMSSE_IOTKIT: 194 /* In IoTKit this is named BUSWAIT but marked reserved, R/O, zero */ 195 r = 0; 196 break; 197 case ARMSSE_SSE200: 198 r = s->nmi_enable; 199 break; 200 case ARMSSE_SSE300: 201 /* In SSE300 this is reserved (for INITSVTOR3) */ 202 goto bad_offset; 203 default: 204 g_assert_not_reached(); 205 } 206 break; 207 case A_WICCTRL: 208 switch (s->sse_version) { 209 case ARMSSE_IOTKIT: 210 case ARMSSE_SSE200: 211 r = s->wicctrl; 212 break; 213 case ARMSSE_SSE300: 214 /* In SSE300 this offset is CPUWAIT */ 215 r = s->cpuwait; 216 break; 217 default: 218 g_assert_not_reached(); 219 } 220 break; 221 case A_EWCTRL: 222 switch (s->sse_version) { 223 case ARMSSE_IOTKIT: 224 goto bad_offset; 225 case ARMSSE_SSE200: 226 r = s->ewctrl; 227 break; 228 case ARMSSE_SSE300: 229 /* In SSE300 this offset is is NMI_ENABLE */ 230 r = s->nmi_enable; 231 break; 232 default: 233 g_assert_not_reached(); 234 } 235 break; 236 case A_PDCM_PD_SYS_SENSE: 237 switch (s->sse_version) { 238 case ARMSSE_IOTKIT: 239 goto bad_offset; 240 case ARMSSE_SSE200: 241 case ARMSSE_SSE300: 242 r = s->pdcm_pd_sys_sense; 243 break; 244 default: 245 g_assert_not_reached(); 246 } 247 break; 248 case A_PDCM_PD_SRAM0_SENSE: 249 switch (s->sse_version) { 250 case ARMSSE_IOTKIT: 251 goto bad_offset; 252 case ARMSSE_SSE200: 253 r = s->pdcm_pd_sram0_sense; 254 break; 255 default: 256 g_assert_not_reached(); 257 } 258 break; 259 case A_PDCM_PD_SRAM1_SENSE: 260 switch (s->sse_version) { 261 case ARMSSE_IOTKIT: 262 goto bad_offset; 263 case ARMSSE_SSE200: 264 r = s->pdcm_pd_sram1_sense; 265 break; 266 default: 267 g_assert_not_reached(); 268 } 269 break; 270 case A_PDCM_PD_SRAM2_SENSE: 271 switch (s->sse_version) { 272 case ARMSSE_IOTKIT: 273 goto bad_offset; 274 case ARMSSE_SSE200: 275 r = s->pdcm_pd_sram2_sense; 276 break; 277 default: 278 g_assert_not_reached(); 279 } 280 break; 281 case A_PDCM_PD_SRAM3_SENSE: 282 switch (s->sse_version) { 283 case ARMSSE_IOTKIT: 284 goto bad_offset; 285 case ARMSSE_SSE200: 286 r = s->pdcm_pd_sram3_sense; 287 break; 288 default: 289 g_assert_not_reached(); 290 } 291 break; 292 case A_PID4 ... A_CID3: 293 r = sysctl_id[(offset - A_PID4) / 4]; 294 break; 295 case A_SECDBGSET: 296 case A_SECDBGCLR: 297 case A_SWRESET: 298 qemu_log_mask(LOG_GUEST_ERROR, 299 "IoTKit SysCtl read: read of WO offset %x\n", 300 (int)offset); 301 r = 0; 302 break; 303 default: 304 bad_offset: 305 qemu_log_mask(LOG_GUEST_ERROR, 306 "IoTKit SysCtl read: bad offset %x\n", (int)offset); 307 r = 0; 308 break; 309 } 310 trace_iotkit_sysctl_read(offset, r, size); 311 return r; 312 } 313 314 static void cpuwait_write(IoTKitSysCtl *s, uint32_t value) 315 { 316 int num_cpus = (s->sse_version == ARMSSE_SSE300) ? 1 : 2; 317 int i; 318 319 for (i = 0; i < num_cpus; i++) { 320 uint32_t mask = 1 << i; 321 if ((s->cpuwait & mask) && !(value & mask)) { 322 /* Powering up CPU 0 */ 323 arm_set_cpu_on_and_reset(i); 324 } 325 } 326 s->cpuwait = value; 327 } 328 329 static void iotkit_sysctl_write(void *opaque, hwaddr offset, 330 uint64_t value, unsigned size) 331 { 332 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque); 333 334 trace_iotkit_sysctl_write(offset, value, size); 335 336 /* 337 * Most of the state here has to do with control of reset and 338 * similar kinds of power up -- for instance the guest can ask 339 * what the reason for the last reset was, or forbid reset for 340 * some causes (like the non-secure watchdog). Most of this is 341 * not relevant to QEMU, which doesn't really model anything other 342 * than a full power-on reset. 343 * We just model the registers as reads-as-written. 344 */ 345 346 switch (offset) { 347 case A_RESET_SYNDROME: 348 qemu_log_mask(LOG_UNIMP, 349 "IoTKit SysCtl RESET_SYNDROME unimplemented\n"); 350 s->reset_syndrome = value; 351 break; 352 case A_RESET_MASK: 353 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl RESET_MASK unimplemented\n"); 354 s->reset_mask = value; 355 break; 356 case A_GRETREG: 357 /* 358 * General retention register, which is only reset by a power-on 359 * reset. Technically this implementation is complete, since 360 * QEMU only supports power-on resets... 361 */ 362 s->gretreg = value; 363 break; 364 case A_INITSVTOR0: 365 switch (s->sse_version) { 366 case ARMSSE_SSE300: 367 /* SSE300 has a LOCK bit which prevents further writes when set */ 368 if (s->initsvtor0 & R_INITSVTOR0_LOCK_MASK) { 369 qemu_log_mask(LOG_GUEST_ERROR, 370 "IoTKit INITSVTOR0 write when register locked\n"); 371 break; 372 } 373 s->initsvtor0 = value; 374 set_init_vtor(0, s->initsvtor0 & R_INITSVTOR0_VTOR_MASK); 375 break; 376 case ARMSSE_IOTKIT: 377 case ARMSSE_SSE200: 378 s->initsvtor0 = value; 379 set_init_vtor(0, s->initsvtor0); 380 break; 381 default: 382 g_assert_not_reached(); 383 } 384 break; 385 case A_CPUWAIT: 386 switch (s->sse_version) { 387 case ARMSSE_IOTKIT: 388 case ARMSSE_SSE200: 389 cpuwait_write(s, value); 390 break; 391 case ARMSSE_SSE300: 392 /* In SSE300 this is reserved (for INITSVTOR2) */ 393 goto bad_offset; 394 default: 395 g_assert_not_reached(); 396 } 397 break; 398 case A_WICCTRL: 399 switch (s->sse_version) { 400 case ARMSSE_IOTKIT: 401 case ARMSSE_SSE200: 402 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl WICCTRL unimplemented\n"); 403 s->wicctrl = value; 404 break; 405 case ARMSSE_SSE300: 406 /* In SSE300 this offset is CPUWAIT */ 407 cpuwait_write(s, value); 408 break; 409 default: 410 g_assert_not_reached(); 411 } 412 break; 413 case A_SECDBGSET: 414 /* write-1-to-set */ 415 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SECDBGSET unimplemented\n"); 416 s->secure_debug |= value; 417 break; 418 case A_SECDBGCLR: 419 /* write-1-to-clear */ 420 s->secure_debug &= ~value; 421 break; 422 case A_SWRESET: 423 /* One w/o bit to request a reset; all other bits reserved */ 424 if (value & R_SWRESET_SWRESETREQ_MASK) { 425 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 426 } 427 break; 428 case A_SCSECCTRL: 429 switch (s->sse_version) { 430 case ARMSSE_IOTKIT: 431 goto bad_offset; 432 case ARMSSE_SSE200: 433 case ARMSSE_SSE300: 434 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n"); 435 s->scsecctrl = value; 436 break; 437 default: 438 g_assert_not_reached(); 439 } 440 break; 441 case A_FCLK_DIV: 442 switch (s->sse_version) { 443 case ARMSSE_IOTKIT: 444 goto bad_offset; 445 case ARMSSE_SSE200: 446 case ARMSSE_SSE300: 447 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n"); 448 s->fclk_div = value; 449 break; 450 default: 451 g_assert_not_reached(); 452 } 453 break; 454 case A_SYSCLK_DIV: 455 switch (s->sse_version) { 456 case ARMSSE_IOTKIT: 457 goto bad_offset; 458 case ARMSSE_SSE200: 459 case ARMSSE_SSE300: 460 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n"); 461 s->sysclk_div = value; 462 break; 463 default: 464 g_assert_not_reached(); 465 } 466 break; 467 case A_CLOCK_FORCE: 468 switch (s->sse_version) { 469 case ARMSSE_IOTKIT: 470 goto bad_offset; 471 case ARMSSE_SSE200: 472 case ARMSSE_SSE300: 473 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\n"); 474 s->clock_force = value; 475 break; 476 default: 477 g_assert_not_reached(); 478 } 479 break; 480 case A_INITSVTOR1: 481 switch (s->sse_version) { 482 case ARMSSE_IOTKIT: 483 goto bad_offset; 484 case ARMSSE_SSE200: 485 s->initsvtor1 = value; 486 set_init_vtor(1, s->initsvtor1); 487 break; 488 case ARMSSE_SSE300: 489 goto bad_offset; 490 default: 491 g_assert_not_reached(); 492 } 493 break; 494 case A_EWCTRL: 495 switch (s->sse_version) { 496 case ARMSSE_IOTKIT: 497 goto bad_offset; 498 case ARMSSE_SSE200: 499 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n"); 500 s->ewctrl = value; 501 break; 502 case ARMSSE_SSE300: 503 /* In SSE300 this offset is is NMI_ENABLE */ 504 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n"); 505 s->nmi_enable = value; 506 break; 507 default: 508 g_assert_not_reached(); 509 } 510 break; 511 case A_PDCM_PD_SYS_SENSE: 512 switch (s->sse_version) { 513 case ARMSSE_IOTKIT: 514 goto bad_offset; 515 case ARMSSE_SSE200: 516 case ARMSSE_SSE300: 517 qemu_log_mask(LOG_UNIMP, 518 "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n"); 519 s->pdcm_pd_sys_sense = value; 520 break; 521 default: 522 g_assert_not_reached(); 523 } 524 break; 525 case A_PDCM_PD_SRAM0_SENSE: 526 switch (s->sse_version) { 527 case ARMSSE_IOTKIT: 528 goto bad_offset; 529 case ARMSSE_SSE200: 530 qemu_log_mask(LOG_UNIMP, 531 "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n"); 532 s->pdcm_pd_sram0_sense = value; 533 break; 534 default: 535 g_assert_not_reached(); 536 } 537 break; 538 case A_PDCM_PD_SRAM1_SENSE: 539 switch (s->sse_version) { 540 case ARMSSE_IOTKIT: 541 goto bad_offset; 542 case ARMSSE_SSE200: 543 qemu_log_mask(LOG_UNIMP, 544 "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n"); 545 s->pdcm_pd_sram1_sense = value; 546 break; 547 default: 548 g_assert_not_reached(); 549 } 550 break; 551 case A_PDCM_PD_SRAM2_SENSE: 552 switch (s->sse_version) { 553 case ARMSSE_IOTKIT: 554 goto bad_offset; 555 case ARMSSE_SSE200: 556 qemu_log_mask(LOG_UNIMP, 557 "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n"); 558 s->pdcm_pd_sram2_sense = value; 559 break; 560 default: 561 g_assert_not_reached(); 562 } 563 break; 564 case A_PDCM_PD_SRAM3_SENSE: 565 switch (s->sse_version) { 566 case ARMSSE_IOTKIT: 567 goto bad_offset; 568 case ARMSSE_SSE200: 569 qemu_log_mask(LOG_UNIMP, 570 "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n"); 571 s->pdcm_pd_sram3_sense = value; 572 break; 573 default: 574 g_assert_not_reached(); 575 } 576 break; 577 case A_NMI_ENABLE: 578 /* In IoTKit this is BUSWAIT: reserved, R/O, zero */ 579 switch (s->sse_version) { 580 case ARMSSE_IOTKIT: 581 goto ro_offset; 582 case ARMSSE_SSE200: 583 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n"); 584 s->nmi_enable = value; 585 break; 586 case ARMSSE_SSE300: 587 /* In SSE300 this is reserved (for INITSVTOR3) */ 588 goto bad_offset; 589 default: 590 g_assert_not_reached(); 591 } 592 break; 593 case A_SECDBGSTAT: 594 case A_PID4 ... A_CID3: 595 ro_offset: 596 qemu_log_mask(LOG_GUEST_ERROR, 597 "IoTKit SysCtl write: write of RO offset %x\n", 598 (int)offset); 599 break; 600 default: 601 bad_offset: 602 qemu_log_mask(LOG_GUEST_ERROR, 603 "IoTKit SysCtl write: bad offset %x\n", (int)offset); 604 break; 605 } 606 } 607 608 static const MemoryRegionOps iotkit_sysctl_ops = { 609 .read = iotkit_sysctl_read, 610 .write = iotkit_sysctl_write, 611 .endianness = DEVICE_LITTLE_ENDIAN, 612 /* byte/halfword accesses are just zero-padded on reads and writes */ 613 .impl.min_access_size = 4, 614 .impl.max_access_size = 4, 615 .valid.min_access_size = 1, 616 .valid.max_access_size = 4, 617 }; 618 619 static void iotkit_sysctl_reset(DeviceState *dev) 620 { 621 IoTKitSysCtl *s = IOTKIT_SYSCTL(dev); 622 623 trace_iotkit_sysctl_reset(); 624 s->secure_debug = 0; 625 s->reset_syndrome = 1; 626 s->reset_mask = 0; 627 s->gretreg = 0; 628 s->initsvtor0 = s->initsvtor0_rst; 629 s->initsvtor1 = s->initsvtor1_rst; 630 s->cpuwait = s->cpuwait_rst; 631 s->wicctrl = 0; 632 s->scsecctrl = 0; 633 s->fclk_div = 0; 634 s->sysclk_div = 0; 635 s->clock_force = 0; 636 s->nmi_enable = 0; 637 s->ewctrl = 0; 638 s->pdcm_pd_sys_sense = 0x7f; 639 s->pdcm_pd_sram0_sense = 0; 640 s->pdcm_pd_sram1_sense = 0; 641 s->pdcm_pd_sram2_sense = 0; 642 s->pdcm_pd_sram3_sense = 0; 643 } 644 645 static void iotkit_sysctl_init(Object *obj) 646 { 647 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 648 IoTKitSysCtl *s = IOTKIT_SYSCTL(obj); 649 650 memory_region_init_io(&s->iomem, obj, &iotkit_sysctl_ops, 651 s, "iotkit-sysctl", 0x1000); 652 sysbus_init_mmio(sbd, &s->iomem); 653 } 654 655 static void iotkit_sysctl_realize(DeviceState *dev, Error **errp) 656 { 657 IoTKitSysCtl *s = IOTKIT_SYSCTL(dev); 658 659 if (!armsse_version_valid(s->sse_version)) { 660 error_setg(errp, "invalid sse-version value %d", s->sse_version); 661 return; 662 } 663 } 664 665 static bool sse200_needed(void *opaque) 666 { 667 IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque); 668 669 return s->sse_version != ARMSSE_IOTKIT; 670 } 671 672 static const VMStateDescription iotkit_sysctl_sse200_vmstate = { 673 .name = "iotkit-sysctl/sse-200", 674 .version_id = 1, 675 .minimum_version_id = 1, 676 .needed = sse200_needed, 677 .fields = (VMStateField[]) { 678 VMSTATE_UINT32(scsecctrl, IoTKitSysCtl), 679 VMSTATE_UINT32(fclk_div, IoTKitSysCtl), 680 VMSTATE_UINT32(sysclk_div, IoTKitSysCtl), 681 VMSTATE_UINT32(clock_force, IoTKitSysCtl), 682 VMSTATE_UINT32(initsvtor1, IoTKitSysCtl), 683 VMSTATE_UINT32(nmi_enable, IoTKitSysCtl), 684 VMSTATE_UINT32(pdcm_pd_sys_sense, IoTKitSysCtl), 685 VMSTATE_UINT32(pdcm_pd_sram0_sense, IoTKitSysCtl), 686 VMSTATE_UINT32(pdcm_pd_sram1_sense, IoTKitSysCtl), 687 VMSTATE_UINT32(pdcm_pd_sram2_sense, IoTKitSysCtl), 688 VMSTATE_UINT32(pdcm_pd_sram3_sense, IoTKitSysCtl), 689 VMSTATE_END_OF_LIST() 690 } 691 }; 692 693 static const VMStateDescription iotkit_sysctl_vmstate = { 694 .name = "iotkit-sysctl", 695 .version_id = 1, 696 .minimum_version_id = 1, 697 .fields = (VMStateField[]) { 698 VMSTATE_UINT32(secure_debug, IoTKitSysCtl), 699 VMSTATE_UINT32(reset_syndrome, IoTKitSysCtl), 700 VMSTATE_UINT32(reset_mask, IoTKitSysCtl), 701 VMSTATE_UINT32(gretreg, IoTKitSysCtl), 702 VMSTATE_UINT32(initsvtor0, IoTKitSysCtl), 703 VMSTATE_UINT32(cpuwait, IoTKitSysCtl), 704 VMSTATE_UINT32(wicctrl, IoTKitSysCtl), 705 VMSTATE_END_OF_LIST() 706 }, 707 .subsections = (const VMStateDescription*[]) { 708 &iotkit_sysctl_sse200_vmstate, 709 NULL 710 } 711 }; 712 713 static Property iotkit_sysctl_props[] = { 714 DEFINE_PROP_UINT32("sse-version", IoTKitSysCtl, sse_version, 0), 715 DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl, cpuwait_rst, 0), 716 DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl, initsvtor0_rst, 717 0x10000000), 718 DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl, initsvtor1_rst, 719 0x10000000), 720 DEFINE_PROP_END_OF_LIST() 721 }; 722 723 static void iotkit_sysctl_class_init(ObjectClass *klass, void *data) 724 { 725 DeviceClass *dc = DEVICE_CLASS(klass); 726 727 dc->vmsd = &iotkit_sysctl_vmstate; 728 dc->reset = iotkit_sysctl_reset; 729 device_class_set_props(dc, iotkit_sysctl_props); 730 dc->realize = iotkit_sysctl_realize; 731 } 732 733 static const TypeInfo iotkit_sysctl_info = { 734 .name = TYPE_IOTKIT_SYSCTL, 735 .parent = TYPE_SYS_BUS_DEVICE, 736 .instance_size = sizeof(IoTKitSysCtl), 737 .instance_init = iotkit_sysctl_init, 738 .class_init = iotkit_sysctl_class_init, 739 }; 740 741 static void iotkit_sysctl_register_types(void) 742 { 743 type_register_static(&iotkit_sysctl_info); 744 } 745 746 type_init(iotkit_sysctl_register_types); 747