10a7bc1c0SAndrey Smirnov /* 20a7bc1c0SAndrey Smirnov * IMX7 Secure Non-Volatile Storage 30a7bc1c0SAndrey Smirnov * 40a7bc1c0SAndrey Smirnov * Copyright (c) 2018, Impinj, Inc. 50a7bc1c0SAndrey Smirnov * 60a7bc1c0SAndrey Smirnov * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 70a7bc1c0SAndrey Smirnov * 80a7bc1c0SAndrey Smirnov * This work is licensed under the terms of the GNU GPL, version 2 or later. 90a7bc1c0SAndrey Smirnov * See the COPYING file in the top-level directory. 100a7bc1c0SAndrey Smirnov * 110a7bc1c0SAndrey Smirnov * Bare minimum emulation code needed to support being able to shut 120a7bc1c0SAndrey Smirnov * down linux guest gracefully. 130a7bc1c0SAndrey Smirnov */ 140a7bc1c0SAndrey Smirnov 150a7bc1c0SAndrey Smirnov #include "qemu/osdep.h" 166f9c3aaaSNikita Ostrenkov #include "qemu/bitops.h" 176f9c3aaaSNikita Ostrenkov #include "qemu/timer.h" 186f9c3aaaSNikita Ostrenkov #include "migration/vmstate.h" 190a7bc1c0SAndrey Smirnov #include "hw/misc/imx7_snvs.h" 206f9c3aaaSNikita Ostrenkov #include "qemu/cutils.h" 210b8fa32fSMarkus Armbruster #include "qemu/module.h" 226f9c3aaaSNikita Ostrenkov #include "sysemu/sysemu.h" 236f9c3aaaSNikita Ostrenkov #include "sysemu/rtc.h" 2454d31236SMarkus Armbruster #include "sysemu/runstate.h" 25bb2fc5b9SBernhard Beschow #include "trace.h" 260a7bc1c0SAndrey Smirnov 276f9c3aaaSNikita Ostrenkov #define RTC_FREQ 32768ULL 286f9c3aaaSNikita Ostrenkov 296f9c3aaaSNikita Ostrenkov static const VMStateDescription vmstate_imx7_snvs = { 306f9c3aaaSNikita Ostrenkov .name = TYPE_IMX7_SNVS, 316f9c3aaaSNikita Ostrenkov .version_id = 1, 326f9c3aaaSNikita Ostrenkov .minimum_version_id = 1, 33*e4ea952fSRichard Henderson .fields = (const VMStateField[]) { 346f9c3aaaSNikita Ostrenkov VMSTATE_UINT64(tick_offset, IMX7SNVSState), 356f9c3aaaSNikita Ostrenkov VMSTATE_UINT64(lpcr, IMX7SNVSState), 366f9c3aaaSNikita Ostrenkov VMSTATE_END_OF_LIST() 376f9c3aaaSNikita Ostrenkov } 386f9c3aaaSNikita Ostrenkov }; 396f9c3aaaSNikita Ostrenkov 406f9c3aaaSNikita Ostrenkov static uint64_t imx7_snvs_get_count(IMX7SNVSState *s) 416f9c3aaaSNikita Ostrenkov { 426f9c3aaaSNikita Ostrenkov uint64_t ticks = muldiv64(qemu_clock_get_ns(rtc_clock), RTC_FREQ, 436f9c3aaaSNikita Ostrenkov NANOSECONDS_PER_SECOND); 446f9c3aaaSNikita Ostrenkov return s->tick_offset + ticks; 456f9c3aaaSNikita Ostrenkov } 466f9c3aaaSNikita Ostrenkov 470a7bc1c0SAndrey Smirnov static uint64_t imx7_snvs_read(void *opaque, hwaddr offset, unsigned size) 480a7bc1c0SAndrey Smirnov { 496f9c3aaaSNikita Ostrenkov IMX7SNVSState *s = IMX7_SNVS(opaque); 506f9c3aaaSNikita Ostrenkov uint64_t ret = 0; 51bb2fc5b9SBernhard Beschow 526f9c3aaaSNikita Ostrenkov switch (offset) { 536f9c3aaaSNikita Ostrenkov case SNVS_LPSRTCMR: 546f9c3aaaSNikita Ostrenkov ret = extract64(imx7_snvs_get_count(s), 32, 15); 556f9c3aaaSNikita Ostrenkov break; 566f9c3aaaSNikita Ostrenkov case SNVS_LPSRTCLR: 576f9c3aaaSNikita Ostrenkov ret = extract64(imx7_snvs_get_count(s), 0, 32); 586f9c3aaaSNikita Ostrenkov break; 596f9c3aaaSNikita Ostrenkov case SNVS_LPCR: 606f9c3aaaSNikita Ostrenkov ret = s->lpcr; 616f9c3aaaSNikita Ostrenkov break; 626f9c3aaaSNikita Ostrenkov } 636f9c3aaaSNikita Ostrenkov 646f9c3aaaSNikita Ostrenkov trace_imx7_snvs_read(offset, ret, size); 656f9c3aaaSNikita Ostrenkov 666f9c3aaaSNikita Ostrenkov return ret; 676f9c3aaaSNikita Ostrenkov } 686f9c3aaaSNikita Ostrenkov 696f9c3aaaSNikita Ostrenkov static void imx7_snvs_reset(DeviceState *dev) 706f9c3aaaSNikita Ostrenkov { 716f9c3aaaSNikita Ostrenkov IMX7SNVSState *s = IMX7_SNVS(dev); 726f9c3aaaSNikita Ostrenkov 736f9c3aaaSNikita Ostrenkov s->lpcr = 0; 740a7bc1c0SAndrey Smirnov } 750a7bc1c0SAndrey Smirnov 760a7bc1c0SAndrey Smirnov static void imx7_snvs_write(void *opaque, hwaddr offset, 770a7bc1c0SAndrey Smirnov uint64_t v, unsigned size) 780a7bc1c0SAndrey Smirnov { 796f9c3aaaSNikita Ostrenkov trace_imx7_snvs_write(offset, v, size); 806f9c3aaaSNikita Ostrenkov 816f9c3aaaSNikita Ostrenkov IMX7SNVSState *s = IMX7_SNVS(opaque); 826f9c3aaaSNikita Ostrenkov 836f9c3aaaSNikita Ostrenkov uint64_t new_value = 0, snvs_count = 0; 846f9c3aaaSNikita Ostrenkov 856f9c3aaaSNikita Ostrenkov if (offset == SNVS_LPSRTCMR || offset == SNVS_LPSRTCLR) { 866f9c3aaaSNikita Ostrenkov snvs_count = imx7_snvs_get_count(s); 876f9c3aaaSNikita Ostrenkov } 886f9c3aaaSNikita Ostrenkov 896f9c3aaaSNikita Ostrenkov switch (offset) { 906f9c3aaaSNikita Ostrenkov case SNVS_LPSRTCMR: 916f9c3aaaSNikita Ostrenkov new_value = deposit64(snvs_count, 32, 32, v); 926f9c3aaaSNikita Ostrenkov break; 936f9c3aaaSNikita Ostrenkov case SNVS_LPSRTCLR: 946f9c3aaaSNikita Ostrenkov new_value = deposit64(snvs_count, 0, 32, v); 956f9c3aaaSNikita Ostrenkov break; 966f9c3aaaSNikita Ostrenkov case SNVS_LPCR: { 976f9c3aaaSNikita Ostrenkov s->lpcr = v; 986f9c3aaaSNikita Ostrenkov 990a7bc1c0SAndrey Smirnov const uint32_t mask = SNVS_LPCR_TOP | SNVS_LPCR_DP_EN; 1000a7bc1c0SAndrey Smirnov 1016f9c3aaaSNikita Ostrenkov if ((v & mask) == mask) { 1020a7bc1c0SAndrey Smirnov qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 1030a7bc1c0SAndrey Smirnov } 1046f9c3aaaSNikita Ostrenkov break; 1056f9c3aaaSNikita Ostrenkov } 1066f9c3aaaSNikita Ostrenkov } 1076f9c3aaaSNikita Ostrenkov 1086f9c3aaaSNikita Ostrenkov if (offset == SNVS_LPSRTCMR || offset == SNVS_LPSRTCLR) { 1096f9c3aaaSNikita Ostrenkov s->tick_offset += new_value - snvs_count; 1106f9c3aaaSNikita Ostrenkov } 1110a7bc1c0SAndrey Smirnov } 1120a7bc1c0SAndrey Smirnov 1130a7bc1c0SAndrey Smirnov static const struct MemoryRegionOps imx7_snvs_ops = { 1140a7bc1c0SAndrey Smirnov .read = imx7_snvs_read, 1150a7bc1c0SAndrey Smirnov .write = imx7_snvs_write, 1160a7bc1c0SAndrey Smirnov .endianness = DEVICE_NATIVE_ENDIAN, 1170a7bc1c0SAndrey Smirnov .impl = { 1180a7bc1c0SAndrey Smirnov /* 1190a7bc1c0SAndrey Smirnov * Our device would not work correctly if the guest was doing 1200a7bc1c0SAndrey Smirnov * unaligned access. This might not be a limitation on the real 1210a7bc1c0SAndrey Smirnov * device but in practice there is no reason for a guest to access 1220a7bc1c0SAndrey Smirnov * this device unaligned. 1230a7bc1c0SAndrey Smirnov */ 1240a7bc1c0SAndrey Smirnov .min_access_size = 4, 1250a7bc1c0SAndrey Smirnov .max_access_size = 4, 1260a7bc1c0SAndrey Smirnov .unaligned = false, 1270a7bc1c0SAndrey Smirnov }, 1280a7bc1c0SAndrey Smirnov }; 1290a7bc1c0SAndrey Smirnov 1300a7bc1c0SAndrey Smirnov static void imx7_snvs_init(Object *obj) 1310a7bc1c0SAndrey Smirnov { 1320a7bc1c0SAndrey Smirnov SysBusDevice *sd = SYS_BUS_DEVICE(obj); 1330a7bc1c0SAndrey Smirnov IMX7SNVSState *s = IMX7_SNVS(obj); 1346f9c3aaaSNikita Ostrenkov struct tm tm; 1350a7bc1c0SAndrey Smirnov 1360a7bc1c0SAndrey Smirnov memory_region_init_io(&s->mmio, obj, &imx7_snvs_ops, s, 1370a7bc1c0SAndrey Smirnov TYPE_IMX7_SNVS, 0x1000); 1380a7bc1c0SAndrey Smirnov 1390a7bc1c0SAndrey Smirnov sysbus_init_mmio(sd, &s->mmio); 1406f9c3aaaSNikita Ostrenkov 1416f9c3aaaSNikita Ostrenkov qemu_get_timedate(&tm, 0); 1426f9c3aaaSNikita Ostrenkov s->tick_offset = mktimegm(&tm) - 1436f9c3aaaSNikita Ostrenkov qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; 1440a7bc1c0SAndrey Smirnov } 1450a7bc1c0SAndrey Smirnov 1460a7bc1c0SAndrey Smirnov static void imx7_snvs_class_init(ObjectClass *klass, void *data) 1470a7bc1c0SAndrey Smirnov { 1480a7bc1c0SAndrey Smirnov DeviceClass *dc = DEVICE_CLASS(klass); 1490a7bc1c0SAndrey Smirnov 1506f9c3aaaSNikita Ostrenkov dc->reset = imx7_snvs_reset; 1516f9c3aaaSNikita Ostrenkov dc->vmsd = &vmstate_imx7_snvs; 1520a7bc1c0SAndrey Smirnov dc->desc = "i.MX7 Secure Non-Volatile Storage Module"; 1530a7bc1c0SAndrey Smirnov } 1540a7bc1c0SAndrey Smirnov 1550a7bc1c0SAndrey Smirnov static const TypeInfo imx7_snvs_info = { 1560a7bc1c0SAndrey Smirnov .name = TYPE_IMX7_SNVS, 1570a7bc1c0SAndrey Smirnov .parent = TYPE_SYS_BUS_DEVICE, 1580a7bc1c0SAndrey Smirnov .instance_size = sizeof(IMX7SNVSState), 1590a7bc1c0SAndrey Smirnov .instance_init = imx7_snvs_init, 1600a7bc1c0SAndrey Smirnov .class_init = imx7_snvs_class_init, 1610a7bc1c0SAndrey Smirnov }; 1620a7bc1c0SAndrey Smirnov 1630a7bc1c0SAndrey Smirnov static void imx7_snvs_register_type(void) 1640a7bc1c0SAndrey Smirnov { 1650a7bc1c0SAndrey Smirnov type_register_static(&imx7_snvs_info); 1660a7bc1c0SAndrey Smirnov } 1670a7bc1c0SAndrey Smirnov type_init(imx7_snvs_register_type) 168