17eb0c8e8Sblueswir1 /* 27eb0c8e8Sblueswir1 * QEMU Sparc Sun4m ECC memory controller emulation 37eb0c8e8Sblueswir1 * 47eb0c8e8Sblueswir1 * Copyright (c) 2007 Robert Reif 57eb0c8e8Sblueswir1 * 67eb0c8e8Sblueswir1 * Permission is hereby granted, free of charge, to any person obtaining a copy 77eb0c8e8Sblueswir1 * of this software and associated documentation files (the "Software"), to deal 87eb0c8e8Sblueswir1 * in the Software without restriction, including without limitation the rights 97eb0c8e8Sblueswir1 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 107eb0c8e8Sblueswir1 * copies of the Software, and to permit persons to whom the Software is 117eb0c8e8Sblueswir1 * furnished to do so, subject to the following conditions: 127eb0c8e8Sblueswir1 * 137eb0c8e8Sblueswir1 * The above copyright notice and this permission notice shall be included in 147eb0c8e8Sblueswir1 * all copies or substantial portions of the Software. 157eb0c8e8Sblueswir1 * 167eb0c8e8Sblueswir1 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 177eb0c8e8Sblueswir1 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 187eb0c8e8Sblueswir1 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 197eb0c8e8Sblueswir1 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 207eb0c8e8Sblueswir1 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 217eb0c8e8Sblueswir1 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 227eb0c8e8Sblueswir1 * THE SOFTWARE. 237eb0c8e8Sblueswir1 */ 2449e66373SBlue Swirl 250d1c9782SPeter Maydell #include "qemu/osdep.h" 2664552b6bSMarkus Armbruster #include "hw/irq.h" 27a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 2883c9f4caSPaolo Bonzini #include "hw/sysbus.h" 29d6454270SMarkus Armbruster #include "migration/vmstate.h" 300b8fa32fSMarkus Armbruster #include "qemu/module.h" 3197bf4851SBlue Swirl #include "trace.h" 32db1015e9SEduardo Habkost #include "qom/object.h" 337eb0c8e8Sblueswir1 347eb0c8e8Sblueswir1 /* There are 3 versions of this chip used in SMP sun4m systems: 357eb0c8e8Sblueswir1 * MCC (version 0, implementation 0) SS-600MP 367eb0c8e8Sblueswir1 * EMC (version 0, implementation 1) SS-10 377eb0c8e8Sblueswir1 * SMC (version 0, implementation 2) SS-10SX and SS-20 385ac574c4SBlue Swirl * 395ac574c4SBlue Swirl * Chipset docs: 405ac574c4SBlue Swirl * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01, 415ac574c4SBlue Swirl * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf 427eb0c8e8Sblueswir1 */ 437eb0c8e8Sblueswir1 440bb3602cSblueswir1 #define ECC_MCC 0x00000000 450bb3602cSblueswir1 #define ECC_EMC 0x10000000 460bb3602cSblueswir1 #define ECC_SMC 0x20000000 470bb3602cSblueswir1 488f2ad0a3Sblueswir1 /* Register indexes */ 49dd53ded3Sblueswir1 #define ECC_MER 0 /* Memory Enable Register */ 508f2ad0a3Sblueswir1 #define ECC_MDR 1 /* Memory Delay Register */ 518f2ad0a3Sblueswir1 #define ECC_MFSR 2 /* Memory Fault Status Register */ 528f2ad0a3Sblueswir1 #define ECC_VCR 3 /* Video Configuration Register */ 538f2ad0a3Sblueswir1 #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */ 548f2ad0a3Sblueswir1 #define ECC_MFAR1 5 /* Memory Fault Address Register 1 */ 558f2ad0a3Sblueswir1 #define ECC_DR 6 /* Diagnostic Register */ 568f2ad0a3Sblueswir1 #define ECC_ECR0 7 /* Event Count Register 0 */ 578f2ad0a3Sblueswir1 #define ECC_ECR1 8 /* Event Count Register 1 */ 587eb0c8e8Sblueswir1 597eb0c8e8Sblueswir1 /* ECC fault control register */ 60dd53ded3Sblueswir1 #define ECC_MER_EE 0x00000001 /* Enable ECC checking */ 6177f193daSblueswir1 #define ECC_MER_EI 0x00000002 /* Enable Interrupts on 6277f193daSblueswir1 correctable errors */ 63dd53ded3Sblueswir1 #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */ 64dd53ded3Sblueswir1 #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */ 65dd53ded3Sblueswir1 #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */ 66dd53ded3Sblueswir1 #define ECC_MER_MRR3 0x00000020 /* SIMM 3 */ 67dd53ded3Sblueswir1 #define ECC_MER_MRR4 0x00000040 /* SIMM 4 */ 68dd53ded3Sblueswir1 #define ECC_MER_MRR5 0x00000080 /* SIMM 5 */ 69dd53ded3Sblueswir1 #define ECC_MER_MRR6 0x00000100 /* SIMM 6 */ 70dd53ded3Sblueswir1 #define ECC_MER_MRR7 0x00000200 /* SIMM 7 */ 710bb3602cSblueswir1 #define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */ 72dd53ded3Sblueswir1 #define ECC_MER_MRR 0x000003fc /* MRR mask */ 730bb3602cSblueswir1 #define ECC_MER_A 0x00000400 /* Memory controller addr map select */ 7477f193daSblueswir1 #define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */ 75dd53ded3Sblueswir1 #define ECC_MER_VER 0x0f000000 /* Version */ 76dd53ded3Sblueswir1 #define ECC_MER_IMPL 0xf0000000 /* Implementation */ 770bb3602cSblueswir1 #define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */ 780bb3602cSblueswir1 #define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */ 790bb3602cSblueswir1 #define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */ 80dd53ded3Sblueswir1 81dd53ded3Sblueswir1 /* ECC memory delay register */ 82dd53ded3Sblueswir1 #define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */ 83dd53ded3Sblueswir1 #define ECC_MDR_MI 0x00001c00 /* MIH Delay */ 84dd53ded3Sblueswir1 #define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */ 85dd53ded3Sblueswir1 #define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */ 86dd53ded3Sblueswir1 #define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */ 87dd53ded3Sblueswir1 #define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */ 88dd53ded3Sblueswir1 #define ECC_MDR_RSC 0x80000000 /* Refresh load control */ 89dd53ded3Sblueswir1 #define ECC_MDR_MASK 0x7fffffff 907eb0c8e8Sblueswir1 917eb0c8e8Sblueswir1 /* ECC fault status register */ 92dd53ded3Sblueswir1 #define ECC_MFSR_CE 0x00000001 /* Correctable error */ 93dd53ded3Sblueswir1 #define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */ 94dd53ded3Sblueswir1 #define ECC_MFSR_TO 0x00000004 /* Timeout on write */ 95dd53ded3Sblueswir1 #define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */ 96dd53ded3Sblueswir1 #define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */ 97dd53ded3Sblueswir1 #define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */ 98dd53ded3Sblueswir1 #define ECC_MFSR_ME 0x00010000 /* Multiple errors */ 99dd53ded3Sblueswir1 #define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */ 1007eb0c8e8Sblueswir1 1017eb0c8e8Sblueswir1 /* ECC fault address register 0 */ 102dd53ded3Sblueswir1 #define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */ 103dd53ded3Sblueswir1 #define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */ 104dd53ded3Sblueswir1 #define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */ 105dd53ded3Sblueswir1 #define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */ 106dd53ded3Sblueswir1 #define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */ 107dd53ded3Sblueswir1 #define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */ 108dd53ded3Sblueswir1 #define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */ 109dd53ded3Sblueswir1 #define ECC_MFAR0_S 0x08000000 /* Supervisor mode */ 110dd53ded3Sblueswir1 #define ECC_MFARO_MID 0xf0000000 /* Module ID */ 1117eb0c8e8Sblueswir1 1127eb0c8e8Sblueswir1 /* ECC diagnostic register */ 113dd53ded3Sblueswir1 #define ECC_DR_CBX 0x00000001 114dd53ded3Sblueswir1 #define ECC_DR_CB0 0x00000002 115dd53ded3Sblueswir1 #define ECC_DR_CB1 0x00000004 116dd53ded3Sblueswir1 #define ECC_DR_CB2 0x00000008 117dd53ded3Sblueswir1 #define ECC_DR_CB4 0x00000010 118dd53ded3Sblueswir1 #define ECC_DR_CB8 0x00000020 119dd53ded3Sblueswir1 #define ECC_DR_CB16 0x00000040 120dd53ded3Sblueswir1 #define ECC_DR_CB32 0x00000080 121dd53ded3Sblueswir1 #define ECC_DR_DMODE 0x00000c00 1227eb0c8e8Sblueswir1 123dd53ded3Sblueswir1 #define ECC_NREGS 9 1247eb0c8e8Sblueswir1 #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t)) 125dd53ded3Sblueswir1 126dd53ded3Sblueswir1 #define ECC_DIAG_SIZE 4 127dd53ded3Sblueswir1 #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) 1287eb0c8e8Sblueswir1 129100bb15cSAndreas Färber #define TYPE_ECC_MEMCTL "eccmemctl" 1308063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(ECCState, ECC_MEMCTL) 131100bb15cSAndreas Färber 132db1015e9SEduardo Habkost struct ECCState { 133100bb15cSAndreas Färber SysBusDevice parent_obj; 134100bb15cSAndreas Färber 1357ef57ccaSAvi Kivity MemoryRegion iomem, iomem_diag; 136e42c20b4Sblueswir1 qemu_irq irq; 1377eb0c8e8Sblueswir1 uint32_t regs[ECC_NREGS]; 138dd53ded3Sblueswir1 uint8_t diag[ECC_DIAG_SIZE]; 1390bb3602cSblueswir1 uint32_t version; 140db1015e9SEduardo Habkost }; 1417eb0c8e8Sblueswir1 142a8170e5eSAvi Kivity static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val, 1437ef57ccaSAvi Kivity unsigned size) 1447eb0c8e8Sblueswir1 { 1457eb0c8e8Sblueswir1 ECCState *s = opaque; 1467eb0c8e8Sblueswir1 147e64d7d59Sblueswir1 switch (addr >> 2) { 148dd53ded3Sblueswir1 case ECC_MER: 1490bb3602cSblueswir1 if (s->version == ECC_MCC) 1500bb3602cSblueswir1 s->regs[ECC_MER] = (val & ECC_MER_MASK_0); 1510bb3602cSblueswir1 else if (s->version == ECC_EMC) 1520bb3602cSblueswir1 s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1); 1530bb3602cSblueswir1 else if (s->version == ECC_SMC) 1540bb3602cSblueswir1 s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2); 15597bf4851SBlue Swirl trace_ecc_mem_writel_mer(val); 1567eb0c8e8Sblueswir1 break; 157dd53ded3Sblueswir1 case ECC_MDR: 1588f2ad0a3Sblueswir1 s->regs[ECC_MDR] = val & ECC_MDR_MASK; 15997bf4851SBlue Swirl trace_ecc_mem_writel_mdr(val); 1607eb0c8e8Sblueswir1 break; 161dd53ded3Sblueswir1 case ECC_MFSR: 1628f2ad0a3Sblueswir1 s->regs[ECC_MFSR] = val; 1630bb3602cSblueswir1 qemu_irq_lower(s->irq); 16497bf4851SBlue Swirl trace_ecc_mem_writel_mfsr(val); 1657eb0c8e8Sblueswir1 break; 166dd53ded3Sblueswir1 case ECC_VCR: 1678f2ad0a3Sblueswir1 s->regs[ECC_VCR] = val; 16897bf4851SBlue Swirl trace_ecc_mem_writel_vcr(val); 1697eb0c8e8Sblueswir1 break; 170dd53ded3Sblueswir1 case ECC_DR: 1718f2ad0a3Sblueswir1 s->regs[ECC_DR] = val; 17297bf4851SBlue Swirl trace_ecc_mem_writel_dr(val); 1737eb0c8e8Sblueswir1 break; 174dd53ded3Sblueswir1 case ECC_ECR0: 1758f2ad0a3Sblueswir1 s->regs[ECC_ECR0] = val; 17697bf4851SBlue Swirl trace_ecc_mem_writel_ecr0(val); 177dd53ded3Sblueswir1 break; 178dd53ded3Sblueswir1 case ECC_ECR1: 1798f2ad0a3Sblueswir1 s->regs[ECC_ECR0] = val; 18097bf4851SBlue Swirl trace_ecc_mem_writel_ecr1(val); 1817eb0c8e8Sblueswir1 break; 1827eb0c8e8Sblueswir1 } 1837eb0c8e8Sblueswir1 } 1847eb0c8e8Sblueswir1 185a8170e5eSAvi Kivity static uint64_t ecc_mem_read(void *opaque, hwaddr addr, 1867ef57ccaSAvi Kivity unsigned size) 1877eb0c8e8Sblueswir1 { 1887eb0c8e8Sblueswir1 ECCState *s = opaque; 1897eb0c8e8Sblueswir1 uint32_t ret = 0; 1907eb0c8e8Sblueswir1 191e64d7d59Sblueswir1 switch (addr >> 2) { 192dd53ded3Sblueswir1 case ECC_MER: 1938f2ad0a3Sblueswir1 ret = s->regs[ECC_MER]; 19497bf4851SBlue Swirl trace_ecc_mem_readl_mer(ret); 1957eb0c8e8Sblueswir1 break; 196dd53ded3Sblueswir1 case ECC_MDR: 1978f2ad0a3Sblueswir1 ret = s->regs[ECC_MDR]; 19897bf4851SBlue Swirl trace_ecc_mem_readl_mdr(ret); 1997eb0c8e8Sblueswir1 break; 200dd53ded3Sblueswir1 case ECC_MFSR: 2018f2ad0a3Sblueswir1 ret = s->regs[ECC_MFSR]; 20297bf4851SBlue Swirl trace_ecc_mem_readl_mfsr(ret); 2037eb0c8e8Sblueswir1 break; 204dd53ded3Sblueswir1 case ECC_VCR: 2058f2ad0a3Sblueswir1 ret = s->regs[ECC_VCR]; 20697bf4851SBlue Swirl trace_ecc_mem_readl_vcr(ret); 2077eb0c8e8Sblueswir1 break; 208dd53ded3Sblueswir1 case ECC_MFAR0: 2098f2ad0a3Sblueswir1 ret = s->regs[ECC_MFAR0]; 21097bf4851SBlue Swirl trace_ecc_mem_readl_mfar0(ret); 2117eb0c8e8Sblueswir1 break; 212dd53ded3Sblueswir1 case ECC_MFAR1: 2138f2ad0a3Sblueswir1 ret = s->regs[ECC_MFAR1]; 21497bf4851SBlue Swirl trace_ecc_mem_readl_mfar1(ret); 2157eb0c8e8Sblueswir1 break; 216dd53ded3Sblueswir1 case ECC_DR: 2178f2ad0a3Sblueswir1 ret = s->regs[ECC_DR]; 21897bf4851SBlue Swirl trace_ecc_mem_readl_dr(ret); 2197eb0c8e8Sblueswir1 break; 220dd53ded3Sblueswir1 case ECC_ECR0: 2218f2ad0a3Sblueswir1 ret = s->regs[ECC_ECR0]; 22297bf4851SBlue Swirl trace_ecc_mem_readl_ecr0(ret); 223dd53ded3Sblueswir1 break; 224dd53ded3Sblueswir1 case ECC_ECR1: 2258f2ad0a3Sblueswir1 ret = s->regs[ECC_ECR0]; 22697bf4851SBlue Swirl trace_ecc_mem_readl_ecr1(ret); 2277eb0c8e8Sblueswir1 break; 2287eb0c8e8Sblueswir1 } 2297eb0c8e8Sblueswir1 return ret; 2307eb0c8e8Sblueswir1 } 2317eb0c8e8Sblueswir1 2327ef57ccaSAvi Kivity static const MemoryRegionOps ecc_mem_ops = { 2337ef57ccaSAvi Kivity .read = ecc_mem_read, 2347ef57ccaSAvi Kivity .write = ecc_mem_write, 2357ef57ccaSAvi Kivity .endianness = DEVICE_NATIVE_ENDIAN, 2367ef57ccaSAvi Kivity .valid = { 2377ef57ccaSAvi Kivity .min_access_size = 4, 2387ef57ccaSAvi Kivity .max_access_size = 4, 2397ef57ccaSAvi Kivity }, 2407eb0c8e8Sblueswir1 }; 2417eb0c8e8Sblueswir1 242a8170e5eSAvi Kivity static void ecc_diag_mem_write(void *opaque, hwaddr addr, 2437ef57ccaSAvi Kivity uint64_t val, unsigned size) 244dd53ded3Sblueswir1 { 245dd53ded3Sblueswir1 ECCState *s = opaque; 246dd53ded3Sblueswir1 24797bf4851SBlue Swirl trace_ecc_diag_mem_writeb(addr, val); 248dd53ded3Sblueswir1 s->diag[addr & ECC_DIAG_MASK] = val; 249dd53ded3Sblueswir1 } 250dd53ded3Sblueswir1 251a8170e5eSAvi Kivity static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr, 2527ef57ccaSAvi Kivity unsigned size) 253dd53ded3Sblueswir1 { 254dd53ded3Sblueswir1 ECCState *s = opaque; 255e64d7d59Sblueswir1 uint32_t ret = s->diag[(int)addr]; 256e64d7d59Sblueswir1 25797bf4851SBlue Swirl trace_ecc_diag_mem_readb(addr, ret); 258dd53ded3Sblueswir1 return ret; 259dd53ded3Sblueswir1 } 260dd53ded3Sblueswir1 2617ef57ccaSAvi Kivity static const MemoryRegionOps ecc_diag_mem_ops = { 2627ef57ccaSAvi Kivity .read = ecc_diag_mem_read, 2637ef57ccaSAvi Kivity .write = ecc_diag_mem_write, 2647ef57ccaSAvi Kivity .endianness = DEVICE_NATIVE_ENDIAN, 2657ef57ccaSAvi Kivity .valid = { 2667ef57ccaSAvi Kivity .min_access_size = 1, 2677ef57ccaSAvi Kivity .max_access_size = 1, 2687ef57ccaSAvi Kivity }, 269dd53ded3Sblueswir1 }; 270dd53ded3Sblueswir1 271c21011a9SBlue Swirl static const VMStateDescription vmstate_ecc = { 272c21011a9SBlue Swirl .name ="ECC", 273c21011a9SBlue Swirl .version_id = 3, 274c21011a9SBlue Swirl .minimum_version_id = 3, 275*e4ea952fSRichard Henderson .fields = (const VMStateField[]) { 276c21011a9SBlue Swirl VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS), 277c21011a9SBlue Swirl VMSTATE_BUFFER(diag, ECCState), 278c21011a9SBlue Swirl VMSTATE_UINT32(version, ECCState), 279c21011a9SBlue Swirl VMSTATE_END_OF_LIST() 2807eb0c8e8Sblueswir1 } 281c21011a9SBlue Swirl }; 2827eb0c8e8Sblueswir1 2830284dc54SBlue Swirl static void ecc_reset(DeviceState *d) 2847eb0c8e8Sblueswir1 { 285100bb15cSAndreas Färber ECCState *s = ECC_MEMCTL(d); 2867eb0c8e8Sblueswir1 287100bb15cSAndreas Färber if (s->version == ECC_MCC) { 2880bb3602cSblueswir1 s->regs[ECC_MER] &= ECC_MER_REU; 289100bb15cSAndreas Färber } else { 2900bb3602cSblueswir1 s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR | 2910bb3602cSblueswir1 ECC_MER_DCI); 292100bb15cSAndreas Färber } 293dd53ded3Sblueswir1 s->regs[ECC_MDR] = 0x20; 294dd53ded3Sblueswir1 s->regs[ECC_MFSR] = 0; 295dd53ded3Sblueswir1 s->regs[ECC_VCR] = 0; 296dd53ded3Sblueswir1 s->regs[ECC_MFAR0] = 0x07c00000; 297dd53ded3Sblueswir1 s->regs[ECC_MFAR1] = 0; 298dd53ded3Sblueswir1 s->regs[ECC_DR] = 0; 299dd53ded3Sblueswir1 s->regs[ECC_ECR0] = 0; 300dd53ded3Sblueswir1 s->regs[ECC_ECR1] = 0; 3017eb0c8e8Sblueswir1 } 3027eb0c8e8Sblueswir1 303b229a576Sxiaoqiang zhao static void ecc_init(Object *obj) 3047eb0c8e8Sblueswir1 { 305b229a576Sxiaoqiang zhao ECCState *s = ECC_MEMCTL(obj); 306b229a576Sxiaoqiang zhao SysBusDevice *dev = SYS_BUS_DEVICE(obj); 3077eb0c8e8Sblueswir1 30849e66373SBlue Swirl sysbus_init_irq(dev, &s->irq); 309b229a576Sxiaoqiang zhao 310b229a576Sxiaoqiang zhao memory_region_init_io(&s->iomem, obj, &ecc_mem_ops, s, "ecc", ECC_SIZE); 311750ecd44SAvi Kivity sysbus_init_mmio(dev, &s->iomem); 312b229a576Sxiaoqiang zhao } 313b229a576Sxiaoqiang zhao 314b229a576Sxiaoqiang zhao static void ecc_realize(DeviceState *dev, Error **errp) 315b229a576Sxiaoqiang zhao { 316b229a576Sxiaoqiang zhao ECCState *s = ECC_MEMCTL(dev); 317b229a576Sxiaoqiang zhao SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 318b229a576Sxiaoqiang zhao 319b229a576Sxiaoqiang zhao s->regs[0] = s->version; 32049e66373SBlue Swirl 32149e66373SBlue Swirl if (s->version == ECC_MCC) { // SS-600MP only 3223c161542SPaolo Bonzini memory_region_init_io(&s->iomem_diag, OBJECT(dev), &ecc_diag_mem_ops, s, 3237ef57ccaSAvi Kivity "ecc.diag", ECC_DIAG_SIZE); 324b229a576Sxiaoqiang zhao sysbus_init_mmio(sbd, &s->iomem_diag); 325dd53ded3Sblueswir1 } 3267eb0c8e8Sblueswir1 } 32749e66373SBlue Swirl 328999e12bbSAnthony Liguori static Property ecc_properties[] = { 329c7bcc85dSPaolo Bonzini DEFINE_PROP_UINT32("version", ECCState, version, -1), 330d210a1b4SGerd Hoffmann DEFINE_PROP_END_OF_LIST(), 331999e12bbSAnthony Liguori }; 332999e12bbSAnthony Liguori 333999e12bbSAnthony Liguori static void ecc_class_init(ObjectClass *klass, void *data) 334999e12bbSAnthony Liguori { 33539bffca2SAnthony Liguori DeviceClass *dc = DEVICE_CLASS(klass); 336999e12bbSAnthony Liguori 337b229a576Sxiaoqiang zhao dc->realize = ecc_realize; 33839bffca2SAnthony Liguori dc->reset = ecc_reset; 33939bffca2SAnthony Liguori dc->vmsd = &vmstate_ecc; 3404f67d30bSMarc-André Lureau device_class_set_props(dc, ecc_properties); 341ee6847d1SGerd Hoffmann } 342999e12bbSAnthony Liguori 3438c43a6f0SAndreas Färber static const TypeInfo ecc_info = { 344100bb15cSAndreas Färber .name = TYPE_ECC_MEMCTL, 34539bffca2SAnthony Liguori .parent = TYPE_SYS_BUS_DEVICE, 34639bffca2SAnthony Liguori .instance_size = sizeof(ECCState), 347b229a576Sxiaoqiang zhao .instance_init = ecc_init, 348999e12bbSAnthony Liguori .class_init = ecc_class_init, 349ee6847d1SGerd Hoffmann }; 350ee6847d1SGerd Hoffmann 351ee6847d1SGerd Hoffmann 35283f7d43aSAndreas Färber static void ecc_register_types(void) 35349e66373SBlue Swirl { 35439bffca2SAnthony Liguori type_register_static(&ecc_info); 35549e66373SBlue Swirl } 35649e66373SBlue Swirl 35783f7d43aSAndreas Färber type_init(ecc_register_types) 358