1 /* 2 * BCM2835 CPRMAN clock manager 3 * 4 * Copyright (c) 2020 Luc Michel <luc@lmichel.fr> 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 /* 10 * This peripheral is roughly divided into 3 main parts: 11 * - the PLLs 12 * - the PLL channels 13 * - the clock muxes 14 * 15 * A main oscillator (xosc) feeds all the PLLs. Each PLLs has one or more 16 * channels. Those channel are then connected to the clock muxes. Each mux has 17 * multiples sources (usually the xosc, some of the PLL channels and some "test 18 * debug" clocks). A mux is configured to select a given source through its 19 * control register. Each mux has one output clock that also goes out of the 20 * CPRMAN. This output clock usually connects to another peripheral in the SoC 21 * (so a given mux is dedicated to a peripheral). 22 * 23 * At each level (PLL, channel and mux), the clock can be altered through 24 * dividers (and multipliers in case of the PLLs), and can be disabled (in this 25 * case, the next levels see no clock). 26 * 27 * This can be sum-up as follows (this is an example and not the actual BCM2835 28 * clock tree): 29 * 30 * /-->[PLL]-|->[PLL channel]--... [mux]--> to peripherals 31 * | |->[PLL channel] muxes takes [mux] 32 * | \->[PLL channel] inputs from [mux] 33 * | some channels [mux] 34 * [xosc]---|-->[PLL]-|->[PLL channel] and other srcs [mux] 35 * | \->[PLL channel] ...-->[mux] 36 * | [mux] 37 * \-->[PLL]--->[PLL channel] [mux] 38 * 39 * The page at https://elinux.org/The_Undocumented_Pi gives the actual clock 40 * tree configuration. 41 * 42 * The CPRMAN exposes clock outputs with the name of the clock mux suffixed 43 * with "-out" (e.g. "uart-out", "h264-out", ...). 44 */ 45 46 #include "qemu/osdep.h" 47 #include "qemu/log.h" 48 #include "migration/vmstate.h" 49 #include "hw/qdev-properties.h" 50 #include "hw/misc/bcm2835_cprman.h" 51 #include "hw/misc/bcm2835_cprman_internals.h" 52 #include "trace.h" 53 54 /* PLL */ 55 56 static void pll_reset(DeviceState *dev) 57 { 58 CprmanPllState *s = CPRMAN_PLL(dev); 59 const PLLResetInfo *info = &PLL_RESET_INFO[s->id]; 60 61 *s->reg_cm = info->cm; 62 *s->reg_a2w_ctrl = info->a2w_ctrl; 63 memcpy(s->reg_a2w_ana, info->a2w_ana, sizeof(info->a2w_ana)); 64 *s->reg_a2w_frac = info->a2w_frac; 65 } 66 67 static bool pll_is_locked(const CprmanPllState *pll) 68 { 69 return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN) 70 && !FIELD_EX32(*pll->reg_cm, CM_PLLx, ANARST); 71 } 72 73 static void pll_update(CprmanPllState *pll) 74 { 75 uint64_t freq, ndiv, fdiv, pdiv; 76 77 if (!pll_is_locked(pll)) { 78 clock_update(pll->out, 0); 79 return; 80 } 81 82 pdiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PDIV); 83 84 if (!pdiv) { 85 clock_update(pll->out, 0); 86 return; 87 } 88 89 ndiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, NDIV); 90 fdiv = FIELD_EX32(*pll->reg_a2w_frac, A2W_PLLx_FRAC, FRAC); 91 92 if (pll->reg_a2w_ana[1] & pll->prediv_mask) { 93 /* The prescaler doubles the parent frequency */ 94 ndiv *= 2; 95 fdiv *= 2; 96 } 97 98 /* 99 * We have a multiplier with an integer part (ndiv) and a fractional part 100 * (fdiv), and a divider (pdiv). 101 */ 102 freq = clock_get_hz(pll->xosc_in) * 103 ((ndiv << R_A2W_PLLx_FRAC_FRAC_LENGTH) + fdiv); 104 freq /= pdiv; 105 freq >>= R_A2W_PLLx_FRAC_FRAC_LENGTH; 106 107 clock_update_hz(pll->out, freq); 108 } 109 110 static void pll_xosc_update(void *opaque, ClockEvent event) 111 { 112 pll_update(CPRMAN_PLL(opaque)); 113 } 114 115 static void pll_init(Object *obj) 116 { 117 CprmanPllState *s = CPRMAN_PLL(obj); 118 119 s->xosc_in = qdev_init_clock_in(DEVICE(s), "xosc-in", pll_xosc_update, 120 s, ClockUpdate); 121 s->out = qdev_init_clock_out(DEVICE(s), "out"); 122 } 123 124 static const VMStateDescription pll_vmstate = { 125 .name = TYPE_CPRMAN_PLL, 126 .version_id = 1, 127 .minimum_version_id = 1, 128 .fields = (const VMStateField[]) { 129 VMSTATE_CLOCK(xosc_in, CprmanPllState), 130 VMSTATE_END_OF_LIST() 131 } 132 }; 133 134 static void pll_class_init(ObjectClass *klass, void *data) 135 { 136 DeviceClass *dc = DEVICE_CLASS(klass); 137 138 device_class_set_legacy_reset(dc, pll_reset); 139 dc->vmsd = &pll_vmstate; 140 /* Reason: Part of BCM2835CprmanState component */ 141 dc->user_creatable = false; 142 } 143 144 static const TypeInfo cprman_pll_info = { 145 .name = TYPE_CPRMAN_PLL, 146 .parent = TYPE_DEVICE, 147 .instance_size = sizeof(CprmanPllState), 148 .class_init = pll_class_init, 149 .instance_init = pll_init, 150 }; 151 152 153 /* PLL channel */ 154 155 static void pll_channel_reset(DeviceState *dev) 156 { 157 CprmanPllChannelState *s = CPRMAN_PLL_CHANNEL(dev); 158 const PLLChannelResetInfo *info = &PLL_CHANNEL_RESET_INFO[s->id]; 159 160 *s->reg_a2w_ctrl = info->a2w_ctrl; 161 } 162 163 static bool pll_channel_is_enabled(CprmanPllChannelState *channel) 164 { 165 /* 166 * XXX I'm not sure of the purpose of the LOAD field. The Linux driver does 167 * not set it when enabling the channel, but does clear it when disabling 168 * it. 169 */ 170 return !FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DISABLE) 171 && !(*channel->reg_cm & channel->hold_mask); 172 } 173 174 static void pll_channel_update(CprmanPllChannelState *channel) 175 { 176 uint64_t freq, div; 177 178 if (!pll_channel_is_enabled(channel)) { 179 clock_update(channel->out, 0); 180 return; 181 } 182 183 div = FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DIV); 184 185 if (!div) { 186 /* 187 * It seems that when the divider value is 0, it is considered as 188 * being maximum by the hardware (see the Linux driver). 189 */ 190 div = R_A2W_PLLx_CHANNELy_DIV_MASK; 191 } 192 193 /* Some channels have an additional fixed divider */ 194 freq = clock_get_hz(channel->pll_in) / (div * channel->fixed_divider); 195 196 clock_update_hz(channel->out, freq); 197 } 198 199 /* Update a PLL and all its channels */ 200 static void pll_update_all_channels(BCM2835CprmanState *s, 201 CprmanPllState *pll) 202 { 203 size_t i; 204 205 pll_update(pll); 206 207 for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { 208 CprmanPllChannelState *channel = &s->channels[i]; 209 if (channel->parent == pll->id) { 210 pll_channel_update(channel); 211 } 212 } 213 } 214 215 static void pll_channel_pll_in_update(void *opaque, ClockEvent event) 216 { 217 pll_channel_update(CPRMAN_PLL_CHANNEL(opaque)); 218 } 219 220 static void pll_channel_init(Object *obj) 221 { 222 CprmanPllChannelState *s = CPRMAN_PLL_CHANNEL(obj); 223 224 s->pll_in = qdev_init_clock_in(DEVICE(s), "pll-in", 225 pll_channel_pll_in_update, s, 226 ClockUpdate); 227 s->out = qdev_init_clock_out(DEVICE(s), "out"); 228 } 229 230 static const VMStateDescription pll_channel_vmstate = { 231 .name = TYPE_CPRMAN_PLL_CHANNEL, 232 .version_id = 1, 233 .minimum_version_id = 1, 234 .fields = (const VMStateField[]) { 235 VMSTATE_CLOCK(pll_in, CprmanPllChannelState), 236 VMSTATE_END_OF_LIST() 237 } 238 }; 239 240 static void pll_channel_class_init(ObjectClass *klass, void *data) 241 { 242 DeviceClass *dc = DEVICE_CLASS(klass); 243 244 device_class_set_legacy_reset(dc, pll_channel_reset); 245 dc->vmsd = &pll_channel_vmstate; 246 /* Reason: Part of BCM2835CprmanState component */ 247 dc->user_creatable = false; 248 } 249 250 static const TypeInfo cprman_pll_channel_info = { 251 .name = TYPE_CPRMAN_PLL_CHANNEL, 252 .parent = TYPE_DEVICE, 253 .instance_size = sizeof(CprmanPllChannelState), 254 .class_init = pll_channel_class_init, 255 .instance_init = pll_channel_init, 256 }; 257 258 259 /* clock mux */ 260 261 static bool clock_mux_is_enabled(CprmanClockMuxState *mux) 262 { 263 return FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, ENABLE); 264 } 265 266 static void clock_mux_update(CprmanClockMuxState *mux) 267 { 268 uint64_t freq; 269 uint32_t div, src = FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, SRC); 270 bool enabled = clock_mux_is_enabled(mux); 271 272 *mux->reg_ctl = FIELD_DP32(*mux->reg_ctl, CM_CLOCKx_CTL, BUSY, enabled); 273 274 if (!enabled) { 275 clock_update(mux->out, 0); 276 return; 277 } 278 279 freq = clock_get_hz(mux->srcs[src]); 280 281 if (mux->int_bits == 0 && mux->frac_bits == 0) { 282 clock_update_hz(mux->out, freq); 283 return; 284 } 285 286 /* 287 * The divider has an integer and a fractional part. The size of each part 288 * varies with the muxes (int_bits and frac_bits). Both parts are 289 * concatenated, with the integer part always starting at bit 12. 290 * 291 * 31 12 11 0 292 * ------------------------------ 293 * CM_DIV | | int | frac | | 294 * ------------------------------ 295 * <-----> <------> 296 * int_bits frac_bits 297 */ 298 div = extract32(*mux->reg_div, 299 R_CM_CLOCKx_DIV_FRAC_LENGTH - mux->frac_bits, 300 mux->int_bits + mux->frac_bits); 301 302 if (!div) { 303 clock_update(mux->out, 0); 304 return; 305 } 306 307 freq = muldiv64(freq, 1 << mux->frac_bits, div); 308 309 clock_update_hz(mux->out, freq); 310 } 311 312 static void clock_mux_src_update(void *opaque, ClockEvent event) 313 { 314 CprmanClockMuxState **backref = opaque; 315 CprmanClockMuxState *s = *backref; 316 CprmanClockMuxSource src = backref - s->backref; 317 318 if (FIELD_EX32(*s->reg_ctl, CM_CLOCKx_CTL, SRC) != src) { 319 return; 320 } 321 322 clock_mux_update(s); 323 } 324 325 static void clock_mux_reset(DeviceState *dev) 326 { 327 CprmanClockMuxState *clock = CPRMAN_CLOCK_MUX(dev); 328 const ClockMuxResetInfo *info = &CLOCK_MUX_RESET_INFO[clock->id]; 329 330 *clock->reg_ctl = info->cm_ctl; 331 *clock->reg_div = info->cm_div; 332 } 333 334 static void clock_mux_init(Object *obj) 335 { 336 CprmanClockMuxState *s = CPRMAN_CLOCK_MUX(obj); 337 size_t i; 338 339 for (i = 0; i < CPRMAN_NUM_CLOCK_MUX_SRC; i++) { 340 char *name = g_strdup_printf("srcs[%zu]", i); 341 s->backref[i] = s; 342 s->srcs[i] = qdev_init_clock_in(DEVICE(s), name, 343 clock_mux_src_update, 344 &s->backref[i], 345 ClockUpdate); 346 g_free(name); 347 } 348 349 s->out = qdev_init_clock_out(DEVICE(s), "out"); 350 } 351 352 static const VMStateDescription clock_mux_vmstate = { 353 .name = TYPE_CPRMAN_CLOCK_MUX, 354 .version_id = 1, 355 .minimum_version_id = 1, 356 .fields = (const VMStateField[]) { 357 VMSTATE_ARRAY_CLOCK(srcs, CprmanClockMuxState, 358 CPRMAN_NUM_CLOCK_MUX_SRC), 359 VMSTATE_END_OF_LIST() 360 } 361 }; 362 363 static void clock_mux_class_init(ObjectClass *klass, void *data) 364 { 365 DeviceClass *dc = DEVICE_CLASS(klass); 366 367 device_class_set_legacy_reset(dc, clock_mux_reset); 368 dc->vmsd = &clock_mux_vmstate; 369 /* Reason: Part of BCM2835CprmanState component */ 370 dc->user_creatable = false; 371 } 372 373 static const TypeInfo cprman_clock_mux_info = { 374 .name = TYPE_CPRMAN_CLOCK_MUX, 375 .parent = TYPE_DEVICE, 376 .instance_size = sizeof(CprmanClockMuxState), 377 .class_init = clock_mux_class_init, 378 .instance_init = clock_mux_init, 379 }; 380 381 382 /* DSI0HSCK mux */ 383 384 static void dsi0hsck_mux_update(CprmanDsi0HsckMuxState *s) 385 { 386 bool src_is_plld = FIELD_EX32(*s->reg_cm, CM_DSI0HSCK, SELPLLD); 387 Clock *src = src_is_plld ? s->plld_in : s->plla_in; 388 389 clock_update(s->out, clock_get(src)); 390 } 391 392 static void dsi0hsck_mux_in_update(void *opaque, ClockEvent event) 393 { 394 dsi0hsck_mux_update(CPRMAN_DSI0HSCK_MUX(opaque)); 395 } 396 397 static void dsi0hsck_mux_init(Object *obj) 398 { 399 CprmanDsi0HsckMuxState *s = CPRMAN_DSI0HSCK_MUX(obj); 400 DeviceState *dev = DEVICE(obj); 401 402 s->plla_in = qdev_init_clock_in(dev, "plla-in", dsi0hsck_mux_in_update, 403 s, ClockUpdate); 404 s->plld_in = qdev_init_clock_in(dev, "plld-in", dsi0hsck_mux_in_update, 405 s, ClockUpdate); 406 s->out = qdev_init_clock_out(DEVICE(s), "out"); 407 } 408 409 static const VMStateDescription dsi0hsck_mux_vmstate = { 410 .name = TYPE_CPRMAN_DSI0HSCK_MUX, 411 .version_id = 1, 412 .minimum_version_id = 1, 413 .fields = (const VMStateField[]) { 414 VMSTATE_CLOCK(plla_in, CprmanDsi0HsckMuxState), 415 VMSTATE_CLOCK(plld_in, CprmanDsi0HsckMuxState), 416 VMSTATE_END_OF_LIST() 417 } 418 }; 419 420 static void dsi0hsck_mux_class_init(ObjectClass *klass, void *data) 421 { 422 DeviceClass *dc = DEVICE_CLASS(klass); 423 424 dc->vmsd = &dsi0hsck_mux_vmstate; 425 /* Reason: Part of BCM2835CprmanState component */ 426 dc->user_creatable = false; 427 } 428 429 static const TypeInfo cprman_dsi0hsck_mux_info = { 430 .name = TYPE_CPRMAN_DSI0HSCK_MUX, 431 .parent = TYPE_DEVICE, 432 .instance_size = sizeof(CprmanDsi0HsckMuxState), 433 .class_init = dsi0hsck_mux_class_init, 434 .instance_init = dsi0hsck_mux_init, 435 }; 436 437 438 /* CPRMAN "top level" model */ 439 440 static uint32_t get_cm_lock(const BCM2835CprmanState *s) 441 { 442 static const int CM_LOCK_MAPPING[CPRMAN_NUM_PLL] = { 443 [CPRMAN_PLLA] = R_CM_LOCK_FLOCKA_SHIFT, 444 [CPRMAN_PLLC] = R_CM_LOCK_FLOCKC_SHIFT, 445 [CPRMAN_PLLD] = R_CM_LOCK_FLOCKD_SHIFT, 446 [CPRMAN_PLLH] = R_CM_LOCK_FLOCKH_SHIFT, 447 [CPRMAN_PLLB] = R_CM_LOCK_FLOCKB_SHIFT, 448 }; 449 450 uint32_t r = 0; 451 size_t i; 452 453 for (i = 0; i < CPRMAN_NUM_PLL; i++) { 454 r |= pll_is_locked(&s->plls[i]) << CM_LOCK_MAPPING[i]; 455 } 456 457 return r; 458 } 459 460 static uint64_t cprman_read(void *opaque, hwaddr offset, 461 unsigned size) 462 { 463 BCM2835CprmanState *s = CPRMAN(opaque); 464 uint64_t r = 0; 465 size_t idx = offset / sizeof(uint32_t); 466 467 switch (idx) { 468 case R_CM_LOCK: 469 r = get_cm_lock(s); 470 break; 471 472 default: 473 r = s->regs[idx]; 474 } 475 476 trace_bcm2835_cprman_read(offset, r); 477 return r; 478 } 479 480 static inline void update_pll_and_channels_from_cm(BCM2835CprmanState *s, 481 size_t idx) 482 { 483 size_t i; 484 485 for (i = 0; i < CPRMAN_NUM_PLL; i++) { 486 if (PLL_INIT_INFO[i].cm_offset == idx) { 487 pll_update_all_channels(s, &s->plls[i]); 488 return; 489 } 490 } 491 } 492 493 static inline void update_channel_from_a2w(BCM2835CprmanState *s, size_t idx) 494 { 495 size_t i; 496 497 for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { 498 if (PLL_CHANNEL_INIT_INFO[i].a2w_ctrl_offset == idx) { 499 pll_channel_update(&s->channels[i]); 500 return; 501 } 502 } 503 } 504 505 static inline void update_mux_from_cm(BCM2835CprmanState *s, size_t idx) 506 { 507 size_t i; 508 509 for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) { 510 if ((CLOCK_MUX_INIT_INFO[i].cm_offset == idx) || 511 (CLOCK_MUX_INIT_INFO[i].cm_offset + 4 == idx)) { 512 /* matches CM_CTL or CM_DIV mux register */ 513 clock_mux_update(&s->clock_muxes[i]); 514 return; 515 } 516 } 517 } 518 519 #define CASE_PLL_A2W_REGS(pll_) \ 520 case R_A2W_ ## pll_ ## _CTRL: \ 521 case R_A2W_ ## pll_ ## _ANA0: \ 522 case R_A2W_ ## pll_ ## _ANA1: \ 523 case R_A2W_ ## pll_ ## _ANA2: \ 524 case R_A2W_ ## pll_ ## _ANA3: \ 525 case R_A2W_ ## pll_ ## _FRAC 526 527 static void cprman_write(void *opaque, hwaddr offset, 528 uint64_t value, unsigned size) 529 { 530 BCM2835CprmanState *s = CPRMAN(opaque); 531 size_t idx = offset / sizeof(uint32_t); 532 533 if (FIELD_EX32(value, CPRMAN, PASSWORD) != CPRMAN_PASSWORD) { 534 trace_bcm2835_cprman_write_invalid_magic(offset, value); 535 return; 536 } 537 538 value &= ~R_CPRMAN_PASSWORD_MASK; 539 540 trace_bcm2835_cprman_write(offset, value); 541 s->regs[idx] = value; 542 543 switch (idx) { 544 case R_CM_PLLA ... R_CM_PLLH: 545 case R_CM_PLLB: 546 /* 547 * A given CM_PLLx register is shared by both the PLL and the channels 548 * of this PLL. 549 */ 550 update_pll_and_channels_from_cm(s, idx); 551 break; 552 553 CASE_PLL_A2W_REGS(PLLA) : 554 pll_update(&s->plls[CPRMAN_PLLA]); 555 break; 556 557 CASE_PLL_A2W_REGS(PLLC) : 558 pll_update(&s->plls[CPRMAN_PLLC]); 559 break; 560 561 CASE_PLL_A2W_REGS(PLLD) : 562 pll_update(&s->plls[CPRMAN_PLLD]); 563 break; 564 565 CASE_PLL_A2W_REGS(PLLH) : 566 pll_update(&s->plls[CPRMAN_PLLH]); 567 break; 568 569 CASE_PLL_A2W_REGS(PLLB) : 570 pll_update(&s->plls[CPRMAN_PLLB]); 571 break; 572 573 case R_A2W_PLLA_DSI0: 574 case R_A2W_PLLA_CORE: 575 case R_A2W_PLLA_PER: 576 case R_A2W_PLLA_CCP2: 577 case R_A2W_PLLC_CORE2: 578 case R_A2W_PLLC_CORE1: 579 case R_A2W_PLLC_PER: 580 case R_A2W_PLLC_CORE0: 581 case R_A2W_PLLD_DSI0: 582 case R_A2W_PLLD_CORE: 583 case R_A2W_PLLD_PER: 584 case R_A2W_PLLD_DSI1: 585 case R_A2W_PLLH_AUX: 586 case R_A2W_PLLH_RCAL: 587 case R_A2W_PLLH_PIX: 588 case R_A2W_PLLB_ARM: 589 update_channel_from_a2w(s, idx); 590 break; 591 592 case R_CM_GNRICCTL ... R_CM_SMIDIV: 593 case R_CM_TCNTCNT ... R_CM_VECDIV: 594 case R_CM_PULSECTL ... R_CM_PULSEDIV: 595 case R_CM_SDCCTL ... R_CM_ARMCTL: 596 case R_CM_AVEOCTL ... R_CM_EMMCDIV: 597 case R_CM_EMMC2CTL ... R_CM_EMMC2DIV: 598 update_mux_from_cm(s, idx); 599 break; 600 601 case R_CM_DSI0HSCK: 602 dsi0hsck_mux_update(&s->dsi0hsck_mux); 603 break; 604 } 605 } 606 607 #undef CASE_PLL_A2W_REGS 608 609 static const MemoryRegionOps cprman_ops = { 610 .read = cprman_read, 611 .write = cprman_write, 612 .endianness = DEVICE_LITTLE_ENDIAN, 613 .valid = { 614 /* 615 * Although this hasn't been checked against real hardware, nor the 616 * information can be found in a datasheet, it seems reasonable because 617 * of the "PASSWORD" magic value found in every registers. 618 */ 619 .min_access_size = 4, 620 .max_access_size = 4, 621 .unaligned = false, 622 }, 623 .impl = { 624 .max_access_size = 4, 625 }, 626 }; 627 628 static void cprman_reset(DeviceState *dev) 629 { 630 BCM2835CprmanState *s = CPRMAN(dev); 631 size_t i; 632 633 memset(s->regs, 0, sizeof(s->regs)); 634 635 for (i = 0; i < CPRMAN_NUM_PLL; i++) { 636 device_cold_reset(DEVICE(&s->plls[i])); 637 } 638 639 for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { 640 device_cold_reset(DEVICE(&s->channels[i])); 641 } 642 643 device_cold_reset(DEVICE(&s->dsi0hsck_mux)); 644 645 for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) { 646 device_cold_reset(DEVICE(&s->clock_muxes[i])); 647 } 648 649 clock_update_hz(s->xosc, s->xosc_freq); 650 } 651 652 static void cprman_init(Object *obj) 653 { 654 BCM2835CprmanState *s = CPRMAN(obj); 655 size_t i; 656 657 for (i = 0; i < CPRMAN_NUM_PLL; i++) { 658 object_initialize_child(obj, PLL_INIT_INFO[i].name, 659 &s->plls[i], TYPE_CPRMAN_PLL); 660 set_pll_init_info(s, &s->plls[i], i); 661 } 662 663 for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { 664 object_initialize_child(obj, PLL_CHANNEL_INIT_INFO[i].name, 665 &s->channels[i], 666 TYPE_CPRMAN_PLL_CHANNEL); 667 set_pll_channel_init_info(s, &s->channels[i], i); 668 } 669 670 object_initialize_child(obj, "dsi0hsck-mux", 671 &s->dsi0hsck_mux, TYPE_CPRMAN_DSI0HSCK_MUX); 672 s->dsi0hsck_mux.reg_cm = &s->regs[R_CM_DSI0HSCK]; 673 674 for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) { 675 char *alias; 676 677 object_initialize_child(obj, CLOCK_MUX_INIT_INFO[i].name, 678 &s->clock_muxes[i], 679 TYPE_CPRMAN_CLOCK_MUX); 680 set_clock_mux_init_info(s, &s->clock_muxes[i], i); 681 682 /* Expose muxes output as CPRMAN outputs */ 683 alias = g_strdup_printf("%s-out", CLOCK_MUX_INIT_INFO[i].name); 684 qdev_alias_clock(DEVICE(&s->clock_muxes[i]), "out", DEVICE(obj), alias); 685 g_free(alias); 686 } 687 688 s->xosc = clock_new(obj, "xosc"); 689 s->gnd = clock_new(obj, "gnd"); 690 691 clock_set(s->gnd, 0); 692 693 memory_region_init_io(&s->iomem, obj, &cprman_ops, 694 s, "bcm2835-cprman", 0x2000); 695 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); 696 } 697 698 static void connect_mux_sources(BCM2835CprmanState *s, 699 CprmanClockMuxState *mux, 700 const CprmanPllChannel *clk_mapping) 701 { 702 size_t i; 703 Clock *td0 = s->clock_muxes[CPRMAN_CLOCK_TD0].out; 704 Clock *td1 = s->clock_muxes[CPRMAN_CLOCK_TD1].out; 705 706 /* For sources from 0 to 3. Source 4 to 9 are mux specific */ 707 Clock * const CLK_SRC_MAPPING[] = { 708 [CPRMAN_CLOCK_SRC_GND] = s->gnd, 709 [CPRMAN_CLOCK_SRC_XOSC] = s->xosc, 710 [CPRMAN_CLOCK_SRC_TD0] = td0, 711 [CPRMAN_CLOCK_SRC_TD1] = td1, 712 }; 713 714 for (i = 0; i < CPRMAN_NUM_CLOCK_MUX_SRC; i++) { 715 CprmanPllChannel mapping = clk_mapping[i]; 716 Clock *src; 717 718 if (mapping == CPRMAN_CLOCK_SRC_FORCE_GROUND) { 719 src = s->gnd; 720 } else if (mapping == CPRMAN_CLOCK_SRC_DSI0HSCK) { 721 src = s->dsi0hsck_mux.out; 722 } else if (i < CPRMAN_CLOCK_SRC_PLLA) { 723 src = CLK_SRC_MAPPING[i]; 724 } else { 725 src = s->channels[mapping].out; 726 } 727 728 clock_set_source(mux->srcs[i], src); 729 } 730 } 731 732 static void cprman_realize(DeviceState *dev, Error **errp) 733 { 734 BCM2835CprmanState *s = CPRMAN(dev); 735 size_t i; 736 737 for (i = 0; i < CPRMAN_NUM_PLL; i++) { 738 CprmanPllState *pll = &s->plls[i]; 739 740 clock_set_source(pll->xosc_in, s->xosc); 741 742 if (!qdev_realize(DEVICE(pll), NULL, errp)) { 743 return; 744 } 745 } 746 747 for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { 748 CprmanPllChannelState *channel = &s->channels[i]; 749 CprmanPll parent = PLL_CHANNEL_INIT_INFO[i].parent; 750 Clock *parent_clk = s->plls[parent].out; 751 752 clock_set_source(channel->pll_in, parent_clk); 753 754 if (!qdev_realize(DEVICE(channel), NULL, errp)) { 755 return; 756 } 757 } 758 759 clock_set_source(s->dsi0hsck_mux.plla_in, 760 s->channels[CPRMAN_PLLA_CHANNEL_DSI0].out); 761 clock_set_source(s->dsi0hsck_mux.plld_in, 762 s->channels[CPRMAN_PLLD_CHANNEL_DSI0].out); 763 764 if (!qdev_realize(DEVICE(&s->dsi0hsck_mux), NULL, errp)) { 765 return; 766 } 767 768 for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) { 769 CprmanClockMuxState *clock_mux = &s->clock_muxes[i]; 770 771 connect_mux_sources(s, clock_mux, CLOCK_MUX_INIT_INFO[i].src_mapping); 772 773 if (!qdev_realize(DEVICE(clock_mux), NULL, errp)) { 774 return; 775 } 776 } 777 } 778 779 static const VMStateDescription cprman_vmstate = { 780 .name = TYPE_BCM2835_CPRMAN, 781 .version_id = 1, 782 .minimum_version_id = 1, 783 .fields = (const VMStateField[]) { 784 VMSTATE_UINT32_ARRAY(regs, BCM2835CprmanState, CPRMAN_NUM_REGS), 785 VMSTATE_END_OF_LIST() 786 } 787 }; 788 789 static const Property cprman_properties[] = { 790 DEFINE_PROP_UINT32("xosc-freq-hz", BCM2835CprmanState, xosc_freq, 19200000), 791 }; 792 793 static void cprman_class_init(ObjectClass *klass, void *data) 794 { 795 DeviceClass *dc = DEVICE_CLASS(klass); 796 797 dc->realize = cprman_realize; 798 device_class_set_legacy_reset(dc, cprman_reset); 799 dc->vmsd = &cprman_vmstate; 800 device_class_set_props(dc, cprman_properties); 801 } 802 803 static const TypeInfo cprman_info = { 804 .name = TYPE_BCM2835_CPRMAN, 805 .parent = TYPE_SYS_BUS_DEVICE, 806 .instance_size = sizeof(BCM2835CprmanState), 807 .class_init = cprman_class_init, 808 .instance_init = cprman_init, 809 }; 810 811 static void cprman_register_types(void) 812 { 813 type_register_static(&cprman_info); 814 type_register_static(&cprman_pll_info); 815 type_register_static(&cprman_pll_channel_info); 816 type_register_static(&cprman_clock_mux_info); 817 type_register_static(&cprman_dsi0hsck_mux_info); 818 } 819 820 type_init(cprman_register_types); 821