1 /* 2 * ASPEED SDRAM Memory Controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qemu/error-report.h" 14 #include "hw/misc/aspeed_sdmc.h" 15 #include "hw/qdev-properties.h" 16 #include "migration/vmstate.h" 17 #include "qapi/error.h" 18 #include "trace.h" 19 #include "qemu/units.h" 20 #include "qemu/cutils.h" 21 #include "qapi/visitor.h" 22 23 /* Protection Key Register */ 24 #define R_PROT (0x00 / 4) 25 #define PROT_UNLOCKED 0x01 26 #define PROT_HARDLOCKED 0x10 /* AST2600 */ 27 #define PROT_SOFTLOCKED 0x00 28 29 #define PROT_KEY_UNLOCK 0xFC600309 30 #define PROT_2700_KEY_UNLOCK 0x1688A8A8 31 #define PROT_KEY_HARDLOCK 0xDEADDEAD /* AST2600 */ 32 33 /* Configuration Register */ 34 #define R_CONF (0x04 / 4) 35 36 /* Interrupt control/status */ 37 #define R_ISR (0x50 / 4) 38 39 /* Control/Status Register #1 (ast2500) */ 40 #define R_STATUS1 (0x60 / 4) 41 #define PHY_BUSY_STATE BIT(0) 42 #define PHY_PLL_LOCK_STATUS BIT(4) 43 44 /* Reserved */ 45 #define R_MCR6C (0x6c / 4) 46 47 #define R_ECC_TEST_CTRL (0x70 / 4) 48 #define ECC_TEST_FINISHED BIT(12) 49 #define ECC_TEST_FAIL BIT(13) 50 51 #define R_TEST_START_LEN (0x74 / 4) 52 #define R_TEST_FAIL_DQ (0x78 / 4) 53 #define R_TEST_INIT_VAL (0x7c / 4) 54 #define R_DRAM_SW (0x88 / 4) 55 #define R_DRAM_TIME (0x8c / 4) 56 #define R_ECC_ERR_INJECT (0xb4 / 4) 57 58 /* AST2700 Register */ 59 #define R_2700_PROT (0x00 / 4) 60 #define R_INT_STATUS (0x04 / 4) 61 #define R_INT_CLEAR (0x08 / 4) 62 #define R_INT_MASK (0x0c / 4) 63 #define R_MAIN_CONF (0x10 / 4) 64 #define R_MAIN_CONTROL (0x14 / 4) 65 #define R_MAIN_STATUS (0x18 / 4) 66 #define R_ERR_STATUS (0x1c / 4) 67 #define R_ECC_FAIL_STATUS (0x78 / 4) 68 #define R_ECC_FAIL_ADDR (0x7c / 4) 69 #define R_ECC_TESTING_CONTROL (0x80 / 4) 70 #define R_PROT_REGION_LOCK_STATUS (0x94 / 4) 71 #define R_TEST_FAIL_ADDR (0xd4 / 4) 72 #define R_TEST_FAIL_D0 (0xd8 / 4) 73 #define R_TEST_FAIL_D1 (0xdc / 4) 74 #define R_TEST_FAIL_D2 (0xe0 / 4) 75 #define R_TEST_FAIL_D3 (0xe4 / 4) 76 #define R_DBG_STATUS (0xf4 / 4) 77 #define R_PHY_INTERFACE_STATUS (0xf8 / 4) 78 #define R_GRAPHIC_MEM_BASE_ADDR (0x10c / 4) 79 #define R_PORT0_INTERFACE_MONITOR0 (0x240 / 4) 80 #define R_PORT0_INTERFACE_MONITOR1 (0x244 / 4) 81 #define R_PORT0_INTERFACE_MONITOR2 (0x248 / 4) 82 #define R_PORT1_INTERFACE_MONITOR0 (0x2c0 / 4) 83 #define R_PORT1_INTERFACE_MONITOR1 (0x2c4 / 4) 84 #define R_PORT1_INTERFACE_MONITOR2 (0x2c8 / 4) 85 #define R_PORT2_INTERFACE_MONITOR0 (0x340 / 4) 86 #define R_PORT2_INTERFACE_MONITOR1 (0x344 / 4) 87 #define R_PORT2_INTERFACE_MONITOR2 (0x348 / 4) 88 #define R_PORT3_INTERFACE_MONITOR0 (0x3c0 / 4) 89 #define R_PORT3_INTERFACE_MONITOR1 (0x3c4 / 4) 90 #define R_PORT3_INTERFACE_MONITOR2 (0x3c8 / 4) 91 #define R_PORT4_INTERFACE_MONITOR0 (0x440 / 4) 92 #define R_PORT4_INTERFACE_MONITOR1 (0x444 / 4) 93 #define R_PORT4_INTERFACE_MONITOR2 (0x448 / 4) 94 #define R_PORT5_INTERFACE_MONITOR0 (0x4c0 / 4) 95 #define R_PORT5_INTERFACE_MONITOR1 (0x4c4 / 4) 96 #define R_PORT5_INTERFACE_MONITOR2 (0x4c8 / 4) 97 98 /* 99 * Configuration register Ox4 (for Aspeed AST2400 SOC) 100 * 101 * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is 102 * what we care about right now as it is checked by U-Boot to 103 * determine the RAM size. 104 */ 105 106 #define ASPEED_SDMC_RESERVED 0xFFFFF800 /* 31:11 reserved */ 107 #define ASPEED_SDMC_AST2300_COMPAT (1 << 10) 108 #define ASPEED_SDMC_SCRAMBLE_PATTERN (1 << 9) 109 #define ASPEED_SDMC_DATA_SCRAMBLE (1 << 8) 110 #define ASPEED_SDMC_ECC_ENABLE (1 << 7) 111 #define ASPEED_SDMC_VGA_COMPAT (1 << 6) /* readonly */ 112 #define ASPEED_SDMC_DRAM_BANK (1 << 5) 113 #define ASPEED_SDMC_DRAM_BURST (1 << 4) 114 #define ASPEED_SDMC_VGA_APERTURE(x) ((x & 0x3) << 2) /* readonly */ 115 #define ASPEED_SDMC_VGA_8MB 0x0 116 #define ASPEED_SDMC_VGA_16MB 0x1 117 #define ASPEED_SDMC_VGA_32MB 0x2 118 #define ASPEED_SDMC_VGA_64MB 0x3 119 #define ASPEED_SDMC_DRAM_SIZE(x) (x & 0x3) 120 121 #define ASPEED_SDMC_READONLY_MASK \ 122 (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT | \ 123 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB)) 124 /* 125 * Configuration register Ox4 (for Aspeed AST2500 SOC and higher) 126 * 127 * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION 128 * should be set to 1 for the AST2500 SOC. 129 */ 130 #define ASPEED_SDMC_HW_VERSION(x) ((x & 0xf) << 28) /* readonly */ 131 #define ASPEED_SDMC_SW_VERSION ((x & 0xff) << 20) 132 #define ASPEED_SDMC_CACHE_INITIAL_DONE (1 << 19) /* readonly */ 133 #define ASPEED_SDMC_AST2500_RESERVED 0x7C000 /* 18:14 reserved */ 134 #define ASPEED_SDMC_CACHE_DDR4_CONF (1 << 13) 135 #define ASPEED_SDMC_CACHE_INITIAL (1 << 12) 136 #define ASPEED_SDMC_CACHE_RANGE_CTRL (1 << 11) 137 #define ASPEED_SDMC_CACHE_ENABLE (1 << 10) /* differs from AST2400 */ 138 #define ASPEED_SDMC_DRAM_TYPE (1 << 4) /* differs from AST2400 */ 139 140 #define ASPEED_SDMC_AST2500_READONLY_MASK \ 141 (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \ 142 ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \ 143 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB)) 144 145 /* 146 * Main Configuration register Ox10 (for Aspeed AST2700 SOC and higher) 147 * 148 */ 149 #define ASPEED_SDMC_AST2700_RESERVED 0xFFFF2082 /* 31:16, 13, 7, 1 */ 150 #define ASPEED_SDMC_AST2700_DATA_SCRAMBLE (1 << 8) 151 #define ASPEED_SDMC_AST2700_ECC_ENABLE (1 << 6) 152 #define ASPEED_SDMC_AST2700_PAGE_MATCHING_ENABLE (1 << 5) 153 #define ASPEED_SDMC_AST2700_DRAM_SIZE(x) ((x & 0x7) << 2) 154 155 #define ASPEED_SDMC_AST2700_READONLY_MASK \ 156 (ASPEED_SDMC_AST2700_RESERVED) 157 158 static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size) 159 { 160 AspeedSDMCState *s = ASPEED_SDMC(opaque); 161 162 addr >>= 2; 163 164 if (addr >= ARRAY_SIZE(s->regs)) { 165 qemu_log_mask(LOG_GUEST_ERROR, 166 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 167 __func__, addr * 4); 168 return 0; 169 } 170 171 trace_aspeed_sdmc_read(addr, s->regs[addr]); 172 return s->regs[addr]; 173 } 174 175 static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, 176 unsigned int size) 177 { 178 AspeedSDMCState *s = ASPEED_SDMC(opaque); 179 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 180 181 addr >>= 2; 182 183 if (addr >= ARRAY_SIZE(s->regs)) { 184 qemu_log_mask(LOG_GUEST_ERROR, 185 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 186 __func__, addr); 187 return; 188 } 189 190 trace_aspeed_sdmc_write(addr, data); 191 asc->write(s, addr, data); 192 } 193 194 static const MemoryRegionOps aspeed_sdmc_ops = { 195 .read = aspeed_sdmc_read, 196 .write = aspeed_sdmc_write, 197 .endianness = DEVICE_LITTLE_ENDIAN, 198 .valid.min_access_size = 4, 199 .valid.max_access_size = 4, 200 }; 201 202 static void aspeed_sdmc_reset(DeviceState *dev) 203 { 204 AspeedSDMCState *s = ASPEED_SDMC(dev); 205 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 206 207 memset(s->regs, 0, sizeof(s->regs)); 208 209 /* Set ram size bit and defaults values */ 210 s->regs[R_CONF] = asc->compute_conf(s, 0); 211 212 /* 213 * PHY status: 214 * - set phy status ok (set bit 1) 215 * - initial PVT calibration ok (clear bit 3) 216 * - runtime calibration ok (clear bit 5) 217 */ 218 s->regs[0x100] = BIT(1); 219 220 /* PHY eye window: set all as passing */ 221 s->regs[0x100 | (0x68 / 4)] = 0xff; 222 s->regs[0x100 | (0x7c / 4)] = 0xff; 223 s->regs[0x100 | (0x50 / 4)] = 0xfffffff; 224 } 225 226 static void aspeed_sdmc_get_ram_size(Object *obj, Visitor *v, const char *name, 227 void *opaque, Error **errp) 228 { 229 AspeedSDMCState *s = ASPEED_SDMC(obj); 230 int64_t value = s->ram_size; 231 232 visit_type_int(v, name, &value, errp); 233 } 234 235 static void aspeed_sdmc_set_ram_size(Object *obj, Visitor *v, const char *name, 236 void *opaque, Error **errp) 237 { 238 int i; 239 char *sz; 240 int64_t value; 241 AspeedSDMCState *s = ASPEED_SDMC(obj); 242 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 243 244 if (!visit_type_int(v, name, &value, errp)) { 245 return; 246 } 247 248 for (i = 0; asc->valid_ram_sizes[i]; i++) { 249 if (value == asc->valid_ram_sizes[i]) { 250 s->ram_size = value; 251 return; 252 } 253 } 254 255 sz = size_to_str(value); 256 error_setg(errp, "Invalid RAM size %s", sz); 257 g_free(sz); 258 } 259 260 static void aspeed_sdmc_initfn(Object *obj) 261 { 262 object_property_add(obj, "ram-size", "int", 263 aspeed_sdmc_get_ram_size, aspeed_sdmc_set_ram_size, 264 NULL, NULL); 265 } 266 267 static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) 268 { 269 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 270 AspeedSDMCState *s = ASPEED_SDMC(dev); 271 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 272 273 assert(asc->max_ram_size < 4 * GiB || asc->is_bus64bit); 274 275 if (!s->ram_size) { 276 error_setg(errp, "RAM size is not set"); 277 return; 278 } 279 280 s->max_ram_size = asc->max_ram_size; 281 282 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s, 283 TYPE_ASPEED_SDMC, 0x1000); 284 sysbus_init_mmio(sbd, &s->iomem); 285 } 286 287 static const VMStateDescription vmstate_aspeed_sdmc = { 288 .name = "aspeed.sdmc", 289 .version_id = 2, 290 .minimum_version_id = 2, 291 .fields = (const VMStateField[]) { 292 VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS), 293 VMSTATE_END_OF_LIST() 294 } 295 }; 296 297 static const Property aspeed_sdmc_properties[] = { 298 DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0), 299 DEFINE_PROP_BOOL("unlocked", AspeedSDMCState, unlocked, false), 300 }; 301 302 static void aspeed_sdmc_class_init(ObjectClass *klass, void *data) 303 { 304 DeviceClass *dc = DEVICE_CLASS(klass); 305 dc->realize = aspeed_sdmc_realize; 306 device_class_set_legacy_reset(dc, aspeed_sdmc_reset); 307 dc->desc = "ASPEED SDRAM Memory Controller"; 308 dc->vmsd = &vmstate_aspeed_sdmc; 309 device_class_set_props(dc, aspeed_sdmc_properties); 310 } 311 312 static const TypeInfo aspeed_sdmc_info = { 313 .name = TYPE_ASPEED_SDMC, 314 .parent = TYPE_SYS_BUS_DEVICE, 315 .instance_size = sizeof(AspeedSDMCState), 316 .instance_init = aspeed_sdmc_initfn, 317 .class_init = aspeed_sdmc_class_init, 318 .class_size = sizeof(AspeedSDMCClass), 319 .abstract = true, 320 }; 321 322 static int aspeed_sdmc_get_ram_bits(AspeedSDMCState *s) 323 { 324 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 325 int i; 326 327 /* 328 * The bitfield value encoding the RAM size is the index of the 329 * possible RAM size array 330 */ 331 for (i = 0; asc->valid_ram_sizes[i]; i++) { 332 if (s->ram_size == asc->valid_ram_sizes[i]) { 333 return i; 334 } 335 } 336 337 /* 338 * Invalid RAM sizes should have been excluded when setting the 339 * SoC RAM size. 340 */ 341 g_assert_not_reached(); 342 } 343 344 static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) 345 { 346 uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT | 347 ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s)); 348 349 /* Make sure readonly bits are kept */ 350 data &= ~ASPEED_SDMC_READONLY_MASK; 351 352 return data | fixed_conf; 353 } 354 355 static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg, 356 uint32_t data) 357 { 358 if (reg == R_PROT) { 359 s->regs[reg] = 360 (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED; 361 return; 362 } 363 364 if (!s->regs[R_PROT]) { 365 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__); 366 return; 367 } 368 369 switch (reg) { 370 case R_CONF: 371 data = aspeed_2400_sdmc_compute_conf(s, data); 372 break; 373 default: 374 break; 375 } 376 377 s->regs[reg] = data; 378 } 379 380 static const uint64_t 381 aspeed_2400_ram_sizes[] = { 64 * MiB, 128 * MiB, 256 * MiB, 512 * MiB, 0}; 382 383 static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data) 384 { 385 DeviceClass *dc = DEVICE_CLASS(klass); 386 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); 387 388 dc->desc = "ASPEED 2400 SDRAM Memory Controller"; 389 asc->max_ram_size = 512 * MiB; 390 asc->compute_conf = aspeed_2400_sdmc_compute_conf; 391 asc->write = aspeed_2400_sdmc_write; 392 asc->valid_ram_sizes = aspeed_2400_ram_sizes; 393 } 394 395 static const TypeInfo aspeed_2400_sdmc_info = { 396 .name = TYPE_ASPEED_2400_SDMC, 397 .parent = TYPE_ASPEED_SDMC, 398 .class_init = aspeed_2400_sdmc_class_init, 399 }; 400 401 static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) 402 { 403 uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) | 404 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | 405 ASPEED_SDMC_CACHE_INITIAL_DONE | 406 ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s)); 407 408 /* Make sure readonly bits are kept */ 409 data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; 410 411 return data | fixed_conf; 412 } 413 414 static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg, 415 uint32_t data) 416 { 417 if (reg == R_PROT) { 418 s->regs[reg] = 419 (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED; 420 return; 421 } 422 423 if (!s->regs[R_PROT]) { 424 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__); 425 return; 426 } 427 428 switch (reg) { 429 case R_CONF: 430 data = aspeed_2500_sdmc_compute_conf(s, data); 431 break; 432 case R_STATUS1: 433 /* Will never return 'busy' */ 434 data &= ~PHY_BUSY_STATE; 435 break; 436 case R_ECC_TEST_CTRL: 437 /* Always done, always happy */ 438 data |= ECC_TEST_FINISHED; 439 data &= ~ECC_TEST_FAIL; 440 break; 441 default: 442 break; 443 } 444 445 s->regs[reg] = data; 446 } 447 448 static const uint64_t 449 aspeed_2500_ram_sizes[] = { 128 * MiB, 256 * MiB, 512 * MiB, 1024 * MiB, 0}; 450 451 static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data) 452 { 453 DeviceClass *dc = DEVICE_CLASS(klass); 454 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); 455 456 dc->desc = "ASPEED 2500 SDRAM Memory Controller"; 457 asc->max_ram_size = 1 * GiB; 458 asc->compute_conf = aspeed_2500_sdmc_compute_conf; 459 asc->write = aspeed_2500_sdmc_write; 460 asc->valid_ram_sizes = aspeed_2500_ram_sizes; 461 } 462 463 static const TypeInfo aspeed_2500_sdmc_info = { 464 .name = TYPE_ASPEED_2500_SDMC, 465 .parent = TYPE_ASPEED_SDMC, 466 .class_init = aspeed_2500_sdmc_class_init, 467 }; 468 469 static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) 470 { 471 uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) | 472 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | 473 ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s)); 474 475 /* Make sure readonly bits are kept (use ast2500 mask) */ 476 data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; 477 478 return data | fixed_conf; 479 } 480 481 static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg, 482 uint32_t data) 483 { 484 /* Unprotected registers */ 485 switch (reg) { 486 case R_ISR: 487 case R_MCR6C: 488 case R_TEST_START_LEN: 489 case R_TEST_FAIL_DQ: 490 case R_TEST_INIT_VAL: 491 case R_DRAM_SW: 492 case R_DRAM_TIME: 493 case R_ECC_ERR_INJECT: 494 s->regs[reg] = data; 495 return; 496 } 497 498 if (s->regs[R_PROT] == PROT_HARDLOCKED) { 499 qemu_log_mask(LOG_GUEST_ERROR, 500 "%s: SDMC is locked until system reset!\n", 501 __func__); 502 return; 503 } 504 505 if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) { 506 qemu_log_mask(LOG_GUEST_ERROR, 507 "%s: SDMC is locked! (write to MCR%02x blocked)\n", 508 __func__, reg * 4); 509 return; 510 } 511 512 switch (reg) { 513 case R_PROT: 514 if (data == PROT_KEY_UNLOCK) { 515 data = PROT_UNLOCKED; 516 } else if (data == PROT_KEY_HARDLOCK) { 517 data = PROT_HARDLOCKED; 518 } else { 519 data = PROT_SOFTLOCKED; 520 } 521 break; 522 case R_CONF: 523 data = aspeed_2600_sdmc_compute_conf(s, data); 524 break; 525 case R_STATUS1: 526 /* Will never return 'busy'. 'lock status' is always set */ 527 data &= ~PHY_BUSY_STATE; 528 data |= PHY_PLL_LOCK_STATUS; 529 break; 530 case R_ECC_TEST_CTRL: 531 /* Always done, always happy */ 532 data |= ECC_TEST_FINISHED; 533 data &= ~ECC_TEST_FAIL; 534 break; 535 default: 536 break; 537 } 538 539 s->regs[reg] = data; 540 } 541 542 static const uint64_t 543 aspeed_2600_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 2048 * MiB, 0}; 544 545 static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data) 546 { 547 DeviceClass *dc = DEVICE_CLASS(klass); 548 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); 549 550 dc->desc = "ASPEED 2600 SDRAM Memory Controller"; 551 asc->max_ram_size = 2 * GiB; 552 asc->compute_conf = aspeed_2600_sdmc_compute_conf; 553 asc->write = aspeed_2600_sdmc_write; 554 asc->valid_ram_sizes = aspeed_2600_ram_sizes; 555 } 556 557 static const TypeInfo aspeed_2600_sdmc_info = { 558 .name = TYPE_ASPEED_2600_SDMC, 559 .parent = TYPE_ASPEED_SDMC, 560 .class_init = aspeed_2600_sdmc_class_init, 561 }; 562 563 static void aspeed_2700_sdmc_reset(DeviceState *dev) 564 { 565 AspeedSDMCState *s = ASPEED_SDMC(dev); 566 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 567 568 memset(s->regs, 0, sizeof(s->regs)); 569 570 /* Set ram size bit and defaults values */ 571 s->regs[R_MAIN_CONF] = asc->compute_conf(s, 0); 572 573 if (s->unlocked) { 574 s->regs[R_2700_PROT] = PROT_UNLOCKED; 575 } 576 } 577 578 static uint32_t aspeed_2700_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) 579 { 580 uint32_t fixed_conf = ASPEED_SDMC_AST2700_PAGE_MATCHING_ENABLE | 581 ASPEED_SDMC_AST2700_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s)); 582 583 /* Make sure readonly bits are kept */ 584 data &= ~ASPEED_SDMC_AST2700_READONLY_MASK; 585 586 return data | fixed_conf; 587 } 588 589 static void aspeed_2700_sdmc_write(AspeedSDMCState *s, uint32_t reg, 590 uint32_t data) 591 { 592 /* Unprotected registers */ 593 switch (reg) { 594 case R_INT_STATUS: 595 case R_INT_CLEAR: 596 case R_INT_MASK: 597 case R_ERR_STATUS: 598 case R_ECC_FAIL_STATUS: 599 case R_ECC_FAIL_ADDR: 600 case R_PROT_REGION_LOCK_STATUS: 601 case R_TEST_FAIL_ADDR: 602 case R_TEST_FAIL_D0: 603 case R_TEST_FAIL_D1: 604 case R_TEST_FAIL_D2: 605 case R_TEST_FAIL_D3: 606 case R_DBG_STATUS: 607 case R_PHY_INTERFACE_STATUS: 608 case R_GRAPHIC_MEM_BASE_ADDR: 609 case R_PORT0_INTERFACE_MONITOR0: 610 case R_PORT0_INTERFACE_MONITOR1: 611 case R_PORT0_INTERFACE_MONITOR2: 612 case R_PORT1_INTERFACE_MONITOR0: 613 case R_PORT1_INTERFACE_MONITOR1: 614 case R_PORT1_INTERFACE_MONITOR2: 615 case R_PORT2_INTERFACE_MONITOR0: 616 case R_PORT2_INTERFACE_MONITOR1: 617 case R_PORT2_INTERFACE_MONITOR2: 618 case R_PORT3_INTERFACE_MONITOR0: 619 case R_PORT3_INTERFACE_MONITOR1: 620 case R_PORT3_INTERFACE_MONITOR2: 621 case R_PORT4_INTERFACE_MONITOR0: 622 case R_PORT4_INTERFACE_MONITOR1: 623 case R_PORT4_INTERFACE_MONITOR2: 624 case R_PORT5_INTERFACE_MONITOR0: 625 case R_PORT5_INTERFACE_MONITOR1: 626 case R_PORT5_INTERFACE_MONITOR2: 627 s->regs[reg] = data; 628 return; 629 } 630 631 if (s->regs[R_2700_PROT] == PROT_HARDLOCKED) { 632 qemu_log_mask(LOG_GUEST_ERROR, 633 "%s: SDMC is locked until system reset!\n", 634 __func__); 635 return; 636 } 637 638 if (reg != R_2700_PROT && s->regs[R_2700_PROT] == PROT_SOFTLOCKED) { 639 qemu_log_mask(LOG_GUEST_ERROR, 640 "%s: SDMC is locked! (write to MCR%02x blocked)\n", 641 __func__, reg * 4); 642 return; 643 } 644 645 switch (reg) { 646 case R_2700_PROT: 647 if (data == PROT_2700_KEY_UNLOCK) { 648 data = PROT_UNLOCKED; 649 } else if (data == PROT_KEY_HARDLOCK) { 650 data = PROT_HARDLOCKED; 651 } else { 652 data = PROT_SOFTLOCKED; 653 } 654 break; 655 case R_MAIN_CONF: 656 data = aspeed_2700_sdmc_compute_conf(s, data); 657 break; 658 case R_MAIN_STATUS: 659 /* Will never return 'busy'. */ 660 data &= ~PHY_BUSY_STATE; 661 break; 662 default: 663 break; 664 } 665 666 s->regs[reg] = data; 667 } 668 669 static const uint64_t 670 aspeed_2700_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 671 2048 * MiB, 4096 * MiB, 8192 * MiB, 0}; 672 673 static void aspeed_2700_sdmc_class_init(ObjectClass *klass, void *data) 674 { 675 DeviceClass *dc = DEVICE_CLASS(klass); 676 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); 677 678 dc->desc = "ASPEED 2700 SDRAM Memory Controller"; 679 device_class_set_legacy_reset(dc, aspeed_2700_sdmc_reset); 680 681 asc->is_bus64bit = true; 682 asc->max_ram_size = 8 * GiB; 683 asc->compute_conf = aspeed_2700_sdmc_compute_conf; 684 asc->write = aspeed_2700_sdmc_write; 685 asc->valid_ram_sizes = aspeed_2700_ram_sizes; 686 } 687 688 static const TypeInfo aspeed_2700_sdmc_info = { 689 .name = TYPE_ASPEED_2700_SDMC, 690 .parent = TYPE_ASPEED_SDMC, 691 .class_init = aspeed_2700_sdmc_class_init, 692 }; 693 694 static void aspeed_sdmc_register_types(void) 695 { 696 type_register_static(&aspeed_sdmc_info); 697 type_register_static(&aspeed_2400_sdmc_info); 698 type_register_static(&aspeed_2500_sdmc_info); 699 type_register_static(&aspeed_2600_sdmc_info); 700 type_register_static(&aspeed_2700_sdmc_info); 701 } 702 703 type_init(aspeed_sdmc_register_types); 704