1 /* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "hw/misc/aspeed_scu.h" 14 #include "hw/qdev-properties.h" 15 #include "migration/vmstate.h" 16 #include "qapi/error.h" 17 #include "qapi/visitor.h" 18 #include "qemu/bitops.h" 19 #include "qemu/log.h" 20 #include "qemu/guest-random.h" 21 #include "qemu/module.h" 22 #include "trace.h" 23 24 #define TO_REG(offset) ((offset) >> 2) 25 26 #define PROT_KEY TO_REG(0x00) 27 #define SYS_RST_CTRL TO_REG(0x04) 28 #define CLK_SEL TO_REG(0x08) 29 #define CLK_STOP_CTRL TO_REG(0x0C) 30 #define FREQ_CNTR_CTRL TO_REG(0x10) 31 #define FREQ_CNTR_EVAL TO_REG(0x14) 32 #define IRQ_CTRL TO_REG(0x18) 33 #define D2PLL_PARAM TO_REG(0x1C) 34 #define MPLL_PARAM TO_REG(0x20) 35 #define HPLL_PARAM TO_REG(0x24) 36 #define FREQ_CNTR_RANGE TO_REG(0x28) 37 #define MISC_CTRL1 TO_REG(0x2C) 38 #define PCI_CTRL1 TO_REG(0x30) 39 #define PCI_CTRL2 TO_REG(0x34) 40 #define PCI_CTRL3 TO_REG(0x38) 41 #define SYS_RST_STATUS TO_REG(0x3C) 42 #define SOC_SCRATCH1 TO_REG(0x40) 43 #define SOC_SCRATCH2 TO_REG(0x44) 44 #define MAC_CLK_DELAY TO_REG(0x48) 45 #define MISC_CTRL2 TO_REG(0x4C) 46 #define VGA_SCRATCH1 TO_REG(0x50) 47 #define VGA_SCRATCH2 TO_REG(0x54) 48 #define VGA_SCRATCH3 TO_REG(0x58) 49 #define VGA_SCRATCH4 TO_REG(0x5C) 50 #define VGA_SCRATCH5 TO_REG(0x60) 51 #define VGA_SCRATCH6 TO_REG(0x64) 52 #define VGA_SCRATCH7 TO_REG(0x68) 53 #define VGA_SCRATCH8 TO_REG(0x6C) 54 #define HW_STRAP1 TO_REG(0x70) 55 #define RNG_CTRL TO_REG(0x74) 56 #define RNG_DATA TO_REG(0x78) 57 #define SILICON_REV TO_REG(0x7C) 58 #define PINMUX_CTRL1 TO_REG(0x80) 59 #define PINMUX_CTRL2 TO_REG(0x84) 60 #define PINMUX_CTRL3 TO_REG(0x88) 61 #define PINMUX_CTRL4 TO_REG(0x8C) 62 #define PINMUX_CTRL5 TO_REG(0x90) 63 #define PINMUX_CTRL6 TO_REG(0x94) 64 #define WDT_RST_CTRL TO_REG(0x9C) 65 #define PINMUX_CTRL7 TO_REG(0xA0) 66 #define PINMUX_CTRL8 TO_REG(0xA4) 67 #define PINMUX_CTRL9 TO_REG(0xA8) 68 #define WAKEUP_EN TO_REG(0xC0) 69 #define WAKEUP_CTRL TO_REG(0xC4) 70 #define HW_STRAP2 TO_REG(0xD0) 71 #define FREE_CNTR4 TO_REG(0xE0) 72 #define FREE_CNTR4_EXT TO_REG(0xE4) 73 #define CPU2_CTRL TO_REG(0x100) 74 #define CPU2_BASE_SEG1 TO_REG(0x104) 75 #define CPU2_BASE_SEG2 TO_REG(0x108) 76 #define CPU2_BASE_SEG3 TO_REG(0x10C) 77 #define CPU2_BASE_SEG4 TO_REG(0x110) 78 #define CPU2_BASE_SEG5 TO_REG(0x114) 79 #define CPU2_CACHE_CTRL TO_REG(0x118) 80 #define CHIP_ID0 TO_REG(0x150) 81 #define CHIP_ID1 TO_REG(0x154) 82 #define UART_HPLL_CLK TO_REG(0x160) 83 #define PCIE_CTRL TO_REG(0x180) 84 #define BMC_MMIO_CTRL TO_REG(0x184) 85 #define RELOC_DECODE_BASE1 TO_REG(0x188) 86 #define RELOC_DECODE_BASE2 TO_REG(0x18C) 87 #define MAILBOX_DECODE_BASE TO_REG(0x190) 88 #define SRAM_DECODE_BASE1 TO_REG(0x194) 89 #define SRAM_DECODE_BASE2 TO_REG(0x198) 90 #define BMC_REV TO_REG(0x19C) 91 #define BMC_DEV_ID TO_REG(0x1A4) 92 93 #define AST2600_PROT_KEY TO_REG(0x00) 94 #define AST2600_SILICON_REV TO_REG(0x04) 95 #define AST2600_SILICON_REV2 TO_REG(0x14) 96 #define AST2600_SYS_RST_CTRL TO_REG(0x40) 97 #define AST2600_SYS_RST_CTRL_CLR TO_REG(0x44) 98 #define AST2600_SYS_RST_CTRL2 TO_REG(0x50) 99 #define AST2600_SYS_RST_CTRL2_CLR TO_REG(0x54) 100 #define AST2600_CLK_STOP_CTRL TO_REG(0x80) 101 #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84) 102 #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90) 103 #define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94) 104 #define AST2600_DEBUG_CTRL TO_REG(0xC8) 105 #define AST2600_DEBUG_CTRL2 TO_REG(0xD8) 106 #define AST2600_SDRAM_HANDSHAKE TO_REG(0x100) 107 #define AST2600_HPLL_PARAM TO_REG(0x200) 108 #define AST2600_HPLL_EXT TO_REG(0x204) 109 #define AST2600_APLL_PARAM TO_REG(0x210) 110 #define AST2600_APLL_EXT TO_REG(0x214) 111 #define AST2600_MPLL_PARAM TO_REG(0x220) 112 #define AST2600_MPLL_EXT TO_REG(0x224) 113 #define AST2600_EPLL_PARAM TO_REG(0x240) 114 #define AST2600_EPLL_EXT TO_REG(0x244) 115 #define AST2600_DPLL_PARAM TO_REG(0x260) 116 #define AST2600_DPLL_EXT TO_REG(0x264) 117 #define AST2600_CLK_SEL TO_REG(0x300) 118 #define AST2600_CLK_SEL2 TO_REG(0x304) 119 #define AST2600_CLK_SEL3 TO_REG(0x308) 120 #define AST2600_CLK_SEL4 TO_REG(0x310) 121 #define AST2600_CLK_SEL5 TO_REG(0x314) 122 #define AST2600_UARTCLK TO_REG(0x338) 123 #define AST2600_HUARTCLK TO_REG(0x33C) 124 #define AST2600_HW_STRAP1 TO_REG(0x500) 125 #define AST2600_HW_STRAP1_CLR TO_REG(0x504) 126 #define AST2600_HW_STRAP1_PROT TO_REG(0x508) 127 #define AST2600_HW_STRAP2 TO_REG(0x510) 128 #define AST2600_HW_STRAP2_CLR TO_REG(0x514) 129 #define AST2600_HW_STRAP2_PROT TO_REG(0x518) 130 #define AST2600_RNG_CTRL TO_REG(0x524) 131 #define AST2600_RNG_DATA TO_REG(0x540) 132 #define AST2600_CHIP_ID0 TO_REG(0x5B0) 133 #define AST2600_CHIP_ID1 TO_REG(0x5B4) 134 135 #define AST2600_CLK TO_REG(0x40) 136 137 #define AST2700_SILICON_REV TO_REG(0x00) 138 #define AST2700_HW_STRAP1 TO_REG(0x10) 139 #define AST2700_HW_STRAP1_CLR TO_REG(0x14) 140 #define AST2700_HW_STRAP1_LOCK TO_REG(0x20) 141 #define AST2700_HW_STRAP1_SEC1 TO_REG(0x24) 142 #define AST2700_HW_STRAP1_SEC2 TO_REG(0x28) 143 #define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C) 144 145 #define AST2700_SCU_CLK_SEL_1 TO_REG(0x280) 146 #define AST2700_SCU_HPLL_PARAM TO_REG(0x300) 147 #define AST2700_SCU_HPLL_EXT_PARAM TO_REG(0x304) 148 #define AST2700_SCU_DPLL_PARAM TO_REG(0x308) 149 #define AST2700_SCU_DPLL_EXT_PARAM TO_REG(0x30c) 150 #define AST2700_SCU_MPLL_PARAM TO_REG(0x310) 151 #define AST2700_SCU_MPLL_EXT_PARAM TO_REG(0x314) 152 #define AST2700_SCU_D1CLK_PARAM TO_REG(0x320) 153 #define AST2700_SCU_D2CLK_PARAM TO_REG(0x330) 154 #define AST2700_SCU_CRT1CLK_PARAM TO_REG(0x340) 155 #define AST2700_SCU_CRT2CLK_PARAM TO_REG(0x350) 156 #define AST2700_SCU_MPHYCLK_PARAM TO_REG(0x360) 157 #define AST2700_SCU_FREQ_CNTR TO_REG(0x3b0) 158 #define AST2700_SCU_CPU_SCRATCH_0 TO_REG(0x780) 159 #define AST2700_SCU_CPU_SCRATCH_1 TO_REG(0x784) 160 #define AST2700_SCU_VGA_SCRATCH_0 TO_REG(0x900) 161 162 #define AST2700_SCUIO_CLK_STOP_CTL_1 TO_REG(0x240) 163 #define AST2700_SCUIO_CLK_STOP_CLR_1 TO_REG(0x244) 164 #define AST2700_SCUIO_CLK_STOP_CTL_2 TO_REG(0x260) 165 #define AST2700_SCUIO_CLK_STOP_CLR_2 TO_REG(0x264) 166 #define AST2700_SCUIO_CLK_SEL_1 TO_REG(0x280) 167 #define AST2700_SCUIO_CLK_SEL_2 TO_REG(0x284) 168 #define AST2700_SCUIO_HPLL_PARAM TO_REG(0x300) 169 #define AST2700_SCUIO_HPLL_EXT_PARAM TO_REG(0x304) 170 #define AST2700_SCUIO_APLL_PARAM TO_REG(0x310) 171 #define AST2700_SCUIO_APLL_EXT_PARAM TO_REG(0x314) 172 #define AST2700_SCUIO_DPLL_PARAM TO_REG(0x320) 173 #define AST2700_SCUIO_DPLL_EXT_PARAM TO_REG(0x324) 174 #define AST2700_SCUIO_DPLL_PARAM_READ TO_REG(0x328) 175 #define AST2700_SCUIO_DPLL_EXT_PARAM_READ TO_REG(0x32c) 176 #define AST2700_SCUIO_UARTCLK_GEN TO_REG(0x330) 177 #define AST2700_SCUIO_HUARTCLK_GEN TO_REG(0x334) 178 #define AST2700_SCUIO_CLK_DUTY_MEAS_RST TO_REG(0x388) 179 180 #define SCU_IO_REGION_SIZE 0x1000 181 182 static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = { 183 [SYS_RST_CTRL] = 0xFFCFFEDCU, 184 [CLK_SEL] = 0xF3F40000U, 185 [CLK_STOP_CTRL] = 0x19FC3E8BU, 186 [D2PLL_PARAM] = 0x00026108U, 187 [MPLL_PARAM] = 0x00030291U, 188 [HPLL_PARAM] = 0x00000291U, 189 [MISC_CTRL1] = 0x00000010U, 190 [PCI_CTRL1] = 0x20001A03U, 191 [PCI_CTRL2] = 0x20001A03U, 192 [PCI_CTRL3] = 0x04000030U, 193 [SYS_RST_STATUS] = 0x00000001U, 194 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */ 195 [MISC_CTRL2] = 0x00000023U, 196 [RNG_CTRL] = 0x0000000EU, 197 [PINMUX_CTRL2] = 0x0000F000U, 198 [PINMUX_CTRL3] = 0x01000000U, 199 [PINMUX_CTRL4] = 0x000000FFU, 200 [PINMUX_CTRL5] = 0x0000A000U, 201 [WDT_RST_CTRL] = 0x003FFFF3U, 202 [PINMUX_CTRL8] = 0xFFFF0000U, 203 [PINMUX_CTRL9] = 0x000FFFFFU, 204 [FREE_CNTR4] = 0x000000FFU, 205 [FREE_CNTR4_EXT] = 0x000000FFU, 206 [CPU2_BASE_SEG1] = 0x80000000U, 207 [CPU2_BASE_SEG4] = 0x1E600000U, 208 [CPU2_BASE_SEG5] = 0xC0000000U, 209 [UART_HPLL_CLK] = 0x00001903U, 210 [PCIE_CTRL] = 0x0000007BU, 211 [BMC_DEV_ID] = 0x00002402U 212 }; 213 214 /* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */ 215 /* AST2500 revision A1 */ 216 217 static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = { 218 [SYS_RST_CTRL] = 0xFFCFFEDCU, 219 [CLK_SEL] = 0xF3F40000U, 220 [CLK_STOP_CTRL] = 0x19FC3E8BU, 221 [D2PLL_PARAM] = 0x00026108U, 222 [MPLL_PARAM] = 0x00030291U, 223 [HPLL_PARAM] = 0x93000400U, 224 [MISC_CTRL1] = 0x00000010U, 225 [PCI_CTRL1] = 0x20001A03U, 226 [PCI_CTRL2] = 0x20001A03U, 227 [PCI_CTRL3] = 0x04000030U, 228 [SYS_RST_STATUS] = 0x00000001U, 229 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */ 230 [MISC_CTRL2] = 0x00000023U, 231 [RNG_CTRL] = 0x0000000EU, 232 [PINMUX_CTRL2] = 0x0000F000U, 233 [PINMUX_CTRL3] = 0x03000000U, 234 [PINMUX_CTRL4] = 0x00000000U, 235 [PINMUX_CTRL5] = 0x0000A000U, 236 [WDT_RST_CTRL] = 0x023FFFF3U, 237 [PINMUX_CTRL8] = 0xFFFF0000U, 238 [PINMUX_CTRL9] = 0x000FFFFFU, 239 [FREE_CNTR4] = 0x000000FFU, 240 [FREE_CNTR4_EXT] = 0x000000FFU, 241 [CPU2_BASE_SEG1] = 0x80000000U, 242 [CPU2_BASE_SEG4] = 0x1E600000U, 243 [CPU2_BASE_SEG5] = 0xC0000000U, 244 [CHIP_ID0] = 0x1234ABCDU, 245 [CHIP_ID1] = 0x88884444U, 246 [UART_HPLL_CLK] = 0x00001903U, 247 [PCIE_CTRL] = 0x0000007BU, 248 [BMC_DEV_ID] = 0x00002402U 249 }; 250 251 static uint32_t aspeed_scu_get_random(void) 252 { 253 uint32_t num; 254 qemu_guest_getrandom_nofail(&num, sizeof(num)); 255 return num; 256 } 257 258 uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s) 259 { 260 return ASPEED_SCU_GET_CLASS(s)->get_apb(s); 261 } 262 263 static uint32_t aspeed_2400_scu_get_apb_freq(AspeedSCUState *s) 264 { 265 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s); 266 uint32_t hpll = asc->calc_hpll(s, s->regs[HPLL_PARAM]); 267 268 return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1) 269 / asc->apb_divider; 270 } 271 272 static uint32_t aspeed_2600_scu_get_apb_freq(AspeedSCUState *s) 273 { 274 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s); 275 uint32_t hpll = asc->calc_hpll(s, s->regs[AST2600_HPLL_PARAM]); 276 277 return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[AST2600_CLK_SEL]) + 1) 278 / asc->apb_divider; 279 } 280 281 static uint32_t aspeed_1030_scu_get_apb_freq(AspeedSCUState *s) 282 { 283 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s); 284 uint32_t hpll = asc->calc_hpll(s, s->regs[AST2600_HPLL_PARAM]); 285 286 return hpll / (SCU_AST1030_CLK_GET_PCLK_DIV(s->regs[AST2600_CLK_SEL4]) + 1) 287 / asc->apb_divider; 288 } 289 290 static uint32_t aspeed_2700_scu_get_apb_freq(AspeedSCUState *s) 291 { 292 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s); 293 uint32_t hpll = asc->calc_hpll(s, s->regs[AST2700_SCU_HPLL_PARAM]); 294 295 return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[AST2700_SCU_CLK_SEL_1]) + 1) 296 / asc->apb_divider; 297 } 298 299 static uint32_t aspeed_2700_scuio_get_apb_freq(AspeedSCUState *s) 300 { 301 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s); 302 uint32_t hpll = asc->calc_hpll(s, s->regs[AST2700_SCUIO_HPLL_PARAM]); 303 304 return hpll / 305 (SCUIO_AST2700_CLK_GET_PCLK_DIV(s->regs[AST2700_SCUIO_CLK_SEL_1]) + 1) 306 / asc->apb_divider; 307 } 308 309 static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size) 310 { 311 AspeedSCUState *s = ASPEED_SCU(opaque); 312 int reg = TO_REG(offset); 313 314 if (reg >= ASPEED_SCU_NR_REGS) { 315 qemu_log_mask(LOG_GUEST_ERROR, 316 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 317 __func__, offset); 318 return 0; 319 } 320 321 switch (reg) { 322 case RNG_DATA: 323 /* 324 * On hardware, RNG_DATA works regardless of 325 * the state of the enable bit in RNG_CTRL 326 */ 327 s->regs[RNG_DATA] = aspeed_scu_get_random(); 328 break; 329 case WAKEUP_EN: 330 qemu_log_mask(LOG_GUEST_ERROR, 331 "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n", 332 __func__, offset); 333 break; 334 } 335 336 trace_aspeed_scu_read(offset, size, s->regs[reg]); 337 return s->regs[reg]; 338 } 339 340 static void aspeed_ast2400_scu_write(void *opaque, hwaddr offset, 341 uint64_t data, unsigned size) 342 { 343 AspeedSCUState *s = ASPEED_SCU(opaque); 344 int reg = TO_REG(offset); 345 346 if (reg >= ASPEED_SCU_NR_REGS) { 347 qemu_log_mask(LOG_GUEST_ERROR, 348 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 349 __func__, offset); 350 return; 351 } 352 353 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 && 354 !s->regs[PROT_KEY]) { 355 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); 356 } 357 358 trace_aspeed_scu_write(offset, size, data); 359 360 switch (reg) { 361 case PROT_KEY: 362 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; 363 return; 364 case SILICON_REV: 365 case FREQ_CNTR_EVAL: 366 case VGA_SCRATCH1 ... VGA_SCRATCH8: 367 case RNG_DATA: 368 case FREE_CNTR4: 369 case FREE_CNTR4_EXT: 370 qemu_log_mask(LOG_GUEST_ERROR, 371 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", 372 __func__, offset); 373 return; 374 } 375 376 s->regs[reg] = data; 377 } 378 379 static void aspeed_ast2500_scu_write(void *opaque, hwaddr offset, 380 uint64_t data, unsigned size) 381 { 382 AspeedSCUState *s = ASPEED_SCU(opaque); 383 int reg = TO_REG(offset); 384 385 if (reg >= ASPEED_SCU_NR_REGS) { 386 qemu_log_mask(LOG_GUEST_ERROR, 387 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 388 __func__, offset); 389 return; 390 } 391 392 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 && 393 !s->regs[PROT_KEY]) { 394 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); 395 return; 396 } 397 398 trace_aspeed_scu_write(offset, size, data); 399 400 switch (reg) { 401 case PROT_KEY: 402 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; 403 return; 404 case HW_STRAP1: 405 s->regs[HW_STRAP1] |= data; 406 return; 407 case SILICON_REV: 408 s->regs[HW_STRAP1] &= ~data; 409 return; 410 case FREQ_CNTR_EVAL: 411 case VGA_SCRATCH1 ... VGA_SCRATCH8: 412 case RNG_DATA: 413 case FREE_CNTR4: 414 case FREE_CNTR4_EXT: 415 case CHIP_ID0: 416 case CHIP_ID1: 417 qemu_log_mask(LOG_GUEST_ERROR, 418 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", 419 __func__, offset); 420 return; 421 } 422 423 s->regs[reg] = data; 424 } 425 426 static const MemoryRegionOps aspeed_ast2400_scu_ops = { 427 .read = aspeed_scu_read, 428 .write = aspeed_ast2400_scu_write, 429 .endianness = DEVICE_LITTLE_ENDIAN, 430 .valid = { 431 .min_access_size = 1, 432 .max_access_size = 4, 433 }, 434 }; 435 436 static const MemoryRegionOps aspeed_ast2500_scu_ops = { 437 .read = aspeed_scu_read, 438 .write = aspeed_ast2500_scu_write, 439 .endianness = DEVICE_LITTLE_ENDIAN, 440 .valid.min_access_size = 4, 441 .valid.max_access_size = 4, 442 .valid.unaligned = false, 443 }; 444 445 static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s) 446 { 447 if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN || 448 ASPEED_SCU_GET_CLASS(s)->clkin_25Mhz) { 449 return 25000000; 450 } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) { 451 return 48000000; 452 } else { 453 return 24000000; 454 } 455 } 456 457 /* 458 * Strapped frequencies for the AST2400 in MHz. They depend on the 459 * clkin frequency. 460 */ 461 static const uint32_t hpll_ast2400_freqs[][4] = { 462 { 384, 360, 336, 408 }, /* 24MHz or 48MHz */ 463 { 400, 375, 350, 425 }, /* 25MHz */ 464 }; 465 466 static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg) 467 { 468 uint8_t freq_select; 469 bool clk_25m_in; 470 uint32_t clkin = aspeed_scu_get_clkin(s); 471 472 if (hpll_reg & SCU_AST2400_H_PLL_OFF) { 473 return 0; 474 } 475 476 if (hpll_reg & SCU_AST2400_H_PLL_PROGRAMMED) { 477 uint32_t multiplier = 1; 478 479 if (!(hpll_reg & SCU_AST2400_H_PLL_BYPASS_EN)) { 480 uint32_t n = (hpll_reg >> 5) & 0x3f; 481 uint32_t od = (hpll_reg >> 4) & 0x1; 482 uint32_t d = hpll_reg & 0xf; 483 484 multiplier = (2 - od) * ((n + 2) / (d + 1)); 485 } 486 487 return clkin * multiplier; 488 } 489 490 /* HW strapping */ 491 clk_25m_in = !!(s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN); 492 freq_select = SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s->hw_strap1); 493 494 return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000; 495 } 496 497 static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg) 498 { 499 uint32_t multiplier = 1; 500 uint32_t clkin = aspeed_scu_get_clkin(s); 501 502 if (hpll_reg & SCU_H_PLL_OFF) { 503 return 0; 504 } 505 506 if (!(hpll_reg & SCU_H_PLL_BYPASS_EN)) { 507 uint32_t p = (hpll_reg >> 13) & 0x3f; 508 uint32_t m = (hpll_reg >> 5) & 0xff; 509 uint32_t n = hpll_reg & 0x1f; 510 511 multiplier = ((m + 1) / (n + 1)) / (p + 1); 512 } 513 514 return clkin * multiplier; 515 } 516 517 static uint32_t aspeed_2600_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg) 518 { 519 uint32_t multiplier = 1; 520 uint32_t clkin = aspeed_scu_get_clkin(s); 521 522 if (hpll_reg & SCU_AST2600_H_PLL_OFF) { 523 return 0; 524 } 525 526 if (!(hpll_reg & SCU_AST2600_H_PLL_BYPASS_EN)) { 527 uint32_t p = (hpll_reg >> 19) & 0xf; 528 uint32_t n = (hpll_reg >> 13) & 0x3f; 529 uint32_t m = hpll_reg & 0x1fff; 530 531 multiplier = ((m + 1) / (n + 1)) / (p + 1); 532 } 533 534 return clkin * multiplier; 535 } 536 537 static void aspeed_scu_reset(DeviceState *dev) 538 { 539 AspeedSCUState *s = ASPEED_SCU(dev); 540 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); 541 542 memcpy(s->regs, asc->resets, asc->nr_regs * 4); 543 s->regs[SILICON_REV] = s->silicon_rev; 544 s->regs[HW_STRAP1] = s->hw_strap1; 545 s->regs[HW_STRAP2] = s->hw_strap2; 546 s->regs[PROT_KEY] = s->hw_prot_key; 547 } 548 549 static uint32_t aspeed_silicon_revs[] = { 550 AST2400_A0_SILICON_REV, 551 AST2400_A1_SILICON_REV, 552 AST2500_A0_SILICON_REV, 553 AST2500_A1_SILICON_REV, 554 AST2600_A0_SILICON_REV, 555 AST2600_A1_SILICON_REV, 556 AST2600_A2_SILICON_REV, 557 AST2600_A3_SILICON_REV, 558 AST1030_A0_SILICON_REV, 559 AST1030_A1_SILICON_REV, 560 AST2700_A0_SILICON_REV, 561 AST2720_A0_SILICON_REV, 562 AST2750_A0_SILICON_REV, 563 AST2700_A1_SILICON_REV, 564 AST2750_A1_SILICON_REV, 565 }; 566 567 bool is_supported_silicon_rev(uint32_t silicon_rev) 568 { 569 int i; 570 571 for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) { 572 if (silicon_rev == aspeed_silicon_revs[i]) { 573 return true; 574 } 575 } 576 577 return false; 578 } 579 580 static void aspeed_scu_realize(DeviceState *dev, Error **errp) 581 { 582 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 583 AspeedSCUState *s = ASPEED_SCU(dev); 584 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); 585 586 if (!is_supported_silicon_rev(s->silicon_rev)) { 587 error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, 588 s->silicon_rev); 589 return; 590 } 591 592 memory_region_init_io(&s->iomem, OBJECT(s), asc->ops, s, 593 TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE); 594 595 sysbus_init_mmio(sbd, &s->iomem); 596 } 597 598 static const VMStateDescription vmstate_aspeed_scu = { 599 .name = "aspeed.scu", 600 .version_id = 2, 601 .minimum_version_id = 2, 602 .fields = (const VMStateField[]) { 603 VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_AST2600_SCU_NR_REGS), 604 VMSTATE_END_OF_LIST() 605 } 606 }; 607 608 static const Property aspeed_scu_properties[] = { 609 DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0), 610 DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0), 611 DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0), 612 DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0), 613 }; 614 615 static void aspeed_scu_class_init(ObjectClass *klass, void *data) 616 { 617 DeviceClass *dc = DEVICE_CLASS(klass); 618 dc->realize = aspeed_scu_realize; 619 device_class_set_legacy_reset(dc, aspeed_scu_reset); 620 dc->desc = "ASPEED System Control Unit"; 621 dc->vmsd = &vmstate_aspeed_scu; 622 device_class_set_props(dc, aspeed_scu_properties); 623 } 624 625 static const TypeInfo aspeed_scu_info = { 626 .name = TYPE_ASPEED_SCU, 627 .parent = TYPE_SYS_BUS_DEVICE, 628 .instance_size = sizeof(AspeedSCUState), 629 .class_init = aspeed_scu_class_init, 630 .class_size = sizeof(AspeedSCUClass), 631 .abstract = true, 632 }; 633 634 static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data) 635 { 636 DeviceClass *dc = DEVICE_CLASS(klass); 637 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); 638 639 dc->desc = "ASPEED 2400 System Control Unit"; 640 asc->resets = ast2400_a0_resets; 641 asc->calc_hpll = aspeed_2400_scu_calc_hpll; 642 asc->get_apb = aspeed_2400_scu_get_apb_freq; 643 asc->apb_divider = 2; 644 asc->nr_regs = ASPEED_SCU_NR_REGS; 645 asc->clkin_25Mhz = false; 646 asc->ops = &aspeed_ast2400_scu_ops; 647 } 648 649 static const TypeInfo aspeed_2400_scu_info = { 650 .name = TYPE_ASPEED_2400_SCU, 651 .parent = TYPE_ASPEED_SCU, 652 .instance_size = sizeof(AspeedSCUState), 653 .class_init = aspeed_2400_scu_class_init, 654 }; 655 656 static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data) 657 { 658 DeviceClass *dc = DEVICE_CLASS(klass); 659 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); 660 661 dc->desc = "ASPEED 2500 System Control Unit"; 662 asc->resets = ast2500_a1_resets; 663 asc->calc_hpll = aspeed_2500_scu_calc_hpll; 664 asc->get_apb = aspeed_2400_scu_get_apb_freq; 665 asc->apb_divider = 4; 666 asc->nr_regs = ASPEED_SCU_NR_REGS; 667 asc->clkin_25Mhz = false; 668 asc->ops = &aspeed_ast2500_scu_ops; 669 } 670 671 static const TypeInfo aspeed_2500_scu_info = { 672 .name = TYPE_ASPEED_2500_SCU, 673 .parent = TYPE_ASPEED_SCU, 674 .instance_size = sizeof(AspeedSCUState), 675 .class_init = aspeed_2500_scu_class_init, 676 }; 677 678 static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset, 679 unsigned size) 680 { 681 AspeedSCUState *s = ASPEED_SCU(opaque); 682 int reg = TO_REG(offset); 683 684 if (reg >= ASPEED_AST2600_SCU_NR_REGS) { 685 qemu_log_mask(LOG_GUEST_ERROR, 686 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 687 __func__, offset); 688 return 0; 689 } 690 691 switch (reg) { 692 case AST2600_HPLL_EXT: 693 case AST2600_EPLL_EXT: 694 case AST2600_MPLL_EXT: 695 /* PLLs are always "locked" */ 696 return s->regs[reg] | BIT(31); 697 case AST2600_RNG_DATA: 698 /* 699 * On hardware, RNG_DATA works regardless of the state of the 700 * enable bit in RNG_CTRL 701 * 702 * TODO: Check this is true for ast2600 703 */ 704 s->regs[AST2600_RNG_DATA] = aspeed_scu_get_random(); 705 break; 706 } 707 708 trace_aspeed_scu_read(offset, size, s->regs[reg]); 709 return s->regs[reg]; 710 } 711 712 static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, 713 uint64_t data64, unsigned size) 714 { 715 AspeedSCUState *s = ASPEED_SCU(opaque); 716 int reg = TO_REG(offset); 717 /* Truncate here so bitwise operations below behave as expected */ 718 uint32_t data = data64; 719 720 if (reg >= ASPEED_AST2600_SCU_NR_REGS) { 721 qemu_log_mask(LOG_GUEST_ERROR, 722 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 723 __func__, offset); 724 return; 725 } 726 727 if (reg > PROT_KEY && !s->regs[PROT_KEY]) { 728 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); 729 } 730 731 trace_aspeed_scu_write(offset, size, data); 732 733 switch (reg) { 734 case AST2600_PROT_KEY: 735 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; 736 return; 737 case AST2600_HW_STRAP1: 738 case AST2600_HW_STRAP2: 739 if (s->regs[reg + 2]) { 740 return; 741 } 742 /* fall through */ 743 case AST2600_SYS_RST_CTRL: 744 case AST2600_SYS_RST_CTRL2: 745 case AST2600_CLK_STOP_CTRL: 746 case AST2600_CLK_STOP_CTRL2: 747 /* W1S (Write 1 to set) registers */ 748 s->regs[reg] |= data; 749 return; 750 case AST2600_SYS_RST_CTRL_CLR: 751 case AST2600_SYS_RST_CTRL2_CLR: 752 case AST2600_CLK_STOP_CTRL_CLR: 753 case AST2600_CLK_STOP_CTRL2_CLR: 754 case AST2600_HW_STRAP1_CLR: 755 case AST2600_HW_STRAP2_CLR: 756 /* 757 * W1C (Write 1 to clear) registers are offset by one address from 758 * the data register 759 */ 760 s->regs[reg - 1] &= ~data; 761 return; 762 763 case AST2600_RNG_DATA: 764 case AST2600_SILICON_REV: 765 case AST2600_SILICON_REV2: 766 case AST2600_CHIP_ID0: 767 case AST2600_CHIP_ID1: 768 /* Add read only registers here */ 769 qemu_log_mask(LOG_GUEST_ERROR, 770 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", 771 __func__, offset); 772 return; 773 } 774 775 s->regs[reg] = data; 776 } 777 778 static const MemoryRegionOps aspeed_ast2600_scu_ops = { 779 .read = aspeed_ast2600_scu_read, 780 .write = aspeed_ast2600_scu_write, 781 .endianness = DEVICE_LITTLE_ENDIAN, 782 .valid.min_access_size = 4, 783 .valid.max_access_size = 4, 784 .valid.unaligned = false, 785 }; 786 787 static const uint32_t ast2600_a3_resets[ASPEED_AST2600_SCU_NR_REGS] = { 788 [AST2600_SYS_RST_CTRL] = 0xF7C3FED8, 789 [AST2600_SYS_RST_CTRL2] = 0x0DFFFFFC, 790 [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A, 791 [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, 792 [AST2600_DEBUG_CTRL] = 0x00000FFF, 793 [AST2600_DEBUG_CTRL2] = 0x000000FF, 794 [AST2600_SDRAM_HANDSHAKE] = 0x00000000, 795 [AST2600_HPLL_PARAM] = 0x1000408F, 796 [AST2600_APLL_PARAM] = 0x1000405F, 797 [AST2600_MPLL_PARAM] = 0x1008405F, 798 [AST2600_EPLL_PARAM] = 0x1004077F, 799 [AST2600_DPLL_PARAM] = 0x1078405F, 800 [AST2600_CLK_SEL] = 0xF3940000, 801 [AST2600_CLK_SEL2] = 0x00700000, 802 [AST2600_CLK_SEL3] = 0x00000000, 803 [AST2600_CLK_SEL4] = 0xF3F40000, 804 [AST2600_CLK_SEL5] = 0x30000000, 805 [AST2600_UARTCLK] = 0x00014506, 806 [AST2600_HUARTCLK] = 0x000145C0, 807 [AST2600_CHIP_ID0] = 0x1234ABCD, 808 [AST2600_CHIP_ID1] = 0x88884444, 809 }; 810 811 static void aspeed_ast2600_scu_reset(DeviceState *dev) 812 { 813 AspeedSCUState *s = ASPEED_SCU(dev); 814 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); 815 816 memcpy(s->regs, asc->resets, asc->nr_regs * 4); 817 818 /* 819 * A0 reports A0 in _REV, but subsequent revisions report A1 regardless 820 * of actual revision. QEMU and Linux only support A1 onwards so this is 821 * sufficient. 822 */ 823 s->regs[AST2600_SILICON_REV] = AST2600_A3_SILICON_REV; 824 s->regs[AST2600_SILICON_REV2] = s->silicon_rev; 825 s->regs[AST2600_HW_STRAP1] = s->hw_strap1; 826 s->regs[AST2600_HW_STRAP2] = s->hw_strap2; 827 s->regs[PROT_KEY] = s->hw_prot_key; 828 } 829 830 static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data) 831 { 832 DeviceClass *dc = DEVICE_CLASS(klass); 833 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); 834 835 dc->desc = "ASPEED 2600 System Control Unit"; 836 device_class_set_legacy_reset(dc, aspeed_ast2600_scu_reset); 837 asc->resets = ast2600_a3_resets; 838 asc->calc_hpll = aspeed_2600_scu_calc_hpll; 839 asc->get_apb = aspeed_2600_scu_get_apb_freq; 840 asc->apb_divider = 4; 841 asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS; 842 asc->clkin_25Mhz = true; 843 asc->ops = &aspeed_ast2600_scu_ops; 844 } 845 846 static const TypeInfo aspeed_2600_scu_info = { 847 .name = TYPE_ASPEED_2600_SCU, 848 .parent = TYPE_ASPEED_SCU, 849 .instance_size = sizeof(AspeedSCUState), 850 .class_init = aspeed_2600_scu_class_init, 851 }; 852 853 static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset, 854 unsigned size) 855 { 856 AspeedSCUState *s = ASPEED_SCU(opaque); 857 int reg = TO_REG(offset); 858 859 if (reg >= ASPEED_AST2700_SCU_NR_REGS) { 860 qemu_log_mask(LOG_GUEST_ERROR, 861 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 862 __func__, offset); 863 return 0; 864 } 865 866 switch (reg) { 867 default: 868 qemu_log_mask(LOG_GUEST_ERROR, 869 "%s: Unhandled read at offset 0x%" HWADDR_PRIx "\n", 870 __func__, offset); 871 } 872 873 trace_aspeed_ast2700_scu_read(offset, size, s->regs[reg]); 874 return s->regs[reg]; 875 } 876 877 static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset, 878 uint64_t data64, unsigned size) 879 { 880 AspeedSCUState *s = ASPEED_SCU(opaque); 881 int reg = TO_REG(offset); 882 /* Truncate here so bitwise operations below behave as expected */ 883 uint32_t data = data64; 884 885 if (reg >= ASPEED_AST2700_SCU_NR_REGS) { 886 qemu_log_mask(LOG_GUEST_ERROR, 887 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 888 __func__, offset); 889 return; 890 } 891 892 trace_aspeed_ast2700_scu_write(offset, size, data); 893 894 switch (reg) { 895 default: 896 qemu_log_mask(LOG_GUEST_ERROR, 897 "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n", 898 __func__, offset); 899 break; 900 } 901 902 s->regs[reg] = data; 903 } 904 905 static const MemoryRegionOps aspeed_ast2700_scu_ops = { 906 .read = aspeed_ast2700_scu_read, 907 .write = aspeed_ast2700_scu_write, 908 .endianness = DEVICE_LITTLE_ENDIAN, 909 .valid.min_access_size = 1, 910 .valid.max_access_size = 8, 911 .valid.unaligned = false, 912 }; 913 914 static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = { 915 [AST2700_HW_STRAP1_CLR] = 0xFFF0FFF0, 916 [AST2700_HW_STRAP1_LOCK] = 0x00000FFF, 917 [AST2700_HW_STRAP1_SEC1] = 0x000000FF, 918 [AST2700_HW_STRAP1_SEC2] = 0x00000000, 919 [AST2700_HW_STRAP1_SEC3] = 0x1000408F, 920 [AST2700_SCU_HPLL_PARAM] = 0x0000009f, 921 [AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f, 922 [AST2700_SCU_DPLL_PARAM] = 0x0080009f, 923 [AST2700_SCU_DPLL_EXT_PARAM] = 0x8000004f, 924 [AST2700_SCU_MPLL_PARAM] = 0x00000040, 925 [AST2700_SCU_MPLL_EXT_PARAM] = 0x80000000, 926 [AST2700_SCU_D1CLK_PARAM] = 0x00050002, 927 [AST2700_SCU_D2CLK_PARAM] = 0x00050002, 928 [AST2700_SCU_CRT1CLK_PARAM] = 0x00050002, 929 [AST2700_SCU_CRT2CLK_PARAM] = 0x00050002, 930 [AST2700_SCU_MPHYCLK_PARAM] = 0x0000004c, 931 [AST2700_SCU_FREQ_CNTR] = 0x000375eb, 932 [AST2700_SCU_CPU_SCRATCH_0] = 0x00000000, 933 [AST2700_SCU_CPU_SCRATCH_1] = 0x00000004, 934 [AST2700_SCU_VGA_SCRATCH_0] = 0x00000040, 935 }; 936 937 static void aspeed_ast2700_scu_reset(DeviceState *dev) 938 { 939 AspeedSCUState *s = ASPEED_SCU(dev); 940 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); 941 942 memcpy(s->regs, asc->resets, asc->nr_regs * 4); 943 s->regs[AST2700_SILICON_REV] = s->silicon_rev; 944 s->regs[AST2700_HW_STRAP1] = s->hw_strap1; 945 } 946 947 static void aspeed_2700_scu_class_init(ObjectClass *klass, void *data) 948 { 949 DeviceClass *dc = DEVICE_CLASS(klass); 950 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); 951 952 dc->desc = "ASPEED 2700 System Control Unit"; 953 device_class_set_legacy_reset(dc, aspeed_ast2700_scu_reset); 954 asc->resets = ast2700_a0_resets; 955 asc->calc_hpll = aspeed_2600_scu_calc_hpll; 956 asc->get_apb = aspeed_2700_scu_get_apb_freq; 957 asc->apb_divider = 4; 958 asc->nr_regs = ASPEED_AST2700_SCU_NR_REGS; 959 asc->clkin_25Mhz = true; 960 asc->ops = &aspeed_ast2700_scu_ops; 961 } 962 963 static uint64_t aspeed_ast2700_scuio_read(void *opaque, hwaddr offset, 964 unsigned size) 965 { 966 AspeedSCUState *s = ASPEED_SCU(opaque); 967 int reg = TO_REG(offset); 968 if (reg >= ASPEED_AST2700_SCU_NR_REGS) { 969 qemu_log_mask(LOG_GUEST_ERROR, 970 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 971 __func__, offset); 972 return 0; 973 } 974 975 switch (reg) { 976 default: 977 qemu_log_mask(LOG_GUEST_ERROR, 978 "%s: Unhandled read at offset 0x%" HWADDR_PRIx "\n", 979 __func__, offset); 980 } 981 982 trace_aspeed_ast2700_scuio_read(offset, size, s->regs[reg]); 983 return s->regs[reg]; 984 } 985 986 static void aspeed_ast2700_scuio_write(void *opaque, hwaddr offset, 987 uint64_t data64, unsigned size) 988 { 989 AspeedSCUState *s = ASPEED_SCU(opaque); 990 int reg = TO_REG(offset); 991 /* Truncate here so bitwise operations below behave as expected */ 992 uint32_t data = data64; 993 bool updated = false; 994 995 if (reg >= ASPEED_AST2700_SCU_NR_REGS) { 996 qemu_log_mask(LOG_GUEST_ERROR, 997 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 998 __func__, offset); 999 return; 1000 } 1001 1002 trace_aspeed_ast2700_scuio_write(offset, size, data); 1003 1004 switch (reg) { 1005 case AST2700_SCUIO_CLK_STOP_CTL_1: 1006 case AST2700_SCUIO_CLK_STOP_CTL_2: 1007 s->regs[reg] |= data; 1008 updated = true; 1009 break; 1010 case AST2700_SCUIO_CLK_STOP_CLR_1: 1011 case AST2700_SCUIO_CLK_STOP_CLR_2: 1012 s->regs[reg - 1] ^= data; 1013 updated = true; 1014 break; 1015 default: 1016 qemu_log_mask(LOG_GUEST_ERROR, 1017 "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n", 1018 __func__, offset); 1019 break; 1020 } 1021 1022 if (!updated) { 1023 s->regs[reg] = data; 1024 } 1025 } 1026 1027 static const MemoryRegionOps aspeed_ast2700_scuio_ops = { 1028 .read = aspeed_ast2700_scuio_read, 1029 .write = aspeed_ast2700_scuio_write, 1030 .endianness = DEVICE_LITTLE_ENDIAN, 1031 .valid.min_access_size = 1, 1032 .valid.max_access_size = 8, 1033 .valid.unaligned = false, 1034 }; 1035 1036 static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] = { 1037 [AST2700_HW_STRAP1_CLR] = 0xFFF0FFF0, 1038 [AST2700_HW_STRAP1_LOCK] = 0x00000FFF, 1039 [AST2700_HW_STRAP1_SEC1] = 0x000000FF, 1040 [AST2700_HW_STRAP1_SEC2] = 0x00000000, 1041 [AST2700_HW_STRAP1_SEC3] = 0x1000408F, 1042 [AST2700_SCUIO_CLK_STOP_CTL_1] = 0xffff8400, 1043 [AST2700_SCUIO_CLK_STOP_CTL_2] = 0x00005f30, 1044 [AST2700_SCUIO_CLK_SEL_1] = 0x86900000, 1045 [AST2700_SCUIO_CLK_SEL_2] = 0x00400000, 1046 [AST2700_SCUIO_HPLL_PARAM] = 0x10000027, 1047 [AST2700_SCUIO_HPLL_EXT_PARAM] = 0x80000014, 1048 [AST2700_SCUIO_APLL_PARAM] = 0x1000001f, 1049 [AST2700_SCUIO_APLL_EXT_PARAM] = 0x8000000f, 1050 [AST2700_SCUIO_DPLL_PARAM] = 0x106e42ce, 1051 [AST2700_SCUIO_DPLL_EXT_PARAM] = 0x80000167, 1052 [AST2700_SCUIO_DPLL_PARAM_READ] = 0x106e42ce, 1053 [AST2700_SCUIO_DPLL_EXT_PARAM_READ] = 0x80000167, 1054 [AST2700_SCUIO_UARTCLK_GEN] = 0x00014506, 1055 [AST2700_SCUIO_HUARTCLK_GEN] = 0x000145c0, 1056 [AST2700_SCUIO_CLK_DUTY_MEAS_RST] = 0x0c9100d2, 1057 }; 1058 1059 static void aspeed_2700_scuio_class_init(ObjectClass *klass, void *data) 1060 { 1061 DeviceClass *dc = DEVICE_CLASS(klass); 1062 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); 1063 1064 dc->desc = "ASPEED 2700 System Control Unit I/O"; 1065 device_class_set_legacy_reset(dc, aspeed_ast2700_scu_reset); 1066 asc->resets = ast2700_a0_resets_io; 1067 asc->calc_hpll = aspeed_2600_scu_calc_hpll; 1068 asc->get_apb = aspeed_2700_scuio_get_apb_freq; 1069 asc->apb_divider = 2; 1070 asc->nr_regs = ASPEED_AST2700_SCU_NR_REGS; 1071 asc->clkin_25Mhz = true; 1072 asc->ops = &aspeed_ast2700_scuio_ops; 1073 } 1074 1075 static const TypeInfo aspeed_2700_scu_info = { 1076 .name = TYPE_ASPEED_2700_SCU, 1077 .parent = TYPE_ASPEED_SCU, 1078 .instance_size = sizeof(AspeedSCUState), 1079 .class_init = aspeed_2700_scu_class_init, 1080 }; 1081 1082 static const TypeInfo aspeed_2700_scuio_info = { 1083 .name = TYPE_ASPEED_2700_SCUIO, 1084 .parent = TYPE_ASPEED_SCU, 1085 .instance_size = sizeof(AspeedSCUState), 1086 .class_init = aspeed_2700_scuio_class_init, 1087 }; 1088 1089 static const uint32_t ast1030_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = { 1090 [AST2600_SYS_RST_CTRL] = 0xFFC3FED8, 1091 [AST2600_SYS_RST_CTRL2] = 0x09FFFFFC, 1092 [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A, 1093 [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, 1094 [AST2600_DEBUG_CTRL2] = 0x00000000, 1095 [AST2600_HPLL_PARAM] = 0x10004077, 1096 [AST2600_HPLL_EXT] = 0x00000031, 1097 [AST2600_CLK_SEL4] = 0x43F90900, 1098 [AST2600_CLK_SEL5] = 0x40000000, 1099 [AST2600_CHIP_ID0] = 0xDEADBEEF, 1100 [AST2600_CHIP_ID1] = 0x0BADCAFE, 1101 }; 1102 1103 static void aspeed_ast1030_scu_reset(DeviceState *dev) 1104 { 1105 AspeedSCUState *s = ASPEED_SCU(dev); 1106 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); 1107 1108 memcpy(s->regs, asc->resets, asc->nr_regs * 4); 1109 1110 s->regs[AST2600_SILICON_REV] = AST1030_A1_SILICON_REV; 1111 s->regs[AST2600_SILICON_REV2] = s->silicon_rev; 1112 s->regs[AST2600_HW_STRAP1] = s->hw_strap1; 1113 s->regs[AST2600_HW_STRAP2] = s->hw_strap2; 1114 s->regs[PROT_KEY] = s->hw_prot_key; 1115 } 1116 1117 static void aspeed_1030_scu_class_init(ObjectClass *klass, void *data) 1118 { 1119 DeviceClass *dc = DEVICE_CLASS(klass); 1120 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); 1121 1122 dc->desc = "ASPEED 1030 System Control Unit"; 1123 device_class_set_legacy_reset(dc, aspeed_ast1030_scu_reset); 1124 asc->resets = ast1030_a1_resets; 1125 asc->calc_hpll = aspeed_2600_scu_calc_hpll; 1126 asc->get_apb = aspeed_1030_scu_get_apb_freq; 1127 asc->apb_divider = 2; 1128 asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS; 1129 asc->clkin_25Mhz = true; 1130 asc->ops = &aspeed_ast2600_scu_ops; 1131 } 1132 1133 static const TypeInfo aspeed_1030_scu_info = { 1134 .name = TYPE_ASPEED_1030_SCU, 1135 .parent = TYPE_ASPEED_SCU, 1136 .instance_size = sizeof(AspeedSCUState), 1137 .class_init = aspeed_1030_scu_class_init, 1138 }; 1139 1140 static void aspeed_scu_register_types(void) 1141 { 1142 type_register_static(&aspeed_scu_info); 1143 type_register_static(&aspeed_2400_scu_info); 1144 type_register_static(&aspeed_2500_scu_info); 1145 type_register_static(&aspeed_2600_scu_info); 1146 type_register_static(&aspeed_1030_scu_info); 1147 type_register_static(&aspeed_2700_scu_info); 1148 type_register_static(&aspeed_2700_scuio_info); 1149 } 1150 1151 type_init(aspeed_scu_register_types); 1152