1 /* 2 * Cortex-A9MPCore Snoop Control Unit (SCU) emulation. 3 * 4 * Copyright (c) 2009 CodeSourcery. 5 * Copyright (c) 2011 Linaro Limited. 6 * Written by Paul Brook, Peter Maydell. 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "hw/sysbus.h" 12 13 /* A9MP private memory region. */ 14 15 typedef struct A9SCUState { 16 /*< private >*/ 17 SysBusDevice parent_obj; 18 /*< public >*/ 19 20 MemoryRegion iomem; 21 uint32_t control; 22 uint32_t status; 23 uint32_t num_cpu; 24 } A9SCUState; 25 26 #define TYPE_A9_SCU "a9-scu" 27 #define A9_SCU(obj) OBJECT_CHECK(A9SCUState, (obj), TYPE_A9_SCU) 28 29 static uint64_t a9_scu_read(void *opaque, hwaddr offset, 30 unsigned size) 31 { 32 A9SCUState *s = (A9SCUState *)opaque; 33 switch (offset) { 34 case 0x00: /* Control */ 35 return s->control; 36 case 0x04: /* Configuration */ 37 return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1); 38 case 0x08: /* CPU Power Status */ 39 return s->status; 40 case 0x09: /* CPU status. */ 41 return s->status >> 8; 42 case 0x0a: /* CPU status. */ 43 return s->status >> 16; 44 case 0x0b: /* CPU status. */ 45 return s->status >> 24; 46 case 0x0c: /* Invalidate All Registers In Secure State */ 47 return 0; 48 case 0x40: /* Filtering Start Address Register */ 49 case 0x44: /* Filtering End Address Register */ 50 /* RAZ/WI, like an implementation with only one AXI master */ 51 return 0; 52 case 0x50: /* SCU Access Control Register */ 53 case 0x54: /* SCU Non-secure Access Control Register */ 54 /* unimplemented, fall through */ 55 default: 56 return 0; 57 } 58 } 59 60 static void a9_scu_write(void *opaque, hwaddr offset, 61 uint64_t value, unsigned size) 62 { 63 A9SCUState *s = (A9SCUState *)opaque; 64 uint32_t mask; 65 uint32_t shift; 66 switch (size) { 67 case 1: 68 mask = 0xff; 69 break; 70 case 2: 71 mask = 0xffff; 72 break; 73 case 4: 74 mask = 0xffffffff; 75 break; 76 default: 77 fprintf(stderr, "Invalid size %u in write to a9 scu register %x\n", 78 size, (unsigned)offset); 79 return; 80 } 81 82 switch (offset) { 83 case 0x00: /* Control */ 84 s->control = value & 1; 85 break; 86 case 0x4: /* Configuration: RO */ 87 break; 88 case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */ 89 shift = (offset - 0x8) * 8; 90 s->status &= ~(mask << shift); 91 s->status |= ((value & mask) << shift); 92 break; 93 case 0x0c: /* Invalidate All Registers In Secure State */ 94 /* no-op as we do not implement caches */ 95 break; 96 case 0x40: /* Filtering Start Address Register */ 97 case 0x44: /* Filtering End Address Register */ 98 /* RAZ/WI, like an implementation with only one AXI master */ 99 break; 100 case 0x50: /* SCU Access Control Register */ 101 case 0x54: /* SCU Non-secure Access Control Register */ 102 /* unimplemented, fall through */ 103 default: 104 break; 105 } 106 } 107 108 static const MemoryRegionOps a9_scu_ops = { 109 .read = a9_scu_read, 110 .write = a9_scu_write, 111 .endianness = DEVICE_NATIVE_ENDIAN, 112 }; 113 114 static void a9_scu_reset(DeviceState *dev) 115 { 116 A9SCUState *s = A9_SCU(dev); 117 s->control = 0; 118 } 119 120 static void a9_scu_init(Object *obj) 121 { 122 A9SCUState *s = A9_SCU(obj); 123 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 124 125 memory_region_init_io(&s->iomem, obj, &a9_scu_ops, s, 126 "a9-scu", 0x100); 127 sysbus_init_mmio(sbd, &s->iomem); 128 } 129 130 static const VMStateDescription vmstate_a9_scu = { 131 .name = "a9-scu", 132 .version_id = 1, 133 .minimum_version_id = 1, 134 .fields = (VMStateField[]) { 135 VMSTATE_UINT32(control, A9SCUState), 136 VMSTATE_UINT32(status, A9SCUState), 137 VMSTATE_END_OF_LIST() 138 } 139 }; 140 141 static Property a9_scu_properties[] = { 142 DEFINE_PROP_UINT32("num-cpu", A9SCUState, num_cpu, 1), 143 DEFINE_PROP_END_OF_LIST(), 144 }; 145 146 static void a9_scu_class_init(ObjectClass *klass, void *data) 147 { 148 DeviceClass *dc = DEVICE_CLASS(klass); 149 150 dc->props = a9_scu_properties; 151 dc->vmsd = &vmstate_a9_scu; 152 dc->reset = a9_scu_reset; 153 } 154 155 static const TypeInfo a9_scu_info = { 156 .name = TYPE_A9_SCU, 157 .parent = TYPE_SYS_BUS_DEVICE, 158 .instance_size = sizeof(A9SCUState), 159 .instance_init = a9_scu_init, 160 .class_init = a9_scu_class_init, 161 }; 162 163 static void a9mp_register_types(void) 164 { 165 type_register_static(&a9_scu_info); 166 } 167 168 type_init(a9mp_register_types) 169