xref: /qemu/hw/mips/trace-events (revision f8ead0d7bdebd81f4d8457c48f1d003fd4d94c69)
1b15e402fSMarkus Armbruster# gt64xxx_pci.c
2*f8ead0d7SPhilippe Mathieu-Daudégt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64
3*f8ead0d7SPhilippe Mathieu-Daudégt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64
41b3422bdSPhilippe Mathieu-Daudégt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64
51b3422bdSPhilippe Mathieu-Daudégt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64
6ab6bff42SPhilippe Mathieu-Daudégt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64
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