1 /* 2 * QEMU Malta board support 3 * 4 * Copyright (c) 2006 Aurelien Jarno 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qemu/bitops.h" 28 #include "qemu/datadir.h" 29 #include "qemu/cutils.h" 30 #include "qemu/guest-random.h" 31 #include "exec/tswap.h" 32 #include "hw/clock.h" 33 #include "hw/southbridge/piix.h" 34 #include "hw/isa/superio.h" 35 #include "hw/char/serial-mm.h" 36 #include "net/net.h" 37 #include "hw/boards.h" 38 #include "hw/i2c/smbus_eeprom.h" 39 #include "hw/block/flash.h" 40 #include "hw/mips/mips.h" 41 #include "hw/mips/bootloader.h" 42 #include "hw/pci/pci.h" 43 #include "hw/pci/pci_bus.h" 44 #include "qemu/log.h" 45 #include "hw/ide/pci.h" 46 #include "hw/irq.h" 47 #include "hw/loader.h" 48 #include "elf.h" 49 #include "qom/object.h" 50 #include "hw/sysbus.h" /* SysBusDevice */ 51 #include "qemu/host-utils.h" 52 #include "system/qtest.h" 53 #include "system/reset.h" 54 #include "system/runstate.h" 55 #include "qapi/error.h" 56 #include "qemu/error-report.h" 57 #include "system/kvm.h" 58 #include "semihosting/semihost.h" 59 #include "hw/mips/cps.h" 60 #include "hw/qdev-clock.h" 61 #include "target/mips/internal.h" 62 #include "trace.h" 63 #include "cpu.h" 64 65 #define ENVP_PADDR 0x2000 66 #define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR) 67 #define ENVP_NB_ENTRIES 16 68 #define ENVP_ENTRY_SIZE 256 69 70 /* Hardware addresses */ 71 #define FLASH_ADDRESS 0x1e000000ULL 72 #define FPGA_ADDRESS 0x1f000000ULL 73 #define RESET_ADDRESS 0x1fc00000ULL 74 75 #define FLASH_SIZE 0x400000 76 #define BIOS_SIZE (4 * MiB) 77 78 #define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0) 79 80 typedef struct { 81 MemoryRegion iomem; 82 MemoryRegion iomem_lo; /* 0 - 0x900 */ 83 MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */ 84 uint32_t leds; 85 uint32_t brk; 86 uint32_t gpout; 87 uint32_t i2cin; 88 uint32_t i2coe; 89 uint32_t i2cout; 90 uint32_t i2csel; 91 CharBackend display; 92 char display_text[9]; 93 SerialMM *uart; 94 bool display_inited; 95 } MaltaFPGAState; 96 97 #if TARGET_BIG_ENDIAN 98 #define BIOS_FILENAME "mips_bios.bin" 99 #else 100 #define BIOS_FILENAME "mipsel_bios.bin" 101 #endif 102 103 #define TYPE_MIPS_MALTA "mips-malta" 104 OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA) 105 106 struct MaltaState { 107 SysBusDevice parent_obj; 108 109 Clock *cpuclk; 110 MIPSCPSState cps; 111 }; 112 113 static struct _loaderparams { 114 int ram_size, ram_low_size; 115 const char *kernel_filename; 116 const char *kernel_cmdline; 117 const char *initrd_filename; 118 } loaderparams; 119 120 /* Malta FPGA */ 121 static void malta_fpga_update_display_leds(MaltaFPGAState *s) 122 { 123 char leds_text[9]; 124 int i; 125 126 for (i = 7 ; i >= 0 ; i--) { 127 if (s->leds & (1 << i)) { 128 leds_text[i] = '#'; 129 } else { 130 leds_text[i] = ' '; 131 } 132 } 133 leds_text[8] = '\0'; 134 135 trace_malta_fpga_leds(leds_text); 136 qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", 137 leds_text); 138 } 139 140 static void malta_fpga_update_display_ascii(MaltaFPGAState *s) 141 { 142 trace_malta_fpga_display(s->display_text); 143 qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", 144 s->display_text); 145 } 146 147 /* 148 * EEPROM 24C01 / 24C02 emulation. 149 * 150 * Emulation for serial EEPROMs: 151 * 24C01 - 1024 bit (128 x 8) 152 * 24C02 - 2048 bit (256 x 8) 153 * 154 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02. 155 */ 156 157 #if defined(DEBUG) 158 # define logout(fmt, ...) \ 159 fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__) 160 #else 161 # define logout(fmt, ...) ((void)0) 162 #endif 163 164 struct _eeprom24c0x_t { 165 uint8_t tick; 166 uint8_t address; 167 uint8_t command; 168 uint8_t ack; 169 uint8_t scl; 170 uint8_t sda; 171 uint8_t data; 172 /* uint16_t size; */ 173 uint8_t contents[256]; 174 }; 175 176 typedef struct _eeprom24c0x_t eeprom24c0x_t; 177 178 static eeprom24c0x_t spd_eeprom = { 179 .contents = { 180 /* 00000000: */ 181 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00, 182 /* 00000008: */ 183 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01, 184 /* 00000010: */ 185 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 186 /* 00000018: */ 187 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF, 188 /* 00000020: */ 189 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00, 190 /* 00000028: */ 191 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 192 /* 00000030: */ 193 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 194 /* 00000038: */ 195 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0, 196 /* 00000040: */ 197 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 198 /* 00000048: */ 199 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 200 /* 00000050: */ 201 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 202 /* 00000058: */ 203 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 204 /* 00000060: */ 205 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 206 /* 00000068: */ 207 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 208 /* 00000070: */ 209 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 210 /* 00000078: */ 211 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4, 212 }, 213 }; 214 215 static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size) 216 { 217 enum sdram_type type; 218 uint8_t *spd = spd_eeprom.contents; 219 uint8_t nbanks = 0; 220 uint16_t density = 0; 221 int i; 222 223 /* work in terms of MB */ 224 ram_size /= MiB; 225 226 while ((ram_size >= 4) && (nbanks <= 2)) { 227 int sz_log2 = MIN(31 - clz32(ram_size), 14); 228 nbanks++; 229 density |= 1 << (sz_log2 - 2); 230 ram_size -= 1 << sz_log2; 231 } 232 233 /* split to 2 banks if possible */ 234 if ((nbanks == 1) && (density > 1)) { 235 nbanks++; 236 density >>= 1; 237 } 238 239 if (density & 0xff00) { 240 density = (density & 0xe0) | ((density >> 8) & 0x1f); 241 type = DDR2; 242 } else if (!(density & 0x1f)) { 243 type = DDR2; 244 } else { 245 type = SDR; 246 } 247 248 if (ram_size) { 249 warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB" 250 " of SDRAM", ram_size); 251 } 252 253 /* fill in SPD memory information */ 254 spd[2] = type; 255 spd[5] = nbanks; 256 spd[31] = density; 257 258 /* checksum */ 259 spd[63] = 0; 260 for (i = 0; i < 63; i++) { 261 spd[63] += spd[i]; 262 } 263 264 /* copy for SMBUS */ 265 memcpy(eeprom, spd, sizeof(spd_eeprom.contents)); 266 } 267 268 static void generate_eeprom_serial(uint8_t *eeprom) 269 { 270 int i, pos = 0; 271 uint8_t mac[6] = { 0x00 }; 272 uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 }; 273 274 /* version */ 275 eeprom[pos++] = 0x01; 276 277 /* count */ 278 eeprom[pos++] = 0x02; 279 280 /* MAC address */ 281 eeprom[pos++] = 0x01; /* MAC */ 282 eeprom[pos++] = 0x06; /* length */ 283 memcpy(&eeprom[pos], mac, sizeof(mac)); 284 pos += sizeof(mac); 285 286 /* serial number */ 287 eeprom[pos++] = 0x02; /* serial */ 288 eeprom[pos++] = 0x05; /* length */ 289 memcpy(&eeprom[pos], sn, sizeof(sn)); 290 pos += sizeof(sn); 291 292 /* checksum */ 293 eeprom[pos] = 0; 294 for (i = 0; i < pos; i++) { 295 eeprom[pos] += eeprom[i]; 296 } 297 } 298 299 static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom) 300 { 301 logout("%u: scl = %u, sda = %u, data = 0x%02x\n", 302 eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data); 303 return eeprom->sda; 304 } 305 306 static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda) 307 { 308 if (eeprom->scl && scl && (eeprom->sda != sda)) { 309 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n", 310 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda, 311 sda ? "stop" : "start"); 312 if (!sda) { 313 eeprom->tick = 1; 314 eeprom->command = 0; 315 } 316 } else if (eeprom->tick == 0 && !eeprom->ack) { 317 /* Waiting for start. */ 318 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n", 319 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); 320 } else if (!eeprom->scl && scl) { 321 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n", 322 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); 323 if (eeprom->ack) { 324 logout("\ti2c ack bit = 0\n"); 325 sda = 0; 326 eeprom->ack = 0; 327 } else if (eeprom->sda == sda) { 328 uint8_t bit = (sda != 0); 329 logout("\ti2c bit = %d\n", bit); 330 if (eeprom->tick < 9) { 331 eeprom->command <<= 1; 332 eeprom->command += bit; 333 eeprom->tick++; 334 if (eeprom->tick == 9) { 335 logout("\tcommand 0x%04x, %s\n", eeprom->command, 336 bit ? "read" : "write"); 337 eeprom->ack = 1; 338 } 339 } else if (eeprom->tick < 17) { 340 if (eeprom->command & 1) { 341 sda = ((eeprom->data & 0x80) != 0); 342 } 343 eeprom->address <<= 1; 344 eeprom->address += bit; 345 eeprom->tick++; 346 eeprom->data <<= 1; 347 if (eeprom->tick == 17) { 348 eeprom->data = eeprom->contents[eeprom->address]; 349 logout("\taddress 0x%04x, data 0x%02x\n", 350 eeprom->address, eeprom->data); 351 eeprom->ack = 1; 352 eeprom->tick = 0; 353 } 354 } else if (eeprom->tick >= 17) { 355 sda = 0; 356 } 357 } else { 358 logout("\tsda changed with raising scl\n"); 359 } 360 } else { 361 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl, 362 scl, eeprom->sda, sda); 363 } 364 eeprom->scl = scl; 365 eeprom->sda = sda; 366 } 367 368 static uint64_t malta_fpga_read(void *opaque, hwaddr addr, 369 unsigned size) 370 { 371 MaltaFPGAState *s = opaque; 372 uint32_t val = 0; 373 uint32_t saddr; 374 375 saddr = (addr & 0xfffff); 376 377 switch (saddr) { 378 379 /* SWITCH Register */ 380 case 0x00200: 381 val = 0x00000000; 382 break; 383 384 /* STATUS Register */ 385 case 0x00208: 386 #if TARGET_BIG_ENDIAN 387 val = 0x00000012; 388 #else 389 val = 0x00000010; 390 #endif 391 break; 392 393 /* JMPRS Register */ 394 case 0x00210: 395 val = 0x00; 396 break; 397 398 /* LEDBAR Register */ 399 case 0x00408: 400 val = s->leds; 401 break; 402 403 /* BRKRES Register */ 404 case 0x00508: 405 val = s->brk; 406 break; 407 408 /* UART Registers are handled directly by the serial device */ 409 410 /* GPOUT Register */ 411 case 0x00a00: 412 val = s->gpout; 413 break; 414 415 /* XXX: implement a real I2C controller */ 416 417 /* GPINP Register */ 418 case 0x00a08: 419 /* IN = OUT until a real I2C control is implemented */ 420 if (s->i2csel) { 421 val = s->i2cout; 422 } else { 423 val = 0x00; 424 } 425 break; 426 427 /* I2CINP Register */ 428 case 0x00b00: 429 val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom)); 430 break; 431 432 /* I2COE Register */ 433 case 0x00b08: 434 val = s->i2coe; 435 break; 436 437 /* I2COUT Register */ 438 case 0x00b10: 439 val = s->i2cout; 440 break; 441 442 /* I2CSEL Register */ 443 case 0x00b18: 444 val = s->i2csel; 445 break; 446 447 default: 448 qemu_log_mask(LOG_GUEST_ERROR, 449 "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n", 450 addr); 451 break; 452 } 453 return val; 454 } 455 456 static void malta_fpga_write(void *opaque, hwaddr addr, 457 uint64_t val, unsigned size) 458 { 459 MaltaFPGAState *s = opaque; 460 uint32_t saddr; 461 462 saddr = (addr & 0xfffff); 463 464 switch (saddr) { 465 466 /* SWITCH Register */ 467 case 0x00200: 468 break; 469 470 /* JMPRS Register */ 471 case 0x00210: 472 break; 473 474 /* LEDBAR Register */ 475 case 0x00408: 476 s->leds = val & 0xff; 477 malta_fpga_update_display_leds(s); 478 break; 479 480 /* ASCIIWORD Register */ 481 case 0x00410: 482 snprintf(s->display_text, 9, "%08X", (uint32_t)val); 483 malta_fpga_update_display_ascii(s); 484 break; 485 486 /* ASCIIPOS0 to ASCIIPOS7 Registers */ 487 case 0x00418: 488 case 0x00420: 489 case 0x00428: 490 case 0x00430: 491 case 0x00438: 492 case 0x00440: 493 case 0x00448: 494 case 0x00450: 495 s->display_text[(saddr - 0x00418) >> 3] = (char) val; 496 malta_fpga_update_display_ascii(s); 497 break; 498 499 /* SOFTRES Register */ 500 case 0x00500: 501 if (val == 0x42) { 502 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 503 } 504 break; 505 506 /* BRKRES Register */ 507 case 0x00508: 508 s->brk = val & 0xff; 509 break; 510 511 /* UART Registers are handled directly by the serial device */ 512 513 /* GPOUT Register */ 514 case 0x00a00: 515 s->gpout = val & 0xff; 516 break; 517 518 /* I2COE Register */ 519 case 0x00b08: 520 s->i2coe = val & 0x03; 521 break; 522 523 /* I2COUT Register */ 524 case 0x00b10: 525 eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01); 526 s->i2cout = val; 527 break; 528 529 /* I2CSEL Register */ 530 case 0x00b18: 531 s->i2csel = val & 0x01; 532 break; 533 534 default: 535 qemu_log_mask(LOG_GUEST_ERROR, 536 "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n", 537 addr); 538 break; 539 } 540 } 541 542 static const MemoryRegionOps malta_fpga_ops = { 543 .read = malta_fpga_read, 544 .write = malta_fpga_write, 545 .endianness = DEVICE_NATIVE_ENDIAN, 546 }; 547 548 static void malta_fpga_reset(void *opaque) 549 { 550 MaltaFPGAState *s = opaque; 551 552 s->leds = 0x00; 553 s->brk = 0x0a; 554 s->gpout = 0x00; 555 s->i2cin = 0x3; 556 s->i2coe = 0x0; 557 s->i2cout = 0x3; 558 s->i2csel = 0x1; 559 560 s->display_text[8] = '\0'; 561 snprintf(s->display_text, 9, " "); 562 } 563 564 static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event) 565 { 566 MaltaFPGAState *s = opaque; 567 568 if (event == CHR_EVENT_OPENED && !s->display_inited) { 569 qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n"); 570 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 571 qemu_chr_fe_printf(&s->display, "+ +\r\n"); 572 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 573 qemu_chr_fe_printf(&s->display, "\n"); 574 qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n"); 575 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 576 qemu_chr_fe_printf(&s->display, "+ +\r\n"); 577 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 578 s->display_inited = true; 579 } 580 } 581 582 static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space, 583 hwaddr base, qemu_irq uart_irq, Chardev *uart_chr) 584 { 585 MaltaFPGAState *s; 586 Chardev *chr; 587 588 s = g_new0(MaltaFPGAState, 1); 589 590 memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s, 591 "malta-fpga", 0x100000); 592 memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga", 593 &s->iomem, 0, 0x900); 594 memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga", 595 &s->iomem, 0xa00, 0x100000 - 0xa00); 596 597 memory_region_add_subregion(address_space, base, &s->iomem_lo); 598 memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi); 599 600 chr = qemu_chr_new("fpga", "vc:320x200", NULL); 601 qemu_chr_fe_init(&s->display, chr, NULL); 602 qemu_chr_fe_set_handlers(&s->display, NULL, NULL, 603 malta_fgpa_display_event, NULL, s, NULL, true); 604 605 s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq, 606 230400, uart_chr, DEVICE_NATIVE_ENDIAN); 607 608 malta_fpga_reset(s); 609 qemu_register_reset(malta_fpga_reset, s); 610 611 return s; 612 } 613 614 /* Network support */ 615 static void network_init(PCIBus *pci_bus) 616 { 617 /* The malta board has a PCNet card using PCI SLOT 11 */ 618 pci_init_nic_in_slot(pci_bus, "pcnet", NULL, "0b"); 619 pci_init_nic_devices(pci_bus, "pcnet"); 620 } 621 622 static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, 623 uint64_t kernel_entry) 624 { 625 static const char pci_pins_cfg[PCI_NUM_PINS] = { 626 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ 627 }; 628 629 /* Bus endianness is always reversed */ 630 #if TARGET_BIG_ENDIAN 631 #define cpu_to_gt32(x) (x) 632 #else 633 #define cpu_to_gt32(x) bswap32(x) 634 #endif 635 636 /* setup MEM-to-PCI0 mapping as done by YAMON */ 637 638 /* move GT64120 registers from 0x14000000 to 0x1be00000 */ 639 bl_gen_write_u32(p, /* GT_ISD */ 640 cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68), 641 cpu_to_gt32(0x1be00000 << 3)); 642 643 /* setup PCI0 io window to 0x18000000-0x181fffff */ 644 bl_gen_write_u32(p, /* GT_PCI0IOLD */ 645 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48), 646 cpu_to_gt32(0x18000000 << 3)); 647 bl_gen_write_u32(p, /* GT_PCI0IOHD */ 648 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50), 649 cpu_to_gt32(0x08000000 << 3)); 650 651 /* setup PCI0 mem windows */ 652 bl_gen_write_u32(p, /* GT_PCI0M0LD */ 653 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58), 654 cpu_to_gt32(0x10000000 << 3)); 655 bl_gen_write_u32(p, /* GT_PCI0M0HD */ 656 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60), 657 cpu_to_gt32(0x07e00000 << 3)); 658 bl_gen_write_u32(p, /* GT_PCI0M1LD */ 659 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80), 660 cpu_to_gt32(0x18200000 << 3)); 661 bl_gen_write_u32(p, /* GT_PCI0M1HD */ 662 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88), 663 cpu_to_gt32(0x0bc00000 << 3)); 664 665 #undef cpu_to_gt32 666 667 /* 668 * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. 669 * Load the PIIX IRQC[A:D] routing config address, then 670 * write routing configuration to the config data register. 671 */ 672 bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */ 673 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), 674 tswap32((1 << 31) /* ConfigEn */ 675 | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 676 | PIIX_PIRQCA)); 677 bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */ 678 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), 679 tswap32(ldl_be_p(pci_pins_cfg))); 680 681 bl_gen_jump_kernel(p, 682 true, ENVP_VADDR - 64, 683 /* 684 * If semihosting is used, arguments have already 685 * been passed, so we preserve $a0. 686 */ 687 !semihosting_get_argc(), 2, 688 true, ENVP_VADDR, 689 true, ENVP_VADDR + 8, 690 true, loaderparams.ram_low_size, 691 kernel_entry); 692 } 693 694 static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, 695 uint64_t kernel_entry) 696 { 697 uint16_t *p; 698 699 /* Small bootloader */ 700 p = (uint16_t *)base; 701 702 stw_p(p++, 0x2800); stw_p(p++, 0x001c); 703 /* bc to_here */ 704 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 705 /* nop */ 706 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 707 /* nop */ 708 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 709 /* nop */ 710 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 711 /* nop */ 712 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 713 /* nop */ 714 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 715 /* nop */ 716 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 717 /* nop */ 718 719 /* to_here: */ 720 721 bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry); 722 } 723 724 /* 725 * ROM and pseudo bootloader 726 * 727 * The following code implements a very very simple bootloader. It first 728 * loads the registers a0 to a3 to the values expected by the OS, and 729 * then jump at the kernel address. 730 * 731 * The bootloader should pass the locations of the kernel arguments and 732 * environment variables tables. Those tables contain the 32-bit address 733 * of NULL terminated strings. The environment variables table should be 734 * terminated by a NULL address. 735 * 736 * For a simpler implementation, the number of kernel arguments is fixed 737 * to two (the name of the kernel and the command line), and the two 738 * tables are actually the same one. 739 * 740 * The registers a0 to a3 should contain the following values: 741 * a0 - number of kernel arguments 742 * a1 - 32-bit address of the kernel arguments table 743 * a2 - 32-bit address of the environment variables table 744 * a3 - RAM size in bytes 745 */ 746 static void write_bootloader(uint8_t *base, uint64_t run_addr, 747 uint64_t kernel_entry) 748 { 749 uint32_t *p; 750 751 /* Small bootloader */ 752 p = (uint32_t *)base; 753 754 stl_p(p++, 0x08000000 | /* j 0x1fc00580 */ 755 ((run_addr + 0x580) & 0x0fffffff) >> 2); 756 stl_p(p++, 0x00000000); /* nop */ 757 758 /* YAMON service vector */ 759 stl_p(base + 0x500, run_addr + 0x0580); /* start: */ 760 stl_p(base + 0x504, run_addr + 0x083c); /* print_count: */ 761 stl_p(base + 0x520, run_addr + 0x0580); /* start: */ 762 stl_p(base + 0x52c, run_addr + 0x0800); /* flush_cache: */ 763 stl_p(base + 0x534, run_addr + 0x0808); /* print: */ 764 stl_p(base + 0x538, run_addr + 0x0800); /* reg_cpu_isr: */ 765 stl_p(base + 0x53c, run_addr + 0x0800); /* unred_cpu_isr: */ 766 stl_p(base + 0x540, run_addr + 0x0800); /* reg_ic_isr: */ 767 stl_p(base + 0x544, run_addr + 0x0800); /* unred_ic_isr: */ 768 stl_p(base + 0x548, run_addr + 0x0800); /* reg_esr: */ 769 stl_p(base + 0x54c, run_addr + 0x0800); /* unreg_esr: */ 770 stl_p(base + 0x550, run_addr + 0x0800); /* getchar: */ 771 stl_p(base + 0x554, run_addr + 0x0800); /* syscon_read: */ 772 773 774 /* Second part of the bootloader */ 775 p = (uint32_t *) (base + 0x580); 776 777 /* 778 * Load BAR registers as done by YAMON: 779 * 780 * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff 781 * - set up PCI0 MEM0 at 0x10000000, size 0x7e00000 782 * - set up PCI0 MEM1 at 0x18200000, size 0xbc00000 783 * 784 */ 785 786 bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry); 787 788 /* YAMON subroutines */ 789 p = (uint32_t *) (base + 0x800); 790 stl_p(p++, 0x03e00009); /* jalr ra */ 791 stl_p(p++, 0x24020000); /* li v0,0 */ 792 /* 808 YAMON print */ 793 stl_p(p++, 0x03e06821); /* move t5,ra */ 794 stl_p(p++, 0x00805821); /* move t3,a0 */ 795 stl_p(p++, 0x00a05021); /* move t2,a1 */ 796 stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ 797 stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ 798 stl_p(p++, 0x10800005); /* beqz a0,834 */ 799 stl_p(p++, 0x00000000); /* nop */ 800 stl_p(p++, 0x0ff0021c); /* jal 870 */ 801 stl_p(p++, 0x00000000); /* nop */ 802 stl_p(p++, 0x1000fff9); /* b 814 */ 803 stl_p(p++, 0x00000000); /* nop */ 804 stl_p(p++, 0x01a00009); /* jalr t5 */ 805 stl_p(p++, 0x01602021); /* move a0,t3 */ 806 /* 0x83c YAMON print_count */ 807 stl_p(p++, 0x03e06821); /* move t5,ra */ 808 stl_p(p++, 0x00805821); /* move t3,a0 */ 809 stl_p(p++, 0x00a05021); /* move t2,a1 */ 810 stl_p(p++, 0x00c06021); /* move t4,a2 */ 811 stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ 812 stl_p(p++, 0x0ff0021c); /* jal 870 */ 813 stl_p(p++, 0x00000000); /* nop */ 814 stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ 815 stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */ 816 stl_p(p++, 0x1580fffa); /* bnez t4,84c */ 817 stl_p(p++, 0x00000000); /* nop */ 818 stl_p(p++, 0x01a00009); /* jalr t5 */ 819 stl_p(p++, 0x01602021); /* move a0,t3 */ 820 /* 0x870 */ 821 stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */ 822 stl_p(p++, 0x350803f8); /* ori t0,t0,0x3f8 */ 823 stl_p(p++, 0x91090005); /* lbu t1,5(t0) */ 824 stl_p(p++, 0x00000000); /* nop */ 825 stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */ 826 stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */ 827 stl_p(p++, 0x00000000); /* nop */ 828 stl_p(p++, 0x03e00009); /* jalr ra */ 829 stl_p(p++, 0xa1040000); /* sb a0,0(t0) */ 830 } 831 832 static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t *prom_buf, int index, 833 const char *string, ...) 834 { 835 va_list ap; 836 uint32_t table_addr; 837 838 if (index >= ENVP_NB_ENTRIES) { 839 return; 840 } 841 842 if (string == NULL) { 843 prom_buf[index] = 0; 844 return; 845 } 846 847 table_addr = sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE; 848 prom_buf[index] = tswap32(ENVP_VADDR + table_addr); 849 850 va_start(ap, string); 851 vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap); 852 va_end(ap); 853 } 854 855 static GString *rng_seed_hex_new(void) 856 { 857 uint8_t rng_seed[32]; 858 859 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 860 return qemu_hexdump_line(NULL, rng_seed, sizeof(rng_seed), 0, 0); 861 } 862 863 static void reinitialize_rng_seed(void *opaque) 864 { 865 g_autoptr(GString) hex = rng_seed_hex_new(); 866 memcpy(opaque, hex->str, hex->len); 867 } 868 869 /* Kernel */ 870 static uint64_t load_kernel(void) 871 { 872 uint64_t kernel_entry, kernel_high, initrd_size; 873 long kernel_size; 874 ram_addr_t initrd_offset; 875 uint32_t *prom_buf; 876 long prom_size; 877 int prom_index = 0; 878 size_t rng_seed_prom_offset; 879 880 kernel_size = load_elf(loaderparams.kernel_filename, NULL, 881 cpu_mips_kseg0_to_phys, NULL, 882 &kernel_entry, NULL, 883 &kernel_high, NULL, 884 TARGET_BIG_ENDIAN ? ELFDATA2MSB : ELFDATA2LSB, 885 EM_MIPS, 1, 0); 886 if (kernel_size < 0) { 887 error_report("could not load kernel '%s': %s", 888 loaderparams.kernel_filename, 889 load_elf_strerror(kernel_size)); 890 exit(1); 891 } 892 893 /* Check where the kernel has been linked */ 894 if (kernel_entry <= USEG_LIMIT) { 895 error_report("Trap-and-Emul kernels (Linux CONFIG_KVM_GUEST)" 896 " are not supported"); 897 exit(1); 898 } 899 900 /* load initrd */ 901 initrd_size = 0; 902 initrd_offset = 0; 903 if (loaderparams.initrd_filename) { 904 initrd_size = get_image_size(loaderparams.initrd_filename); 905 if (initrd_size > 0) { 906 /* 907 * The kernel allocates the bootmap memory in the low memory after 908 * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB 909 * pages. 910 */ 911 initrd_offset = ROUND_UP(loaderparams.ram_low_size 912 - (initrd_size + 128 * KiB), 913 INITRD_PAGE_SIZE); 914 if (kernel_high >= initrd_offset) { 915 error_report("memory too small for initial ram disk '%s'", 916 loaderparams.initrd_filename); 917 exit(1); 918 } 919 initrd_size = load_image_targphys(loaderparams.initrd_filename, 920 initrd_offset, 921 loaderparams.ram_size - initrd_offset); 922 } 923 if (initrd_size == (target_ulong) -1) { 924 error_report("could not load initial ram disk '%s'", 925 loaderparams.initrd_filename); 926 exit(1); 927 } 928 } 929 930 /* Setup prom parameters. */ 931 prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE); 932 prom_buf = g_malloc(prom_size); 933 934 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename); 935 if (initrd_size > 0) { 936 prom_set(prom_buf, prom_index++, 937 "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s", 938 cpu_mips_phys_to_kseg0(NULL, initrd_offset), 939 initrd_size, loaderparams.kernel_cmdline); 940 } else { 941 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline); 942 } 943 944 prom_set(prom_buf, prom_index++, "memsize"); 945 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size); 946 947 prom_set(prom_buf, prom_index++, "ememsize"); 948 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size); 949 950 prom_set(prom_buf, prom_index++, "modetty0"); 951 prom_set(prom_buf, prom_index++, "38400n8r"); 952 953 prom_set(prom_buf, prom_index++, "rngseed"); 954 rng_seed_prom_offset = prom_index * ENVP_ENTRY_SIZE + 955 sizeof(uint32_t) * ENVP_NB_ENTRIES; 956 { 957 g_autoptr(GString) hex = rng_seed_hex_new(); 958 prom_set(prom_buf, prom_index++, "%s", hex->str); 959 } 960 961 prom_set(prom_buf, prom_index++, NULL); 962 963 rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR); 964 qemu_register_reset_nosnapshotload(reinitialize_rng_seed, 965 rom_ptr(ENVP_PADDR, prom_size) + rng_seed_prom_offset); 966 967 g_free(prom_buf); 968 return kernel_entry; 969 } 970 971 static void malta_mips_config(MIPSCPU *cpu) 972 { 973 MachineState *ms = MACHINE(qdev_get_machine()); 974 unsigned int smp_cpus = ms->smp.cpus; 975 CPUMIPSState *env = &cpu->env; 976 CPUState *cs = CPU(cpu); 977 978 if (ase_mt_available(env)) { 979 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, 980 CP0MVPC0_PTC, 8, 981 smp_cpus * cs->nr_threads - 1); 982 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, 983 CP0MVPC0_PVPE, 4, smp_cpus - 1); 984 } 985 } 986 987 static int malta_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) 988 { 989 int slot; 990 991 slot = PCI_SLOT(pci_dev->devfn); 992 993 switch (slot) { 994 /* PIIX4 USB */ 995 case 10: 996 return 3; 997 /* AMD 79C973 Ethernet */ 998 case 11: 999 return 1; 1000 /* Crystal 4281 Sound */ 1001 case 12: 1002 return 2; 1003 /* PCI slot 1 to 4 */ 1004 case 18 ... 21: 1005 return ((slot - 18) + irq_num) & 0x03; 1006 /* Unknown device, don't do any translation */ 1007 default: 1008 return irq_num; 1009 } 1010 } 1011 1012 static void main_cpu_reset(void *opaque) 1013 { 1014 MIPSCPU *cpu = opaque; 1015 CPUMIPSState *env = &cpu->env; 1016 1017 cpu_reset(CPU(cpu)); 1018 1019 /* 1020 * The bootloader does not need to be rewritten as it is located in a 1021 * read only location. The kernel location and the arguments table 1022 * location does not change. 1023 */ 1024 if (loaderparams.kernel_filename) { 1025 env->CP0_Status &= ~(1 << CP0St_ERL); 1026 } 1027 1028 malta_mips_config(cpu); 1029 } 1030 1031 static void create_cpu_without_cps(MachineState *ms, MaltaState *s, 1032 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1033 { 1034 CPUMIPSState *env; 1035 MIPSCPU *cpu; 1036 int i; 1037 1038 for (i = 0; i < ms->smp.cpus; i++) { 1039 cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk, 1040 TARGET_BIG_ENDIAN); 1041 1042 /* Init internal devices */ 1043 cpu_mips_irq_init_cpu(cpu); 1044 cpu_mips_clock_init(cpu); 1045 qemu_register_reset(main_cpu_reset, cpu); 1046 } 1047 1048 cpu = MIPS_CPU(first_cpu); 1049 env = &cpu->env; 1050 *i8259_irq = env->irq[2]; 1051 *cbus_irq = env->irq[4]; 1052 } 1053 1054 static void create_cps(MachineState *ms, MaltaState *s, 1055 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1056 { 1057 object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); 1058 object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, 1059 &error_fatal); 1060 object_property_set_bool(OBJECT(&s->cps), "cpu-big-endian", 1061 TARGET_BIG_ENDIAN, &error_abort); 1062 object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus, 1063 &error_fatal); 1064 qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); 1065 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); 1066 1067 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); 1068 1069 *i8259_irq = get_cps_irq(&s->cps, 3); 1070 *cbus_irq = NULL; 1071 } 1072 1073 static void mips_create_cpu(MachineState *ms, MaltaState *s, 1074 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1075 { 1076 if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) { 1077 create_cps(ms, s, cbus_irq, i8259_irq); 1078 } else { 1079 create_cpu_without_cps(ms, s, cbus_irq, i8259_irq); 1080 } 1081 } 1082 1083 static 1084 void mips_malta_init(MachineState *machine) 1085 { 1086 ram_addr_t ram_size = machine->ram_size; 1087 ram_addr_t ram_low_size; 1088 const char *kernel_filename = machine->kernel_filename; 1089 const char *kernel_cmdline = machine->kernel_cmdline; 1090 const char *initrd_filename = machine->initrd_filename; 1091 char *filename; 1092 PFlashCFI01 *fl; 1093 MemoryRegion *system_memory = get_system_memory(); 1094 MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1); 1095 MemoryRegion *ram_low_postio; 1096 MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1); 1097 const size_t smbus_eeprom_size = 8 * 256; 1098 uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size); 1099 uint64_t kernel_entry, bootloader_run_addr; 1100 PCIBus *pci_bus; 1101 ISABus *isa_bus; 1102 qemu_irq cbus_irq, i8259_irq; 1103 I2CBus *smbus; 1104 DriveInfo *dinfo; 1105 int fl_idx = 0; 1106 MaltaState *s; 1107 PCIDevice *piix4; 1108 DeviceState *dev; 1109 1110 s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA)); 1111 sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal); 1112 1113 /* create CPU */ 1114 mips_create_cpu(machine, s, &cbus_irq, &i8259_irq); 1115 1116 /* allocate RAM */ 1117 if (ram_size > 2 * GiB) { 1118 error_report("Too much memory for this machine: %" PRId64 "MB," 1119 " maximum 2048MB", ram_size / MiB); 1120 exit(1); 1121 } 1122 1123 /* register RAM at high address where it is undisturbed by IO */ 1124 memory_region_add_subregion(system_memory, 0x80000000, machine->ram); 1125 1126 /* alias for pre IO hole access */ 1127 memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram", 1128 machine->ram, 0, MIN(ram_size, 256 * MiB)); 1129 memory_region_add_subregion(system_memory, 0, ram_low_preio); 1130 1131 /* alias for post IO hole access, if there is enough RAM */ 1132 if (ram_size > 512 * MiB) { 1133 ram_low_postio = g_new(MemoryRegion, 1); 1134 memory_region_init_alias(ram_low_postio, NULL, 1135 "mips_malta_low_postio.ram", 1136 machine->ram, 512 * MiB, 1137 ram_size - 512 * MiB); 1138 memory_region_add_subregion(system_memory, 512 * MiB, 1139 ram_low_postio); 1140 } 1141 1142 /* FPGA */ 1143 1144 /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ 1145 malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2)); 1146 1147 /* Load firmware in flash / BIOS. */ 1148 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 1149 fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios", 1150 FLASH_SIZE, 1151 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 1152 65536, 1153 4, 0x0000, 0x0000, 0x0000, 0x0000, 1154 TARGET_BIG_ENDIAN); 1155 bios = pflash_cfi01_get_memory(fl); 1156 fl_idx++; 1157 if (kernel_filename) { 1158 ram_low_size = MIN(ram_size, 256 * MiB); 1159 bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS); 1160 1161 /* Write a small bootloader to the flash location. */ 1162 loaderparams.ram_size = ram_size; 1163 loaderparams.ram_low_size = ram_low_size; 1164 loaderparams.kernel_filename = kernel_filename; 1165 loaderparams.kernel_cmdline = kernel_cmdline; 1166 loaderparams.initrd_filename = initrd_filename; 1167 kernel_entry = load_kernel(); 1168 1169 if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { 1170 write_bootloader(memory_region_get_ram_ptr(bios), 1171 bootloader_run_addr, kernel_entry); 1172 } else { 1173 write_bootloader_nanomips(memory_region_get_ram_ptr(bios), 1174 bootloader_run_addr, kernel_entry); 1175 } 1176 } else { 1177 target_long bios_size = FLASH_SIZE; 1178 /* Load firmware from flash. */ 1179 if (!dinfo) { 1180 /* Load a BIOS image. */ 1181 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, 1182 machine->firmware ?: BIOS_FILENAME); 1183 if (filename) { 1184 bios_size = load_image_targphys(filename, FLASH_ADDRESS, 1185 BIOS_SIZE); 1186 g_free(filename); 1187 } else { 1188 bios_size = -1; 1189 } 1190 if ((bios_size < 0 || bios_size > BIOS_SIZE) && 1191 machine->firmware && !qtest_enabled()) { 1192 error_report("Could not load MIPS bios '%s'", machine->firmware); 1193 exit(1); 1194 } 1195 } 1196 /* 1197 * In little endian mode the 32bit words in the bios are swapped, 1198 * a neat trick which allows bi-endian firmware. 1199 */ 1200 #if !TARGET_BIG_ENDIAN 1201 { 1202 uint32_t *end, *addr; 1203 const size_t swapsize = MIN(bios_size, 0x3e0000); 1204 addr = rom_ptr(FLASH_ADDRESS, swapsize); 1205 if (!addr) { 1206 addr = memory_region_get_ram_ptr(bios); 1207 } 1208 end = (void *)addr + swapsize; 1209 while (addr < end) { 1210 bswap32s(addr); 1211 addr++; 1212 } 1213 } 1214 #endif 1215 } 1216 1217 /* 1218 * Map the BIOS at a 2nd physical location, as on the real board. 1219 * Copy it so that we can patch in the MIPS revision, which cannot be 1220 * handled by an overlapping region as the resulting ROM code subpage 1221 * regions are not executable. 1222 */ 1223 memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE, 1224 &error_fatal); 1225 if (!rom_copy(memory_region_get_ram_ptr(bios_copy), 1226 FLASH_ADDRESS, BIOS_SIZE)) { 1227 memcpy(memory_region_get_ram_ptr(bios_copy), 1228 memory_region_get_ram_ptr(bios), BIOS_SIZE); 1229 } 1230 memory_region_set_readonly(bios_copy, true); 1231 memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy); 1232 1233 /* Board ID = 0x420 (Malta Board with CoreLV) */ 1234 stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); 1235 1236 /* Northbridge */ 1237 dev = qdev_new("gt64120"); 1238 qdev_prop_set_bit(dev, "cpu-little-endian", !TARGET_BIG_ENDIAN); 1239 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1240 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); 1241 pci_bus_map_irqs(pci_bus, malta_pci_slot_get_pirq); 1242 1243 /* Southbridge */ 1244 piix4 = pci_new_multifunction(PIIX4_PCI_DEVFN, TYPE_PIIX4_PCI_DEVICE); 1245 qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100); 1246 pci_realize_and_unref(piix4, pci_bus, &error_fatal); 1247 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); 1248 1249 dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide")); 1250 pci_ide_create_devs(PCI_DEVICE(dev)); 1251 1252 /* Interrupt controller */ 1253 qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq); 1254 1255 /* generate SPD EEPROM data */ 1256 dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm")); 1257 smbus = I2C_BUS(qdev_get_child_bus(dev, "i2c")); 1258 generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); 1259 generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]); 1260 smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size); 1261 g_free(smbus_eeprom_buf); 1262 1263 /* Super I/O: SMS FDC37M817 */ 1264 isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO); 1265 1266 /* Network card */ 1267 network_init(pci_bus); 1268 1269 /* Optional PCI video card */ 1270 pci_vga_init(pci_bus); 1271 } 1272 1273 static void mips_malta_instance_init(Object *obj) 1274 { 1275 MaltaState *s = MIPS_MALTA(obj); 1276 1277 s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); 1278 clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */ 1279 } 1280 1281 static const TypeInfo mips_malta_device = { 1282 .name = TYPE_MIPS_MALTA, 1283 .parent = TYPE_SYS_BUS_DEVICE, 1284 .instance_size = sizeof(MaltaState), 1285 .instance_init = mips_malta_instance_init, 1286 }; 1287 1288 GlobalProperty malta_compat[] = { 1289 { "PIIX4_PM", "memory-hotplug-support", "off" }, 1290 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 1291 { "PIIX4_PM", "acpi-root-pci-hotplug", "off" }, 1292 { "PIIX4_PM", "x-not-migrate-acpi-index", "true" }, 1293 }; 1294 const size_t malta_compat_len = G_N_ELEMENTS(malta_compat); 1295 1296 static void mips_malta_machine_init(MachineClass *mc) 1297 { 1298 mc->desc = "MIPS Malta Core LV"; 1299 mc->init = mips_malta_init; 1300 mc->block_default_type = IF_IDE; 1301 mc->max_cpus = 16; 1302 mc->is_default = true; 1303 #ifdef TARGET_MIPS64 1304 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc"); 1305 #else 1306 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf"); 1307 #endif 1308 mc->default_ram_id = "mips_malta.ram"; 1309 compat_props_add(mc->compat_props, malta_compat, malta_compat_len); 1310 } 1311 1312 DEFINE_MACHINE("malta", mips_malta_machine_init) 1313 1314 static void mips_malta_register_types(void) 1315 { 1316 type_register_static(&mips_malta_device); 1317 } 1318 1319 type_init(mips_malta_register_types) 1320