1 /* 2 * QEMU MIPS Jazz support 3 * 4 * Copyright (c) 2007-2008 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/mips/mips.h" 28 #include "hw/mips/cpudevs.h" 29 #include "hw/i386/pc.h" 30 #include "hw/char/serial.h" 31 #include "hw/isa/isa.h" 32 #include "hw/block/fdc.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/arch_init.h" 35 #include "hw/boards.h" 36 #include "net/net.h" 37 #include "hw/scsi/esp.h" 38 #include "hw/mips/bios.h" 39 #include "hw/loader.h" 40 #include "hw/timer/mc146818rtc.h" 41 #include "hw/timer/i8254.h" 42 #include "hw/display/vga.h" 43 #include "hw/audio/pcspk.h" 44 #include "sysemu/block-backend.h" 45 #include "hw/sysbus.h" 46 #include "exec/address-spaces.h" 47 #include "sysemu/qtest.h" 48 #include "qapi/error.h" 49 #include "qemu/error-report.h" 50 #include "qemu/help_option.h" 51 52 enum jazz_model_e 53 { 54 JAZZ_MAGNUM, 55 JAZZ_PICA61, 56 }; 57 58 static void main_cpu_reset(void *opaque) 59 { 60 MIPSCPU *cpu = opaque; 61 62 cpu_reset(CPU(cpu)); 63 } 64 65 static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size) 66 { 67 uint8_t val; 68 address_space_read(&address_space_memory, 0x90000071, 69 MEMTXATTRS_UNSPECIFIED, &val, 1); 70 return val; 71 } 72 73 static void rtc_write(void *opaque, hwaddr addr, 74 uint64_t val, unsigned size) 75 { 76 uint8_t buf = val & 0xff; 77 address_space_write(&address_space_memory, 0x90000071, 78 MEMTXATTRS_UNSPECIFIED, &buf, 1); 79 } 80 81 static const MemoryRegionOps rtc_ops = { 82 .read = rtc_read, 83 .write = rtc_write, 84 .endianness = DEVICE_NATIVE_ENDIAN, 85 }; 86 87 static uint64_t dma_dummy_read(void *opaque, hwaddr addr, 88 unsigned size) 89 { 90 /* Nothing to do. That is only to ensure that 91 * the current DMA acknowledge cycle is completed. */ 92 return 0xff; 93 } 94 95 static void dma_dummy_write(void *opaque, hwaddr addr, 96 uint64_t val, unsigned size) 97 { 98 /* Nothing to do. That is only to ensure that 99 * the current DMA acknowledge cycle is completed. */ 100 } 101 102 static const MemoryRegionOps dma_dummy_ops = { 103 .read = dma_dummy_read, 104 .write = dma_dummy_write, 105 .endianness = DEVICE_NATIVE_ENDIAN, 106 }; 107 108 #define MAGNUM_BIOS_SIZE_MAX 0x7e000 109 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) 110 111 static CPUUnassignedAccess real_do_unassigned_access; 112 static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr, 113 bool is_write, bool is_exec, 114 int opaque, unsigned size) 115 { 116 if (!is_exec) { 117 /* ignore invalid access (ie do not raise exception) */ 118 return; 119 } 120 (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size); 121 } 122 123 static void mips_jazz_init(MachineState *machine, 124 enum jazz_model_e jazz_model) 125 { 126 MemoryRegion *address_space = get_system_memory(); 127 char *filename; 128 int bios_size, n; 129 MIPSCPU *cpu; 130 CPUClass *cc; 131 CPUMIPSState *env; 132 qemu_irq *i8259; 133 rc4030_dma *dmas; 134 IOMMUMemoryRegion *rc4030_dma_mr; 135 MemoryRegion *isa_mem = g_new(MemoryRegion, 1); 136 MemoryRegion *isa_io = g_new(MemoryRegion, 1); 137 MemoryRegion *rtc = g_new(MemoryRegion, 1); 138 MemoryRegion *i8042 = g_new(MemoryRegion, 1); 139 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1); 140 NICInfo *nd; 141 DeviceState *dev, *rc4030; 142 SysBusDevice *sysbus; 143 ISABus *isa_bus; 144 ISADevice *pit; 145 DriveInfo *fds[MAX_FD]; 146 qemu_irq esp_reset, dma_enable; 147 MemoryRegion *ram = g_new(MemoryRegion, 1); 148 MemoryRegion *bios = g_new(MemoryRegion, 1); 149 MemoryRegion *bios2 = g_new(MemoryRegion, 1); 150 151 /* init CPUs */ 152 cpu = MIPS_CPU(cpu_create(machine->cpu_type)); 153 env = &cpu->env; 154 qemu_register_reset(main_cpu_reset, cpu); 155 156 /* Chipset returns 0 in invalid reads and do not raise data exceptions. 157 * However, we can't simply add a global memory region to catch 158 * everything, as memory core directly call unassigned_mem_read/write 159 * on some invalid accesses, which call do_unassigned_access on the 160 * CPU, which raise an exception. 161 * Handle that case by hijacking the do_unassigned_access method on 162 * the CPU, and do not raise exceptions for data access. */ 163 cc = CPU_GET_CLASS(cpu); 164 real_do_unassigned_access = cc->do_unassigned_access; 165 cc->do_unassigned_access = mips_jazz_do_unassigned_access; 166 167 /* allocate RAM */ 168 memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram", 169 machine->ram_size); 170 memory_region_add_subregion(address_space, 0, ram); 171 172 memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, 173 &error_fatal); 174 memory_region_set_readonly(bios, true); 175 memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios, 176 0, MAGNUM_BIOS_SIZE); 177 memory_region_add_subregion(address_space, 0x1fc00000LL, bios); 178 memory_region_add_subregion(address_space, 0xfff00000LL, bios2); 179 180 /* load the BIOS image. */ 181 if (bios_name == NULL) 182 bios_name = BIOS_FILENAME; 183 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 184 if (filename) { 185 bios_size = load_image_targphys(filename, 0xfff00000LL, 186 MAGNUM_BIOS_SIZE); 187 g_free(filename); 188 } else { 189 bios_size = -1; 190 } 191 if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) { 192 error_report("Could not load MIPS bios '%s'", bios_name); 193 exit(1); 194 } 195 196 /* Init CPU internal devices */ 197 cpu_mips_irq_init_cpu(cpu); 198 cpu_mips_clock_init(cpu); 199 200 /* Chipset */ 201 rc4030 = rc4030_init(&dmas, &rc4030_dma_mr); 202 sysbus = SYS_BUS_DEVICE(rc4030); 203 sysbus_connect_irq(sysbus, 0, env->irq[6]); 204 sysbus_connect_irq(sysbus, 1, env->irq[3]); 205 memory_region_add_subregion(address_space, 0x80000000, 206 sysbus_mmio_get_region(sysbus, 0)); 207 memory_region_add_subregion(address_space, 0xf0000000, 208 sysbus_mmio_get_region(sysbus, 1)); 209 memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000); 210 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); 211 212 /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */ 213 memory_region_init(isa_io, NULL, "isa-io", 0x00010000); 214 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000); 215 memory_region_add_subregion(address_space, 0x90000000, isa_io); 216 memory_region_add_subregion(address_space, 0x91000000, isa_mem); 217 isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort); 218 219 /* ISA devices */ 220 i8259 = i8259_init(isa_bus, env->irq[4]); 221 isa_bus_irqs(isa_bus, i8259); 222 DMA_init(isa_bus, 0); 223 pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); 224 pcspk_init(isa_bus, pit); 225 226 /* Video card */ 227 switch (jazz_model) { 228 case JAZZ_MAGNUM: 229 dev = qdev_create(NULL, "sysbus-g364"); 230 qdev_init_nofail(dev); 231 sysbus = SYS_BUS_DEVICE(dev); 232 sysbus_mmio_map(sysbus, 0, 0x60080000); 233 sysbus_mmio_map(sysbus, 1, 0x40000000); 234 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3)); 235 { 236 /* Simple ROM, so user doesn't have to provide one */ 237 MemoryRegion *rom_mr = g_new(MemoryRegion, 1); 238 memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000, 239 &error_fatal); 240 memory_region_set_readonly(rom_mr, true); 241 uint8_t *rom = memory_region_get_ram_ptr(rom_mr); 242 memory_region_add_subregion(address_space, 0x60000000, rom_mr); 243 rom[0] = 0x10; /* Mips G364 */ 244 } 245 break; 246 case JAZZ_PICA61: 247 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory()); 248 break; 249 default: 250 break; 251 } 252 253 /* Network controller */ 254 for (n = 0; n < nb_nics; n++) { 255 nd = &nd_table[n]; 256 if (!nd->model) 257 nd->model = g_strdup("dp83932"); 258 if (strcmp(nd->model, "dp83932") == 0) { 259 qemu_check_nic_model(nd, "dp83932"); 260 261 dev = qdev_create(NULL, "dp8393x"); 262 qdev_set_nic_properties(dev, nd); 263 qdev_prop_set_uint8(dev, "it_shift", 2); 264 qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr); 265 qdev_init_nofail(dev); 266 sysbus = SYS_BUS_DEVICE(dev); 267 sysbus_mmio_map(sysbus, 0, 0x80001000); 268 sysbus_mmio_map(sysbus, 1, 0x8000b000); 269 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); 270 break; 271 } else if (is_help_option(nd->model)) { 272 error_report("Supported NICs: dp83932"); 273 exit(1); 274 } else { 275 error_report("Unsupported NIC: %s", nd->model); 276 exit(1); 277 } 278 } 279 280 /* SCSI adapter */ 281 esp_init(0x80002000, 0, 282 rc4030_dma_read, rc4030_dma_write, dmas[0], 283 qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable); 284 285 /* Floppy */ 286 for (n = 0; n < MAX_FD; n++) { 287 fds[n] = drive_get(IF_FLOPPY, 0, n); 288 } 289 /* FIXME: we should enable DMA with a custom IsaDma device */ 290 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds); 291 292 /* Real time clock */ 293 mc146818_rtc_init(isa_bus, 1980, NULL); 294 memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000); 295 memory_region_add_subregion(address_space, 0x80004000, rtc); 296 297 /* Keyboard (i8042) */ 298 i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7), 299 i8042, 0x1000, 0x1); 300 memory_region_add_subregion(address_space, 0x80005000, i8042); 301 302 /* Serial ports */ 303 if (serial_hds[0]) { 304 serial_mm_init(address_space, 0x80006000, 0, 305 qdev_get_gpio_in(rc4030, 8), 8000000/16, 306 serial_hds[0], DEVICE_NATIVE_ENDIAN); 307 } 308 if (serial_hds[1]) { 309 serial_mm_init(address_space, 0x80007000, 0, 310 qdev_get_gpio_in(rc4030, 9), 8000000/16, 311 serial_hds[1], DEVICE_NATIVE_ENDIAN); 312 } 313 314 /* Parallel port */ 315 if (parallel_hds[0]) 316 parallel_mm_init(address_space, 0x80008000, 0, 317 qdev_get_gpio_in(rc4030, 0), parallel_hds[0]); 318 319 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ 320 321 /* NVRAM */ 322 dev = qdev_create(NULL, "ds1225y"); 323 qdev_init_nofail(dev); 324 sysbus = SYS_BUS_DEVICE(dev); 325 sysbus_mmio_map(sysbus, 0, 0x80009000); 326 327 /* LED indicator */ 328 sysbus_create_simple("jazz-led", 0x8000f000, NULL); 329 } 330 331 static 332 void mips_magnum_init(MachineState *machine) 333 { 334 mips_jazz_init(machine, JAZZ_MAGNUM); 335 } 336 337 static 338 void mips_pica61_init(MachineState *machine) 339 { 340 mips_jazz_init(machine, JAZZ_PICA61); 341 } 342 343 static void mips_magnum_class_init(ObjectClass *oc, void *data) 344 { 345 MachineClass *mc = MACHINE_CLASS(oc); 346 347 mc->desc = "MIPS Magnum"; 348 mc->init = mips_magnum_init; 349 mc->block_default_type = IF_SCSI; 350 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); 351 } 352 353 static const TypeInfo mips_magnum_type = { 354 .name = MACHINE_TYPE_NAME("magnum"), 355 .parent = TYPE_MACHINE, 356 .class_init = mips_magnum_class_init, 357 }; 358 359 static void mips_pica61_class_init(ObjectClass *oc, void *data) 360 { 361 MachineClass *mc = MACHINE_CLASS(oc); 362 363 mc->desc = "Acer Pica 61"; 364 mc->init = mips_pica61_init; 365 mc->block_default_type = IF_SCSI; 366 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); 367 } 368 369 static const TypeInfo mips_pica61_type = { 370 .name = MACHINE_TYPE_NAME("pica61"), 371 .parent = TYPE_MACHINE, 372 .class_init = mips_pica61_class_init, 373 }; 374 375 static void mips_jazz_machine_init(void) 376 { 377 type_register_static(&mips_magnum_type); 378 type_register_static(&mips_pica61_type); 379 } 380 381 type_init(mips_jazz_machine_init) 382