1 /* 2 * QEMU MIPS Jazz support 3 * 4 * Copyright (c) 2007-2008 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "hw/hw.h" 26 #include "hw/mips/mips.h" 27 #include "hw/mips/cpudevs.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/isa/isa.h" 31 #include "hw/block/fdc.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/arch_init.h" 34 #include "hw/boards.h" 35 #include "net/net.h" 36 #include "hw/scsi/esp.h" 37 #include "hw/mips/bios.h" 38 #include "hw/loader.h" 39 #include "hw/timer/mc146818rtc.h" 40 #include "hw/timer/i8254.h" 41 #include "hw/audio/pcspk.h" 42 #include "sysemu/block-backend.h" 43 #include "hw/sysbus.h" 44 #include "exec/address-spaces.h" 45 #include "sysemu/qtest.h" 46 #include "qemu/error-report.h" 47 48 enum jazz_model_e 49 { 50 JAZZ_MAGNUM, 51 JAZZ_PICA61, 52 }; 53 54 static void main_cpu_reset(void *opaque) 55 { 56 MIPSCPU *cpu = opaque; 57 58 cpu_reset(CPU(cpu)); 59 } 60 61 static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size) 62 { 63 uint8_t val; 64 address_space_read(&address_space_memory, 0x90000071, 65 MEMTXATTRS_UNSPECIFIED, &val, 1); 66 return val; 67 } 68 69 static void rtc_write(void *opaque, hwaddr addr, 70 uint64_t val, unsigned size) 71 { 72 uint8_t buf = val & 0xff; 73 address_space_write(&address_space_memory, 0x90000071, 74 MEMTXATTRS_UNSPECIFIED, &buf, 1); 75 } 76 77 static const MemoryRegionOps rtc_ops = { 78 .read = rtc_read, 79 .write = rtc_write, 80 .endianness = DEVICE_NATIVE_ENDIAN, 81 }; 82 83 static uint64_t dma_dummy_read(void *opaque, hwaddr addr, 84 unsigned size) 85 { 86 /* Nothing to do. That is only to ensure that 87 * the current DMA acknowledge cycle is completed. */ 88 return 0xff; 89 } 90 91 static void dma_dummy_write(void *opaque, hwaddr addr, 92 uint64_t val, unsigned size) 93 { 94 /* Nothing to do. That is only to ensure that 95 * the current DMA acknowledge cycle is completed. */ 96 } 97 98 static const MemoryRegionOps dma_dummy_ops = { 99 .read = dma_dummy_read, 100 .write = dma_dummy_write, 101 .endianness = DEVICE_NATIVE_ENDIAN, 102 }; 103 104 #define MAGNUM_BIOS_SIZE_MAX 0x7e000 105 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) 106 107 static CPUUnassignedAccess real_do_unassigned_access; 108 static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr, 109 bool is_write, bool is_exec, 110 int opaque, unsigned size) 111 { 112 if (!is_exec) { 113 /* ignore invalid access (ie do not raise exception) */ 114 return; 115 } 116 (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size); 117 } 118 119 static void mips_jazz_init(MachineState *machine, 120 enum jazz_model_e jazz_model) 121 { 122 MemoryRegion *address_space = get_system_memory(); 123 const char *cpu_model = machine->cpu_model; 124 char *filename; 125 int bios_size, n; 126 MIPSCPU *cpu; 127 CPUClass *cc; 128 CPUMIPSState *env; 129 qemu_irq *i8259; 130 rc4030_dma *dmas; 131 MemoryRegion *rc4030_dma_mr; 132 MemoryRegion *isa_mem = g_new(MemoryRegion, 1); 133 MemoryRegion *isa_io = g_new(MemoryRegion, 1); 134 MemoryRegion *rtc = g_new(MemoryRegion, 1); 135 MemoryRegion *i8042 = g_new(MemoryRegion, 1); 136 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1); 137 NICInfo *nd; 138 DeviceState *dev, *rc4030; 139 SysBusDevice *sysbus; 140 ISABus *isa_bus; 141 ISADevice *pit; 142 DriveInfo *fds[MAX_FD]; 143 qemu_irq esp_reset, dma_enable; 144 MemoryRegion *ram = g_new(MemoryRegion, 1); 145 MemoryRegion *bios = g_new(MemoryRegion, 1); 146 MemoryRegion *bios2 = g_new(MemoryRegion, 1); 147 148 /* init CPUs */ 149 if (cpu_model == NULL) { 150 cpu_model = "R4000"; 151 } 152 cpu = cpu_mips_init(cpu_model); 153 if (cpu == NULL) { 154 fprintf(stderr, "Unable to find CPU definition\n"); 155 exit(1); 156 } 157 env = &cpu->env; 158 qemu_register_reset(main_cpu_reset, cpu); 159 160 /* Chipset returns 0 in invalid reads and do not raise data exceptions. 161 * However, we can't simply add a global memory region to catch 162 * everything, as memory core directly call unassigned_mem_read/write 163 * on some invalid accesses, which call do_unassigned_access on the 164 * CPU, which raise an exception. 165 * Handle that case by hijacking the do_unassigned_access method on 166 * the CPU, and do not raise exceptions for data access. */ 167 cc = CPU_GET_CLASS(cpu); 168 real_do_unassigned_access = cc->do_unassigned_access; 169 cc->do_unassigned_access = mips_jazz_do_unassigned_access; 170 171 /* allocate RAM */ 172 memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram", 173 machine->ram_size); 174 memory_region_add_subregion(address_space, 0, ram); 175 176 memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, 177 &error_fatal); 178 vmstate_register_ram_global(bios); 179 memory_region_set_readonly(bios, true); 180 memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios, 181 0, MAGNUM_BIOS_SIZE); 182 memory_region_add_subregion(address_space, 0x1fc00000LL, bios); 183 memory_region_add_subregion(address_space, 0xfff00000LL, bios2); 184 185 /* load the BIOS image. */ 186 if (bios_name == NULL) 187 bios_name = BIOS_FILENAME; 188 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 189 if (filename) { 190 bios_size = load_image_targphys(filename, 0xfff00000LL, 191 MAGNUM_BIOS_SIZE); 192 g_free(filename); 193 } else { 194 bios_size = -1; 195 } 196 if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) { 197 error_report("Could not load MIPS bios '%s'", bios_name); 198 exit(1); 199 } 200 201 /* Init CPU internal devices */ 202 cpu_mips_irq_init_cpu(env); 203 cpu_mips_clock_init(env); 204 205 /* Chipset */ 206 rc4030 = rc4030_init(&dmas, &rc4030_dma_mr); 207 sysbus = SYS_BUS_DEVICE(rc4030); 208 sysbus_connect_irq(sysbus, 0, env->irq[6]); 209 sysbus_connect_irq(sysbus, 1, env->irq[3]); 210 memory_region_add_subregion(address_space, 0x80000000, 211 sysbus_mmio_get_region(sysbus, 0)); 212 memory_region_add_subregion(address_space, 0xf0000000, 213 sysbus_mmio_get_region(sysbus, 1)); 214 memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000); 215 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); 216 217 /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */ 218 memory_region_init(isa_io, NULL, "isa-io", 0x00010000); 219 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000); 220 memory_region_add_subregion(address_space, 0x90000000, isa_io); 221 memory_region_add_subregion(address_space, 0x91000000, isa_mem); 222 isa_bus = isa_bus_new(NULL, isa_mem, isa_io); 223 224 /* ISA devices */ 225 i8259 = i8259_init(isa_bus, env->irq[4]); 226 isa_bus_irqs(isa_bus, i8259); 227 DMA_init(0); 228 pit = pit_init(isa_bus, 0x40, 0, NULL); 229 pcspk_init(isa_bus, pit); 230 231 /* Video card */ 232 switch (jazz_model) { 233 case JAZZ_MAGNUM: 234 dev = qdev_create(NULL, "sysbus-g364"); 235 qdev_init_nofail(dev); 236 sysbus = SYS_BUS_DEVICE(dev); 237 sysbus_mmio_map(sysbus, 0, 0x60080000); 238 sysbus_mmio_map(sysbus, 1, 0x40000000); 239 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3)); 240 { 241 /* Simple ROM, so user doesn't have to provide one */ 242 MemoryRegion *rom_mr = g_new(MemoryRegion, 1); 243 memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000, 244 &error_fatal); 245 vmstate_register_ram_global(rom_mr); 246 memory_region_set_readonly(rom_mr, true); 247 uint8_t *rom = memory_region_get_ram_ptr(rom_mr); 248 memory_region_add_subregion(address_space, 0x60000000, rom_mr); 249 rom[0] = 0x10; /* Mips G364 */ 250 } 251 break; 252 case JAZZ_PICA61: 253 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory()); 254 break; 255 default: 256 break; 257 } 258 259 /* Network controller */ 260 for (n = 0; n < nb_nics; n++) { 261 nd = &nd_table[n]; 262 if (!nd->model) 263 nd->model = g_strdup("dp83932"); 264 if (strcmp(nd->model, "dp83932") == 0) { 265 qemu_check_nic_model(nd, "dp83932"); 266 267 dev = qdev_create(NULL, "dp8393x"); 268 qdev_set_nic_properties(dev, nd); 269 qdev_prop_set_uint8(dev, "it_shift", 2); 270 qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr); 271 qdev_init_nofail(dev); 272 sysbus = SYS_BUS_DEVICE(dev); 273 sysbus_mmio_map(sysbus, 0, 0x80001000); 274 sysbus_mmio_map(sysbus, 1, 0x8000b000); 275 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); 276 break; 277 } else if (is_help_option(nd->model)) { 278 fprintf(stderr, "qemu: Supported NICs: dp83932\n"); 279 exit(1); 280 } else { 281 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); 282 exit(1); 283 } 284 } 285 286 /* SCSI adapter */ 287 esp_init(0x80002000, 0, 288 rc4030_dma_read, rc4030_dma_write, dmas[0], 289 qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable); 290 291 /* Floppy */ 292 if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) { 293 fprintf(stderr, "qemu: too many floppy drives\n"); 294 exit(1); 295 } 296 for (n = 0; n < MAX_FD; n++) { 297 fds[n] = drive_get(IF_FLOPPY, 0, n); 298 } 299 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), 0, 0x80003000, fds); 300 301 /* Real time clock */ 302 rtc_init(isa_bus, 1980, NULL); 303 memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000); 304 memory_region_add_subregion(address_space, 0x80004000, rtc); 305 306 /* Keyboard (i8042) */ 307 i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7), 308 i8042, 0x1000, 0x1); 309 memory_region_add_subregion(address_space, 0x80005000, i8042); 310 311 /* Serial ports */ 312 if (serial_hds[0]) { 313 serial_mm_init(address_space, 0x80006000, 0, 314 qdev_get_gpio_in(rc4030, 8), 8000000/16, 315 serial_hds[0], DEVICE_NATIVE_ENDIAN); 316 } 317 if (serial_hds[1]) { 318 serial_mm_init(address_space, 0x80007000, 0, 319 qdev_get_gpio_in(rc4030, 9), 8000000/16, 320 serial_hds[1], DEVICE_NATIVE_ENDIAN); 321 } 322 323 /* Parallel port */ 324 if (parallel_hds[0]) 325 parallel_mm_init(address_space, 0x80008000, 0, 326 qdev_get_gpio_in(rc4030, 0), parallel_hds[0]); 327 328 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ 329 330 /* NVRAM */ 331 dev = qdev_create(NULL, "ds1225y"); 332 qdev_init_nofail(dev); 333 sysbus = SYS_BUS_DEVICE(dev); 334 sysbus_mmio_map(sysbus, 0, 0x80009000); 335 336 /* LED indicator */ 337 sysbus_create_simple("jazz-led", 0x8000f000, NULL); 338 } 339 340 static 341 void mips_magnum_init(MachineState *machine) 342 { 343 mips_jazz_init(machine, JAZZ_MAGNUM); 344 } 345 346 static 347 void mips_pica61_init(MachineState *machine) 348 { 349 mips_jazz_init(machine, JAZZ_PICA61); 350 } 351 352 static void mips_magnum_machine_init(MachineClass *mc) 353 { 354 mc->desc = "MIPS Magnum"; 355 mc->init = mips_magnum_init; 356 mc->block_default_type = IF_SCSI; 357 } 358 359 DEFINE_MACHINE("magnum", mips_magnum_machine_init) 360 361 static void mips_pica61_machine_init(MachineClass *mc) 362 { 363 mc->desc = "Acer Pica 61"; 364 mc->init = mips_pica61_init; 365 mc->block_default_type = IF_SCSI; 366 } 367 368 DEFINE_MACHINE("pica61", mips_pica61_machine_init) 369