1 /* 2 * QEMU MIPS Jazz support 3 * 4 * Copyright (c) 2007-2008 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/mips/mips.h" 28 #include "hw/mips/cpudevs.h" 29 #include "hw/i386/pc.h" 30 #include "hw/dma/i8257.h" 31 #include "hw/char/serial.h" 32 #include "hw/char/parallel.h" 33 #include "hw/isa/isa.h" 34 #include "hw/block/fdc.h" 35 #include "sysemu/sysemu.h" 36 #include "sysemu/arch_init.h" 37 #include "hw/boards.h" 38 #include "net/net.h" 39 #include "hw/scsi/esp.h" 40 #include "hw/mips/bios.h" 41 #include "hw/loader.h" 42 #include "hw/timer/mc146818rtc.h" 43 #include "hw/timer/i8254.h" 44 #include "hw/display/vga.h" 45 #include "hw/audio/pcspk.h" 46 #include "hw/sysbus.h" 47 #include "exec/address-spaces.h" 48 #include "sysemu/qtest.h" 49 #include "qapi/error.h" 50 #include "qemu/error-report.h" 51 #include "qemu/help_option.h" 52 53 enum jazz_model_e 54 { 55 JAZZ_MAGNUM, 56 JAZZ_PICA61, 57 }; 58 59 static void main_cpu_reset(void *opaque) 60 { 61 MIPSCPU *cpu = opaque; 62 63 cpu_reset(CPU(cpu)); 64 } 65 66 static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size) 67 { 68 uint8_t val; 69 address_space_read(&address_space_memory, 0x90000071, 70 MEMTXATTRS_UNSPECIFIED, &val, 1); 71 return val; 72 } 73 74 static void rtc_write(void *opaque, hwaddr addr, 75 uint64_t val, unsigned size) 76 { 77 uint8_t buf = val & 0xff; 78 address_space_write(&address_space_memory, 0x90000071, 79 MEMTXATTRS_UNSPECIFIED, &buf, 1); 80 } 81 82 static const MemoryRegionOps rtc_ops = { 83 .read = rtc_read, 84 .write = rtc_write, 85 .endianness = DEVICE_NATIVE_ENDIAN, 86 }; 87 88 static uint64_t dma_dummy_read(void *opaque, hwaddr addr, 89 unsigned size) 90 { 91 /* Nothing to do. That is only to ensure that 92 * the current DMA acknowledge cycle is completed. */ 93 return 0xff; 94 } 95 96 static void dma_dummy_write(void *opaque, hwaddr addr, 97 uint64_t val, unsigned size) 98 { 99 /* Nothing to do. That is only to ensure that 100 * the current DMA acknowledge cycle is completed. */ 101 } 102 103 static const MemoryRegionOps dma_dummy_ops = { 104 .read = dma_dummy_read, 105 .write = dma_dummy_write, 106 .endianness = DEVICE_NATIVE_ENDIAN, 107 }; 108 109 #define MAGNUM_BIOS_SIZE_MAX 0x7e000 110 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) 111 112 static CPUUnassignedAccess real_do_unassigned_access; 113 static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr, 114 bool is_write, bool is_exec, 115 int opaque, unsigned size) 116 { 117 if (!is_exec) { 118 /* ignore invalid access (ie do not raise exception) */ 119 return; 120 } 121 (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size); 122 } 123 124 static void mips_jazz_init(MachineState *machine, 125 enum jazz_model_e jazz_model) 126 { 127 MemoryRegion *address_space = get_system_memory(); 128 char *filename; 129 int bios_size, n; 130 MIPSCPU *cpu; 131 CPUClass *cc; 132 CPUMIPSState *env; 133 qemu_irq *i8259; 134 rc4030_dma *dmas; 135 IOMMUMemoryRegion *rc4030_dma_mr; 136 MemoryRegion *isa_mem = g_new(MemoryRegion, 1); 137 MemoryRegion *isa_io = g_new(MemoryRegion, 1); 138 MemoryRegion *rtc = g_new(MemoryRegion, 1); 139 MemoryRegion *i8042 = g_new(MemoryRegion, 1); 140 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1); 141 NICInfo *nd; 142 DeviceState *dev, *rc4030; 143 SysBusDevice *sysbus; 144 ISABus *isa_bus; 145 ISADevice *pit; 146 DriveInfo *fds[MAX_FD]; 147 qemu_irq esp_reset, dma_enable; 148 MemoryRegion *ram = g_new(MemoryRegion, 1); 149 MemoryRegion *bios = g_new(MemoryRegion, 1); 150 MemoryRegion *bios2 = g_new(MemoryRegion, 1); 151 ESPState *esp; 152 153 /* init CPUs */ 154 cpu = MIPS_CPU(cpu_create(machine->cpu_type)); 155 env = &cpu->env; 156 qemu_register_reset(main_cpu_reset, cpu); 157 158 /* Chipset returns 0 in invalid reads and do not raise data exceptions. 159 * However, we can't simply add a global memory region to catch 160 * everything, as memory core directly call unassigned_mem_read/write 161 * on some invalid accesses, which call do_unassigned_access on the 162 * CPU, which raise an exception. 163 * Handle that case by hijacking the do_unassigned_access method on 164 * the CPU, and do not raise exceptions for data access. */ 165 cc = CPU_GET_CLASS(cpu); 166 real_do_unassigned_access = cc->do_unassigned_access; 167 cc->do_unassigned_access = mips_jazz_do_unassigned_access; 168 169 /* allocate RAM */ 170 memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram", 171 machine->ram_size); 172 memory_region_add_subregion(address_space, 0, ram); 173 174 memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, 175 &error_fatal); 176 memory_region_set_readonly(bios, true); 177 memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios, 178 0, MAGNUM_BIOS_SIZE); 179 memory_region_add_subregion(address_space, 0x1fc00000LL, bios); 180 memory_region_add_subregion(address_space, 0xfff00000LL, bios2); 181 182 /* load the BIOS image. */ 183 if (bios_name == NULL) 184 bios_name = BIOS_FILENAME; 185 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 186 if (filename) { 187 bios_size = load_image_targphys(filename, 0xfff00000LL, 188 MAGNUM_BIOS_SIZE); 189 g_free(filename); 190 } else { 191 bios_size = -1; 192 } 193 if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) { 194 error_report("Could not load MIPS bios '%s'", bios_name); 195 exit(1); 196 } 197 198 /* Init CPU internal devices */ 199 cpu_mips_irq_init_cpu(cpu); 200 cpu_mips_clock_init(cpu); 201 202 /* Chipset */ 203 rc4030 = rc4030_init(&dmas, &rc4030_dma_mr); 204 sysbus = SYS_BUS_DEVICE(rc4030); 205 sysbus_connect_irq(sysbus, 0, env->irq[6]); 206 sysbus_connect_irq(sysbus, 1, env->irq[3]); 207 memory_region_add_subregion(address_space, 0x80000000, 208 sysbus_mmio_get_region(sysbus, 0)); 209 memory_region_add_subregion(address_space, 0xf0000000, 210 sysbus_mmio_get_region(sysbus, 1)); 211 memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000); 212 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); 213 214 /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */ 215 memory_region_init(isa_io, NULL, "isa-io", 0x00010000); 216 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000); 217 memory_region_add_subregion(address_space, 0x90000000, isa_io); 218 memory_region_add_subregion(address_space, 0x91000000, isa_mem); 219 isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort); 220 221 /* ISA devices */ 222 i8259 = i8259_init(isa_bus, env->irq[4]); 223 isa_bus_irqs(isa_bus, i8259); 224 i8257_dma_init(isa_bus, 0); 225 pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); 226 pcspk_init(isa_bus, pit); 227 228 /* Video card */ 229 switch (jazz_model) { 230 case JAZZ_MAGNUM: 231 dev = qdev_create(NULL, "sysbus-g364"); 232 qdev_init_nofail(dev); 233 sysbus = SYS_BUS_DEVICE(dev); 234 sysbus_mmio_map(sysbus, 0, 0x60080000); 235 sysbus_mmio_map(sysbus, 1, 0x40000000); 236 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3)); 237 { 238 /* Simple ROM, so user doesn't have to provide one */ 239 MemoryRegion *rom_mr = g_new(MemoryRegion, 1); 240 memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000, 241 &error_fatal); 242 memory_region_set_readonly(rom_mr, true); 243 uint8_t *rom = memory_region_get_ram_ptr(rom_mr); 244 memory_region_add_subregion(address_space, 0x60000000, rom_mr); 245 rom[0] = 0x10; /* Mips G364 */ 246 } 247 break; 248 case JAZZ_PICA61: 249 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory()); 250 break; 251 default: 252 break; 253 } 254 255 /* Network controller */ 256 for (n = 0; n < nb_nics; n++) { 257 nd = &nd_table[n]; 258 if (!nd->model) 259 nd->model = g_strdup("dp83932"); 260 if (strcmp(nd->model, "dp83932") == 0) { 261 qemu_check_nic_model(nd, "dp83932"); 262 263 dev = qdev_create(NULL, "dp8393x"); 264 qdev_set_nic_properties(dev, nd); 265 qdev_prop_set_uint8(dev, "it_shift", 2); 266 qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr); 267 qdev_init_nofail(dev); 268 sysbus = SYS_BUS_DEVICE(dev); 269 sysbus_mmio_map(sysbus, 0, 0x80001000); 270 sysbus_mmio_map(sysbus, 1, 0x8000b000); 271 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); 272 break; 273 } else if (is_help_option(nd->model)) { 274 error_report("Supported NICs: dp83932"); 275 exit(1); 276 } else { 277 error_report("Unsupported NIC: %s", nd->model); 278 exit(1); 279 } 280 } 281 282 /* SCSI adapter */ 283 esp = esp_init(0x80002000, 0, rc4030_dma_read, rc4030_dma_write, dmas[0], 284 qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable); 285 scsi_bus_legacy_handle_cmdline(&esp->bus); 286 287 /* Floppy */ 288 for (n = 0; n < MAX_FD; n++) { 289 fds[n] = drive_get(IF_FLOPPY, 0, n); 290 } 291 /* FIXME: we should enable DMA with a custom IsaDma device */ 292 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds); 293 294 /* Real time clock */ 295 mc146818_rtc_init(isa_bus, 1980, NULL); 296 memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000); 297 memory_region_add_subregion(address_space, 0x80004000, rtc); 298 299 /* Keyboard (i8042) */ 300 i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7), 301 i8042, 0x1000, 0x1); 302 memory_region_add_subregion(address_space, 0x80005000, i8042); 303 304 /* Serial ports */ 305 if (serial_hds[0]) { 306 serial_mm_init(address_space, 0x80006000, 0, 307 qdev_get_gpio_in(rc4030, 8), 8000000/16, 308 serial_hds[0], DEVICE_NATIVE_ENDIAN); 309 } 310 if (serial_hds[1]) { 311 serial_mm_init(address_space, 0x80007000, 0, 312 qdev_get_gpio_in(rc4030, 9), 8000000/16, 313 serial_hds[1], DEVICE_NATIVE_ENDIAN); 314 } 315 316 /* Parallel port */ 317 if (parallel_hds[0]) 318 parallel_mm_init(address_space, 0x80008000, 0, 319 qdev_get_gpio_in(rc4030, 0), parallel_hds[0]); 320 321 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ 322 323 /* NVRAM */ 324 dev = qdev_create(NULL, "ds1225y"); 325 qdev_init_nofail(dev); 326 sysbus = SYS_BUS_DEVICE(dev); 327 sysbus_mmio_map(sysbus, 0, 0x80009000); 328 329 /* LED indicator */ 330 sysbus_create_simple("jazz-led", 0x8000f000, NULL); 331 } 332 333 static 334 void mips_magnum_init(MachineState *machine) 335 { 336 mips_jazz_init(machine, JAZZ_MAGNUM); 337 } 338 339 static 340 void mips_pica61_init(MachineState *machine) 341 { 342 mips_jazz_init(machine, JAZZ_PICA61); 343 } 344 345 static void mips_magnum_class_init(ObjectClass *oc, void *data) 346 { 347 MachineClass *mc = MACHINE_CLASS(oc); 348 349 mc->desc = "MIPS Magnum"; 350 mc->init = mips_magnum_init; 351 mc->block_default_type = IF_SCSI; 352 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); 353 } 354 355 static const TypeInfo mips_magnum_type = { 356 .name = MACHINE_TYPE_NAME("magnum"), 357 .parent = TYPE_MACHINE, 358 .class_init = mips_magnum_class_init, 359 }; 360 361 static void mips_pica61_class_init(ObjectClass *oc, void *data) 362 { 363 MachineClass *mc = MACHINE_CLASS(oc); 364 365 mc->desc = "Acer Pica 61"; 366 mc->init = mips_pica61_init; 367 mc->block_default_type = IF_SCSI; 368 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); 369 } 370 371 static const TypeInfo mips_pica61_type = { 372 .name = MACHINE_TYPE_NAME("pica61"), 373 .parent = TYPE_MACHINE, 374 .class_init = mips_pica61_class_init, 375 }; 376 377 static void mips_jazz_machine_init(void) 378 { 379 type_register_static(&mips_magnum_type); 380 type_register_static(&mips_pica61_type); 381 } 382 383 type_init(mips_jazz_machine_init) 384