1 /* 2 * QEMU MIPS Jazz support 3 * 4 * Copyright (c) 2007-2008 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "hw/hw.h" 26 #include "hw/mips/mips.h" 27 #include "hw/mips/cpudevs.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/isa/isa.h" 31 #include "hw/block/fdc.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/arch_init.h" 34 #include "hw/boards.h" 35 #include "net/net.h" 36 #include "hw/scsi/esp.h" 37 #include "hw/mips/bios.h" 38 #include "hw/loader.h" 39 #include "hw/timer/mc146818rtc.h" 40 #include "hw/timer/i8254.h" 41 #include "hw/audio/pcspk.h" 42 #include "sysemu/block-backend.h" 43 #include "hw/sysbus.h" 44 #include "exec/address-spaces.h" 45 #include "sysemu/qtest.h" 46 #include "qemu/error-report.h" 47 48 enum jazz_model_e 49 { 50 JAZZ_MAGNUM, 51 JAZZ_PICA61, 52 }; 53 54 static void main_cpu_reset(void *opaque) 55 { 56 MIPSCPU *cpu = opaque; 57 58 cpu_reset(CPU(cpu)); 59 } 60 61 static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size) 62 { 63 return cpu_inw(0x71); 64 } 65 66 static void rtc_write(void *opaque, hwaddr addr, 67 uint64_t val, unsigned size) 68 { 69 cpu_outw(0x71, val & 0xff); 70 } 71 72 static const MemoryRegionOps rtc_ops = { 73 .read = rtc_read, 74 .write = rtc_write, 75 .endianness = DEVICE_NATIVE_ENDIAN, 76 }; 77 78 static uint64_t dma_dummy_read(void *opaque, hwaddr addr, 79 unsigned size) 80 { 81 /* Nothing to do. That is only to ensure that 82 * the current DMA acknowledge cycle is completed. */ 83 return 0xff; 84 } 85 86 static void dma_dummy_write(void *opaque, hwaddr addr, 87 uint64_t val, unsigned size) 88 { 89 /* Nothing to do. That is only to ensure that 90 * the current DMA acknowledge cycle is completed. */ 91 } 92 93 static const MemoryRegionOps dma_dummy_ops = { 94 .read = dma_dummy_read, 95 .write = dma_dummy_write, 96 .endianness = DEVICE_NATIVE_ENDIAN, 97 }; 98 99 #define MAGNUM_BIOS_SIZE_MAX 0x7e000 100 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) 101 102 static void cpu_request_exit(void *opaque, int irq, int level) 103 { 104 CPUState *cpu = current_cpu; 105 106 if (cpu && level) { 107 cpu_exit(cpu); 108 } 109 } 110 111 static CPUUnassignedAccess real_do_unassigned_access; 112 static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr, 113 bool is_write, bool is_exec, 114 int opaque, unsigned size) 115 { 116 if (!is_exec) { 117 /* ignore invalid access (ie do not raise exception) */ 118 return; 119 } 120 (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size); 121 } 122 123 static void mips_jazz_init(MemoryRegion *address_space, 124 MemoryRegion *address_space_io, 125 ram_addr_t ram_size, 126 const char *cpu_model, 127 enum jazz_model_e jazz_model) 128 { 129 char *filename; 130 int bios_size, n; 131 MIPSCPU *cpu; 132 CPUClass *cc; 133 CPUMIPSState *env; 134 qemu_irq *rc4030, *i8259; 135 rc4030_dma *dmas; 136 void* rc4030_opaque; 137 MemoryRegion *isa = g_new(MemoryRegion, 1); 138 MemoryRegion *rtc = g_new(MemoryRegion, 1); 139 MemoryRegion *i8042 = g_new(MemoryRegion, 1); 140 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1); 141 NICInfo *nd; 142 DeviceState *dev; 143 SysBusDevice *sysbus; 144 ISABus *isa_bus; 145 ISADevice *pit; 146 DriveInfo *fds[MAX_FD]; 147 qemu_irq esp_reset, dma_enable; 148 qemu_irq *cpu_exit_irq; 149 MemoryRegion *ram = g_new(MemoryRegion, 1); 150 MemoryRegion *bios = g_new(MemoryRegion, 1); 151 MemoryRegion *bios2 = g_new(MemoryRegion, 1); 152 153 /* init CPUs */ 154 if (cpu_model == NULL) { 155 #ifdef TARGET_MIPS64 156 cpu_model = "R4000"; 157 #else 158 /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */ 159 cpu_model = "24Kf"; 160 #endif 161 } 162 cpu = cpu_mips_init(cpu_model); 163 if (cpu == NULL) { 164 fprintf(stderr, "Unable to find CPU definition\n"); 165 exit(1); 166 } 167 env = &cpu->env; 168 qemu_register_reset(main_cpu_reset, cpu); 169 170 /* Chipset returns 0 in invalid reads and do not raise data exceptions. 171 * However, we can't simply add a global memory region to catch 172 * everything, as memory core directly call unassigned_mem_read/write 173 * on some invalid accesses, which call do_unassigned_access on the 174 * CPU, which raise an exception. 175 * Handle that case by hijacking the do_unassigned_access method on 176 * the CPU, and do not raise exceptions for data access. */ 177 cc = CPU_GET_CLASS(cpu); 178 real_do_unassigned_access = cc->do_unassigned_access; 179 cc->do_unassigned_access = mips_jazz_do_unassigned_access; 180 181 /* allocate RAM */ 182 memory_region_init_ram(ram, NULL, "mips_jazz.ram", ram_size, &error_abort); 183 vmstate_register_ram_global(ram); 184 memory_region_add_subregion(address_space, 0, ram); 185 186 memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, 187 &error_abort); 188 vmstate_register_ram_global(bios); 189 memory_region_set_readonly(bios, true); 190 memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios, 191 0, MAGNUM_BIOS_SIZE); 192 memory_region_add_subregion(address_space, 0x1fc00000LL, bios); 193 memory_region_add_subregion(address_space, 0xfff00000LL, bios2); 194 195 /* load the BIOS image. */ 196 if (bios_name == NULL) 197 bios_name = BIOS_FILENAME; 198 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 199 if (filename) { 200 bios_size = load_image_targphys(filename, 0xfff00000LL, 201 MAGNUM_BIOS_SIZE); 202 g_free(filename); 203 } else { 204 bios_size = -1; 205 } 206 if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) { 207 error_report("Could not load MIPS bios '%s'", bios_name); 208 exit(1); 209 } 210 211 /* Init CPU internal devices */ 212 cpu_mips_irq_init_cpu(env); 213 cpu_mips_clock_init(env); 214 215 /* Chipset */ 216 rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas, 217 address_space); 218 memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000); 219 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); 220 221 /* ISA devices */ 222 isa_bus = isa_bus_new(NULL, address_space_io); 223 i8259 = i8259_init(isa_bus, env->irq[4]); 224 isa_bus_irqs(isa_bus, i8259); 225 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 226 DMA_init(0, cpu_exit_irq); 227 pit = pit_init(isa_bus, 0x40, 0, NULL); 228 pcspk_init(isa_bus, pit); 229 230 /* ISA IO space at 0x90000000 */ 231 memory_region_init_alias(isa, NULL, "isa_mmio", 232 get_system_io(), 0, 0x01000000); 233 memory_region_add_subregion(address_space, 0x90000000, isa); 234 isa_mem_base = 0x11000000; 235 236 /* Video card */ 237 switch (jazz_model) { 238 case JAZZ_MAGNUM: 239 dev = qdev_create(NULL, "sysbus-g364"); 240 qdev_init_nofail(dev); 241 sysbus = SYS_BUS_DEVICE(dev); 242 sysbus_mmio_map(sysbus, 0, 0x60080000); 243 sysbus_mmio_map(sysbus, 1, 0x40000000); 244 sysbus_connect_irq(sysbus, 0, rc4030[3]); 245 { 246 /* Simple ROM, so user doesn't have to provide one */ 247 MemoryRegion *rom_mr = g_new(MemoryRegion, 1); 248 memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000, 249 &error_abort); 250 vmstate_register_ram_global(rom_mr); 251 memory_region_set_readonly(rom_mr, true); 252 uint8_t *rom = memory_region_get_ram_ptr(rom_mr); 253 memory_region_add_subregion(address_space, 0x60000000, rom_mr); 254 rom[0] = 0x10; /* Mips G364 */ 255 } 256 break; 257 case JAZZ_PICA61: 258 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory()); 259 break; 260 default: 261 break; 262 } 263 264 /* Network controller */ 265 for (n = 0; n < nb_nics; n++) { 266 nd = &nd_table[n]; 267 if (!nd->model) 268 nd->model = g_strdup("dp83932"); 269 if (strcmp(nd->model, "dp83932") == 0) { 270 dp83932_init(nd, 0x80001000, 2, get_system_memory(), rc4030[4], 271 rc4030_opaque, rc4030_dma_memory_rw); 272 break; 273 } else if (is_help_option(nd->model)) { 274 fprintf(stderr, "qemu: Supported NICs: dp83932\n"); 275 exit(1); 276 } else { 277 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); 278 exit(1); 279 } 280 } 281 282 /* SCSI adapter */ 283 esp_init(0x80002000, 0, 284 rc4030_dma_read, rc4030_dma_write, dmas[0], 285 rc4030[5], &esp_reset, &dma_enable); 286 287 /* Floppy */ 288 if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) { 289 fprintf(stderr, "qemu: too many floppy drives\n"); 290 exit(1); 291 } 292 for (n = 0; n < MAX_FD; n++) { 293 fds[n] = drive_get(IF_FLOPPY, 0, n); 294 } 295 fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds); 296 297 /* Real time clock */ 298 rtc_init(isa_bus, 1980, NULL); 299 memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000); 300 memory_region_add_subregion(address_space, 0x80004000, rtc); 301 302 /* Keyboard (i8042) */ 303 i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1); 304 memory_region_add_subregion(address_space, 0x80005000, i8042); 305 306 /* Serial ports */ 307 if (serial_hds[0]) { 308 serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16, 309 serial_hds[0], DEVICE_NATIVE_ENDIAN); 310 } 311 if (serial_hds[1]) { 312 serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16, 313 serial_hds[1], DEVICE_NATIVE_ENDIAN); 314 } 315 316 /* Parallel port */ 317 if (parallel_hds[0]) 318 parallel_mm_init(address_space, 0x80008000, 0, rc4030[0], 319 parallel_hds[0]); 320 321 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ 322 323 /* NVRAM */ 324 dev = qdev_create(NULL, "ds1225y"); 325 qdev_init_nofail(dev); 326 sysbus = SYS_BUS_DEVICE(dev); 327 sysbus_mmio_map(sysbus, 0, 0x80009000); 328 329 /* LED indicator */ 330 sysbus_create_simple("jazz-led", 0x8000f000, NULL); 331 } 332 333 static 334 void mips_magnum_init(MachineState *machine) 335 { 336 ram_addr_t ram_size = machine->ram_size; 337 const char *cpu_model = machine->cpu_model; 338 mips_jazz_init(get_system_memory(), get_system_io(), 339 ram_size, cpu_model, JAZZ_MAGNUM); 340 } 341 342 static 343 void mips_pica61_init(MachineState *machine) 344 { 345 ram_addr_t ram_size = machine->ram_size; 346 const char *cpu_model = machine->cpu_model; 347 mips_jazz_init(get_system_memory(), get_system_io(), 348 ram_size, cpu_model, JAZZ_PICA61); 349 } 350 351 static QEMUMachine mips_magnum_machine = { 352 .name = "magnum", 353 .desc = "MIPS Magnum", 354 .init = mips_magnum_init, 355 .block_default_type = IF_SCSI, 356 }; 357 358 static QEMUMachine mips_pica61_machine = { 359 .name = "pica61", 360 .desc = "Acer Pica 61", 361 .init = mips_pica61_init, 362 .block_default_type = IF_SCSI, 363 }; 364 365 static void mips_jazz_machine_init(void) 366 { 367 qemu_register_machine(&mips_magnum_machine); 368 qemu_register_machine(&mips_pica61_machine); 369 } 370 371 machine_init(mips_jazz_machine_init); 372