1 /* 2 * QEMU MIPS Jazz support 3 * 4 * Copyright (c) 2007-2008 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "hw/hw.h" 26 #include "hw/mips/mips.h" 27 #include "hw/mips/cpudevs.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/isa/isa.h" 31 #include "hw/block/fdc.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/arch_init.h" 34 #include "hw/boards.h" 35 #include "net/net.h" 36 #include "hw/scsi/esp.h" 37 #include "hw/mips/bios.h" 38 #include "hw/loader.h" 39 #include "hw/timer/mc146818rtc.h" 40 #include "hw/timer/i8254.h" 41 #include "hw/audio/pcspk.h" 42 #include "sysemu/block-backend.h" 43 #include "hw/sysbus.h" 44 #include "exec/address-spaces.h" 45 #include "sysemu/qtest.h" 46 #include "qemu/error-report.h" 47 48 enum jazz_model_e 49 { 50 JAZZ_MAGNUM, 51 JAZZ_PICA61, 52 }; 53 54 static void main_cpu_reset(void *opaque) 55 { 56 MIPSCPU *cpu = opaque; 57 58 cpu_reset(CPU(cpu)); 59 } 60 61 static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size) 62 { 63 uint8_t val; 64 address_space_read(&address_space_memory, 0x90000071, 65 MEMTXATTRS_UNSPECIFIED, &val, 1); 66 return val; 67 } 68 69 static void rtc_write(void *opaque, hwaddr addr, 70 uint64_t val, unsigned size) 71 { 72 uint8_t buf = val & 0xff; 73 address_space_write(&address_space_memory, 0x90000071, 74 MEMTXATTRS_UNSPECIFIED, &buf, 1); 75 } 76 77 static const MemoryRegionOps rtc_ops = { 78 .read = rtc_read, 79 .write = rtc_write, 80 .endianness = DEVICE_NATIVE_ENDIAN, 81 }; 82 83 static uint64_t dma_dummy_read(void *opaque, hwaddr addr, 84 unsigned size) 85 { 86 /* Nothing to do. That is only to ensure that 87 * the current DMA acknowledge cycle is completed. */ 88 return 0xff; 89 } 90 91 static void dma_dummy_write(void *opaque, hwaddr addr, 92 uint64_t val, unsigned size) 93 { 94 /* Nothing to do. That is only to ensure that 95 * the current DMA acknowledge cycle is completed. */ 96 } 97 98 static const MemoryRegionOps dma_dummy_ops = { 99 .read = dma_dummy_read, 100 .write = dma_dummy_write, 101 .endianness = DEVICE_NATIVE_ENDIAN, 102 }; 103 104 #define MAGNUM_BIOS_SIZE_MAX 0x7e000 105 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) 106 107 static void cpu_request_exit(void *opaque, int irq, int level) 108 { 109 CPUState *cpu = current_cpu; 110 111 if (cpu && level) { 112 cpu_exit(cpu); 113 } 114 } 115 116 static CPUUnassignedAccess real_do_unassigned_access; 117 static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr, 118 bool is_write, bool is_exec, 119 int opaque, unsigned size) 120 { 121 if (!is_exec) { 122 /* ignore invalid access (ie do not raise exception) */ 123 return; 124 } 125 (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size); 126 } 127 128 static void mips_jazz_init(MachineState *machine, 129 enum jazz_model_e jazz_model) 130 { 131 MemoryRegion *address_space = get_system_memory(); 132 const char *cpu_model = machine->cpu_model; 133 char *filename; 134 int bios_size, n; 135 MIPSCPU *cpu; 136 CPUClass *cc; 137 CPUMIPSState *env; 138 qemu_irq *i8259; 139 rc4030_dma *dmas; 140 MemoryRegion *rc4030_dma_mr; 141 MemoryRegion *isa_mem = g_new(MemoryRegion, 1); 142 MemoryRegion *isa_io = g_new(MemoryRegion, 1); 143 MemoryRegion *rtc = g_new(MemoryRegion, 1); 144 MemoryRegion *i8042 = g_new(MemoryRegion, 1); 145 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1); 146 NICInfo *nd; 147 DeviceState *dev, *rc4030; 148 SysBusDevice *sysbus; 149 ISABus *isa_bus; 150 ISADevice *pit; 151 DriveInfo *fds[MAX_FD]; 152 qemu_irq esp_reset, dma_enable; 153 qemu_irq *cpu_exit_irq; 154 MemoryRegion *ram = g_new(MemoryRegion, 1); 155 MemoryRegion *bios = g_new(MemoryRegion, 1); 156 MemoryRegion *bios2 = g_new(MemoryRegion, 1); 157 158 /* init CPUs */ 159 if (cpu_model == NULL) { 160 cpu_model = "R4000"; 161 } 162 cpu = cpu_mips_init(cpu_model); 163 if (cpu == NULL) { 164 fprintf(stderr, "Unable to find CPU definition\n"); 165 exit(1); 166 } 167 env = &cpu->env; 168 qemu_register_reset(main_cpu_reset, cpu); 169 170 /* Chipset returns 0 in invalid reads and do not raise data exceptions. 171 * However, we can't simply add a global memory region to catch 172 * everything, as memory core directly call unassigned_mem_read/write 173 * on some invalid accesses, which call do_unassigned_access on the 174 * CPU, which raise an exception. 175 * Handle that case by hijacking the do_unassigned_access method on 176 * the CPU, and do not raise exceptions for data access. */ 177 cc = CPU_GET_CLASS(cpu); 178 real_do_unassigned_access = cc->do_unassigned_access; 179 cc->do_unassigned_access = mips_jazz_do_unassigned_access; 180 181 /* allocate RAM */ 182 memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram", 183 machine->ram_size); 184 memory_region_add_subregion(address_space, 0, ram); 185 186 memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, 187 &error_abort); 188 vmstate_register_ram_global(bios); 189 memory_region_set_readonly(bios, true); 190 memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios, 191 0, MAGNUM_BIOS_SIZE); 192 memory_region_add_subregion(address_space, 0x1fc00000LL, bios); 193 memory_region_add_subregion(address_space, 0xfff00000LL, bios2); 194 195 /* load the BIOS image. */ 196 if (bios_name == NULL) 197 bios_name = BIOS_FILENAME; 198 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 199 if (filename) { 200 bios_size = load_image_targphys(filename, 0xfff00000LL, 201 MAGNUM_BIOS_SIZE); 202 g_free(filename); 203 } else { 204 bios_size = -1; 205 } 206 if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) { 207 error_report("Could not load MIPS bios '%s'", bios_name); 208 exit(1); 209 } 210 211 /* Init CPU internal devices */ 212 cpu_mips_irq_init_cpu(env); 213 cpu_mips_clock_init(env); 214 215 /* Chipset */ 216 rc4030 = rc4030_init(&dmas, &rc4030_dma_mr); 217 sysbus = SYS_BUS_DEVICE(rc4030); 218 sysbus_connect_irq(sysbus, 0, env->irq[6]); 219 sysbus_connect_irq(sysbus, 1, env->irq[3]); 220 memory_region_add_subregion(address_space, 0x80000000, 221 sysbus_mmio_get_region(sysbus, 0)); 222 memory_region_add_subregion(address_space, 0xf0000000, 223 sysbus_mmio_get_region(sysbus, 1)); 224 memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000); 225 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); 226 227 /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */ 228 memory_region_init(isa_io, NULL, "isa-io", 0x00010000); 229 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000); 230 memory_region_add_subregion(address_space, 0x90000000, isa_io); 231 memory_region_add_subregion(address_space, 0x91000000, isa_mem); 232 isa_bus = isa_bus_new(NULL, isa_mem, isa_io); 233 234 /* ISA devices */ 235 i8259 = i8259_init(isa_bus, env->irq[4]); 236 isa_bus_irqs(isa_bus, i8259); 237 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 238 DMA_init(0, cpu_exit_irq); 239 pit = pit_init(isa_bus, 0x40, 0, NULL); 240 pcspk_init(isa_bus, pit); 241 242 /* Video card */ 243 switch (jazz_model) { 244 case JAZZ_MAGNUM: 245 dev = qdev_create(NULL, "sysbus-g364"); 246 qdev_init_nofail(dev); 247 sysbus = SYS_BUS_DEVICE(dev); 248 sysbus_mmio_map(sysbus, 0, 0x60080000); 249 sysbus_mmio_map(sysbus, 1, 0x40000000); 250 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3)); 251 { 252 /* Simple ROM, so user doesn't have to provide one */ 253 MemoryRegion *rom_mr = g_new(MemoryRegion, 1); 254 memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000, 255 &error_abort); 256 vmstate_register_ram_global(rom_mr); 257 memory_region_set_readonly(rom_mr, true); 258 uint8_t *rom = memory_region_get_ram_ptr(rom_mr); 259 memory_region_add_subregion(address_space, 0x60000000, rom_mr); 260 rom[0] = 0x10; /* Mips G364 */ 261 } 262 break; 263 case JAZZ_PICA61: 264 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory()); 265 break; 266 default: 267 break; 268 } 269 270 /* Network controller */ 271 for (n = 0; n < nb_nics; n++) { 272 nd = &nd_table[n]; 273 if (!nd->model) 274 nd->model = g_strdup("dp83932"); 275 if (strcmp(nd->model, "dp83932") == 0) { 276 qemu_check_nic_model(nd, "dp83932"); 277 278 dev = qdev_create(NULL, "dp8393x"); 279 qdev_set_nic_properties(dev, nd); 280 qdev_prop_set_uint8(dev, "it_shift", 2); 281 qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr); 282 qdev_init_nofail(dev); 283 sysbus = SYS_BUS_DEVICE(dev); 284 sysbus_mmio_map(sysbus, 0, 0x80001000); 285 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); 286 break; 287 } else if (is_help_option(nd->model)) { 288 fprintf(stderr, "qemu: Supported NICs: dp83932\n"); 289 exit(1); 290 } else { 291 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); 292 exit(1); 293 } 294 } 295 296 /* SCSI adapter */ 297 esp_init(0x80002000, 0, 298 rc4030_dma_read, rc4030_dma_write, dmas[0], 299 qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable); 300 301 /* Floppy */ 302 if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) { 303 fprintf(stderr, "qemu: too many floppy drives\n"); 304 exit(1); 305 } 306 for (n = 0; n < MAX_FD; n++) { 307 fds[n] = drive_get(IF_FLOPPY, 0, n); 308 } 309 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), 0, 0x80003000, fds); 310 311 /* Real time clock */ 312 rtc_init(isa_bus, 1980, NULL); 313 memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000); 314 memory_region_add_subregion(address_space, 0x80004000, rtc); 315 316 /* Keyboard (i8042) */ 317 i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7), 318 i8042, 0x1000, 0x1); 319 memory_region_add_subregion(address_space, 0x80005000, i8042); 320 321 /* Serial ports */ 322 if (serial_hds[0]) { 323 serial_mm_init(address_space, 0x80006000, 0, 324 qdev_get_gpio_in(rc4030, 8), 8000000/16, 325 serial_hds[0], DEVICE_NATIVE_ENDIAN); 326 } 327 if (serial_hds[1]) { 328 serial_mm_init(address_space, 0x80007000, 0, 329 qdev_get_gpio_in(rc4030, 9), 8000000/16, 330 serial_hds[1], DEVICE_NATIVE_ENDIAN); 331 } 332 333 /* Parallel port */ 334 if (parallel_hds[0]) 335 parallel_mm_init(address_space, 0x80008000, 0, 336 qdev_get_gpio_in(rc4030, 0), parallel_hds[0]); 337 338 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ 339 340 /* NVRAM */ 341 dev = qdev_create(NULL, "ds1225y"); 342 qdev_init_nofail(dev); 343 sysbus = SYS_BUS_DEVICE(dev); 344 sysbus_mmio_map(sysbus, 0, 0x80009000); 345 346 /* LED indicator */ 347 sysbus_create_simple("jazz-led", 0x8000f000, NULL); 348 } 349 350 static 351 void mips_magnum_init(MachineState *machine) 352 { 353 mips_jazz_init(machine, JAZZ_MAGNUM); 354 } 355 356 static 357 void mips_pica61_init(MachineState *machine) 358 { 359 mips_jazz_init(machine, JAZZ_PICA61); 360 } 361 362 static QEMUMachine mips_magnum_machine = { 363 .name = "magnum", 364 .desc = "MIPS Magnum", 365 .init = mips_magnum_init, 366 .block_default_type = IF_SCSI, 367 }; 368 369 static QEMUMachine mips_pica61_machine = { 370 .name = "pica61", 371 .desc = "Acer Pica 61", 372 .init = mips_pica61_init, 373 .block_default_type = IF_SCSI, 374 }; 375 376 static void mips_jazz_machine_init(void) 377 { 378 qemu_register_machine(&mips_magnum_machine); 379 qemu_register_machine(&mips_pica61_machine); 380 } 381 382 machine_init(mips_jazz_machine_init); 383