1 /* 2 * QEMU MIPS Jazz support 3 * 4 * Copyright (c) 2007-2008 Hervé Poussineau 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/mips/mips.h" 28 #include "hw/mips/cpudevs.h" 29 #include "hw/i386/pc.h" 30 #include "hw/char/serial.h" 31 #include "hw/isa/isa.h" 32 #include "hw/block/fdc.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/arch_init.h" 35 #include "hw/boards.h" 36 #include "net/net.h" 37 #include "hw/scsi/esp.h" 38 #include "hw/mips/bios.h" 39 #include "hw/loader.h" 40 #include "hw/timer/mc146818rtc.h" 41 #include "hw/timer/i8254.h" 42 #include "hw/audio/pcspk.h" 43 #include "sysemu/block-backend.h" 44 #include "hw/sysbus.h" 45 #include "exec/address-spaces.h" 46 #include "sysemu/qtest.h" 47 #include "qemu/error-report.h" 48 49 enum jazz_model_e 50 { 51 JAZZ_MAGNUM, 52 JAZZ_PICA61, 53 }; 54 55 static void main_cpu_reset(void *opaque) 56 { 57 MIPSCPU *cpu = opaque; 58 59 cpu_reset(CPU(cpu)); 60 } 61 62 static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size) 63 { 64 uint8_t val; 65 address_space_read(&address_space_memory, 0x90000071, 66 MEMTXATTRS_UNSPECIFIED, &val, 1); 67 return val; 68 } 69 70 static void rtc_write(void *opaque, hwaddr addr, 71 uint64_t val, unsigned size) 72 { 73 uint8_t buf = val & 0xff; 74 address_space_write(&address_space_memory, 0x90000071, 75 MEMTXATTRS_UNSPECIFIED, &buf, 1); 76 } 77 78 static const MemoryRegionOps rtc_ops = { 79 .read = rtc_read, 80 .write = rtc_write, 81 .endianness = DEVICE_NATIVE_ENDIAN, 82 }; 83 84 static uint64_t dma_dummy_read(void *opaque, hwaddr addr, 85 unsigned size) 86 { 87 /* Nothing to do. That is only to ensure that 88 * the current DMA acknowledge cycle is completed. */ 89 return 0xff; 90 } 91 92 static void dma_dummy_write(void *opaque, hwaddr addr, 93 uint64_t val, unsigned size) 94 { 95 /* Nothing to do. That is only to ensure that 96 * the current DMA acknowledge cycle is completed. */ 97 } 98 99 static const MemoryRegionOps dma_dummy_ops = { 100 .read = dma_dummy_read, 101 .write = dma_dummy_write, 102 .endianness = DEVICE_NATIVE_ENDIAN, 103 }; 104 105 #define MAGNUM_BIOS_SIZE_MAX 0x7e000 106 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) 107 108 static CPUUnassignedAccess real_do_unassigned_access; 109 static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr, 110 bool is_write, bool is_exec, 111 int opaque, unsigned size) 112 { 113 if (!is_exec) { 114 /* ignore invalid access (ie do not raise exception) */ 115 return; 116 } 117 (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size); 118 } 119 120 static void mips_jazz_init(MachineState *machine, 121 enum jazz_model_e jazz_model) 122 { 123 MemoryRegion *address_space = get_system_memory(); 124 const char *cpu_model = machine->cpu_model; 125 char *filename; 126 int bios_size, n; 127 MIPSCPU *cpu; 128 CPUClass *cc; 129 CPUMIPSState *env; 130 qemu_irq *i8259; 131 rc4030_dma *dmas; 132 MemoryRegion *rc4030_dma_mr; 133 MemoryRegion *isa_mem = g_new(MemoryRegion, 1); 134 MemoryRegion *isa_io = g_new(MemoryRegion, 1); 135 MemoryRegion *rtc = g_new(MemoryRegion, 1); 136 MemoryRegion *i8042 = g_new(MemoryRegion, 1); 137 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1); 138 NICInfo *nd; 139 DeviceState *dev, *rc4030; 140 SysBusDevice *sysbus; 141 ISABus *isa_bus; 142 ISADevice *pit; 143 DriveInfo *fds[MAX_FD]; 144 qemu_irq esp_reset, dma_enable; 145 MemoryRegion *ram = g_new(MemoryRegion, 1); 146 MemoryRegion *bios = g_new(MemoryRegion, 1); 147 MemoryRegion *bios2 = g_new(MemoryRegion, 1); 148 149 /* init CPUs */ 150 if (cpu_model == NULL) { 151 cpu_model = "R4000"; 152 } 153 cpu = cpu_mips_init(cpu_model); 154 if (cpu == NULL) { 155 fprintf(stderr, "Unable to find CPU definition\n"); 156 exit(1); 157 } 158 env = &cpu->env; 159 qemu_register_reset(main_cpu_reset, cpu); 160 161 /* Chipset returns 0 in invalid reads and do not raise data exceptions. 162 * However, we can't simply add a global memory region to catch 163 * everything, as memory core directly call unassigned_mem_read/write 164 * on some invalid accesses, which call do_unassigned_access on the 165 * CPU, which raise an exception. 166 * Handle that case by hijacking the do_unassigned_access method on 167 * the CPU, and do not raise exceptions for data access. */ 168 cc = CPU_GET_CLASS(cpu); 169 real_do_unassigned_access = cc->do_unassigned_access; 170 cc->do_unassigned_access = mips_jazz_do_unassigned_access; 171 172 /* allocate RAM */ 173 memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram", 174 machine->ram_size); 175 memory_region_add_subregion(address_space, 0, ram); 176 177 memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, 178 &error_fatal); 179 vmstate_register_ram_global(bios); 180 memory_region_set_readonly(bios, true); 181 memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios, 182 0, MAGNUM_BIOS_SIZE); 183 memory_region_add_subregion(address_space, 0x1fc00000LL, bios); 184 memory_region_add_subregion(address_space, 0xfff00000LL, bios2); 185 186 /* load the BIOS image. */ 187 if (bios_name == NULL) 188 bios_name = BIOS_FILENAME; 189 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 190 if (filename) { 191 bios_size = load_image_targphys(filename, 0xfff00000LL, 192 MAGNUM_BIOS_SIZE); 193 g_free(filename); 194 } else { 195 bios_size = -1; 196 } 197 if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) { 198 error_report("Could not load MIPS bios '%s'", bios_name); 199 exit(1); 200 } 201 202 /* Init CPU internal devices */ 203 cpu_mips_irq_init_cpu(env); 204 cpu_mips_clock_init(env); 205 206 /* Chipset */ 207 rc4030 = rc4030_init(&dmas, &rc4030_dma_mr); 208 sysbus = SYS_BUS_DEVICE(rc4030); 209 sysbus_connect_irq(sysbus, 0, env->irq[6]); 210 sysbus_connect_irq(sysbus, 1, env->irq[3]); 211 memory_region_add_subregion(address_space, 0x80000000, 212 sysbus_mmio_get_region(sysbus, 0)); 213 memory_region_add_subregion(address_space, 0xf0000000, 214 sysbus_mmio_get_region(sysbus, 1)); 215 memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000); 216 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); 217 218 /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */ 219 memory_region_init(isa_io, NULL, "isa-io", 0x00010000); 220 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000); 221 memory_region_add_subregion(address_space, 0x90000000, isa_io); 222 memory_region_add_subregion(address_space, 0x91000000, isa_mem); 223 isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort); 224 225 /* ISA devices */ 226 i8259 = i8259_init(isa_bus, env->irq[4]); 227 isa_bus_irqs(isa_bus, i8259); 228 DMA_init(isa_bus, 0); 229 pit = pit_init(isa_bus, 0x40, 0, NULL); 230 pcspk_init(isa_bus, pit); 231 232 /* Video card */ 233 switch (jazz_model) { 234 case JAZZ_MAGNUM: 235 dev = qdev_create(NULL, "sysbus-g364"); 236 qdev_init_nofail(dev); 237 sysbus = SYS_BUS_DEVICE(dev); 238 sysbus_mmio_map(sysbus, 0, 0x60080000); 239 sysbus_mmio_map(sysbus, 1, 0x40000000); 240 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3)); 241 { 242 /* Simple ROM, so user doesn't have to provide one */ 243 MemoryRegion *rom_mr = g_new(MemoryRegion, 1); 244 memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000, 245 &error_fatal); 246 vmstate_register_ram_global(rom_mr); 247 memory_region_set_readonly(rom_mr, true); 248 uint8_t *rom = memory_region_get_ram_ptr(rom_mr); 249 memory_region_add_subregion(address_space, 0x60000000, rom_mr); 250 rom[0] = 0x10; /* Mips G364 */ 251 } 252 break; 253 case JAZZ_PICA61: 254 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory()); 255 break; 256 default: 257 break; 258 } 259 260 /* Network controller */ 261 for (n = 0; n < nb_nics; n++) { 262 nd = &nd_table[n]; 263 if (!nd->model) 264 nd->model = g_strdup("dp83932"); 265 if (strcmp(nd->model, "dp83932") == 0) { 266 qemu_check_nic_model(nd, "dp83932"); 267 268 dev = qdev_create(NULL, "dp8393x"); 269 qdev_set_nic_properties(dev, nd); 270 qdev_prop_set_uint8(dev, "it_shift", 2); 271 qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr); 272 qdev_init_nofail(dev); 273 sysbus = SYS_BUS_DEVICE(dev); 274 sysbus_mmio_map(sysbus, 0, 0x80001000); 275 sysbus_mmio_map(sysbus, 1, 0x8000b000); 276 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); 277 break; 278 } else if (is_help_option(nd->model)) { 279 fprintf(stderr, "qemu: Supported NICs: dp83932\n"); 280 exit(1); 281 } else { 282 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); 283 exit(1); 284 } 285 } 286 287 /* SCSI adapter */ 288 esp_init(0x80002000, 0, 289 rc4030_dma_read, rc4030_dma_write, dmas[0], 290 qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable); 291 292 /* Floppy */ 293 if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) { 294 fprintf(stderr, "qemu: too many floppy drives\n"); 295 exit(1); 296 } 297 for (n = 0; n < MAX_FD; n++) { 298 fds[n] = drive_get(IF_FLOPPY, 0, n); 299 } 300 /* FIXME: we should enable DMA with a custom IsaDma device */ 301 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds); 302 303 /* Real time clock */ 304 rtc_init(isa_bus, 1980, NULL); 305 memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000); 306 memory_region_add_subregion(address_space, 0x80004000, rtc); 307 308 /* Keyboard (i8042) */ 309 i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7), 310 i8042, 0x1000, 0x1); 311 memory_region_add_subregion(address_space, 0x80005000, i8042); 312 313 /* Serial ports */ 314 if (serial_hds[0]) { 315 serial_mm_init(address_space, 0x80006000, 0, 316 qdev_get_gpio_in(rc4030, 8), 8000000/16, 317 serial_hds[0], DEVICE_NATIVE_ENDIAN); 318 } 319 if (serial_hds[1]) { 320 serial_mm_init(address_space, 0x80007000, 0, 321 qdev_get_gpio_in(rc4030, 9), 8000000/16, 322 serial_hds[1], DEVICE_NATIVE_ENDIAN); 323 } 324 325 /* Parallel port */ 326 if (parallel_hds[0]) 327 parallel_mm_init(address_space, 0x80008000, 0, 328 qdev_get_gpio_in(rc4030, 0), parallel_hds[0]); 329 330 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ 331 332 /* NVRAM */ 333 dev = qdev_create(NULL, "ds1225y"); 334 qdev_init_nofail(dev); 335 sysbus = SYS_BUS_DEVICE(dev); 336 sysbus_mmio_map(sysbus, 0, 0x80009000); 337 338 /* LED indicator */ 339 sysbus_create_simple("jazz-led", 0x8000f000, NULL); 340 } 341 342 static 343 void mips_magnum_init(MachineState *machine) 344 { 345 mips_jazz_init(machine, JAZZ_MAGNUM); 346 } 347 348 static 349 void mips_pica61_init(MachineState *machine) 350 { 351 mips_jazz_init(machine, JAZZ_PICA61); 352 } 353 354 static void mips_magnum_class_init(ObjectClass *oc, void *data) 355 { 356 MachineClass *mc = MACHINE_CLASS(oc); 357 358 mc->desc = "MIPS Magnum"; 359 mc->init = mips_magnum_init; 360 mc->block_default_type = IF_SCSI; 361 } 362 363 static const TypeInfo mips_magnum_type = { 364 .name = MACHINE_TYPE_NAME("magnum"), 365 .parent = TYPE_MACHINE, 366 .class_init = mips_magnum_class_init, 367 }; 368 369 static void mips_pica61_class_init(ObjectClass *oc, void *data) 370 { 371 MachineClass *mc = MACHINE_CLASS(oc); 372 373 mc->desc = "Acer Pica 61"; 374 mc->init = mips_pica61_init; 375 mc->block_default_type = IF_SCSI; 376 } 377 378 static const TypeInfo mips_pica61_type = { 379 .name = MACHINE_TYPE_NAME("pica61"), 380 .parent = TYPE_MACHINE, 381 .class_init = mips_pica61_class_init, 382 }; 383 384 static void mips_jazz_machine_init(void) 385 { 386 type_register_static(&mips_magnum_type); 387 type_register_static(&mips_pica61_type); 388 } 389 390 type_init(mips_jazz_machine_init) 391