1 /* 2 * QEMU fulong 2e mini pc support 3 * 4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) 6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 7 * This code is licensed under the GNU GPL v2. 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 */ 12 13 /* 14 * Fulong 2e mini pc is based on ICT/ST Loongson 2e CPU (MIPS III like, 800MHz) 15 * http://www.linux-mips.org/wiki/Fulong 16 * 17 * Loongson 2e user manual: 18 * http://www.loongsondeveloper.com/doc/Loongson2EUserGuide.pdf 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "hw/hw.h" 26 #include "hw/i386/pc.h" 27 #include "hw/dma/i8257.h" 28 #include "hw/isa/superio.h" 29 #include "net/net.h" 30 #include "hw/boards.h" 31 #include "hw/i2c/smbus.h" 32 #include "hw/block/flash.h" 33 #include "hw/mips/mips.h" 34 #include "hw/mips/cpudevs.h" 35 #include "hw/pci/pci.h" 36 #include "audio/audio.h" 37 #include "qemu/log.h" 38 #include "hw/loader.h" 39 #include "hw/ide.h" 40 #include "elf.h" 41 #include "hw/isa/vt82c686.h" 42 #include "hw/timer/mc146818rtc.h" 43 #include "hw/timer/i8254.h" 44 #include "exec/address-spaces.h" 45 #include "sysemu/qtest.h" 46 #include "qemu/error-report.h" 47 48 #define DEBUG_FULONG2E_INIT 49 50 #define ENVP_ADDR 0x80002000l 51 #define ENVP_NB_ENTRIES 16 52 #define ENVP_ENTRY_SIZE 256 53 54 /* fulong 2e has a 512k flash: Winbond W39L040AP70Z */ 55 #define BIOS_SIZE (512 * KiB) 56 #define MAX_IDE_BUS 2 57 58 /* 59 * PMON is not part of qemu and released with BSD license, anyone 60 * who want to build a pmon binary please first git-clone the source 61 * from the git repository at: 62 * http://www.loongson.cn/support/git/pmon 63 * Then follow the "Compile Guide" available at: 64 * http://dev.lemote.com/code/pmon 65 * 66 * Notes: 67 * 1, don't use the source at http://dev.lemote.com/http_git/pmon.git 68 * 2, use "Bonito2edev" to replace "dir_corresponding_to_your_target_hardware" 69 * in the "Compile Guide". 70 */ 71 #define FULONG_BIOSNAME "pmon_fulong2e.bin" 72 73 /* PCI SLOT in fulong 2e */ 74 #define FULONG2E_VIA_SLOT 5 75 #define FULONG2E_ATI_SLOT 6 76 #define FULONG2E_RTL8139_SLOT 7 77 78 static struct _loaderparams { 79 int ram_size; 80 const char *kernel_filename; 81 const char *kernel_cmdline; 82 const char *initrd_filename; 83 } loaderparams; 84 85 static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index, 86 const char *string, ...) 87 { 88 va_list ap; 89 int32_t table_addr; 90 91 if (index >= ENVP_NB_ENTRIES) 92 return; 93 94 if (string == NULL) { 95 prom_buf[index] = 0; 96 return; 97 } 98 99 table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE; 100 prom_buf[index] = tswap32(ENVP_ADDR + table_addr); 101 102 va_start(ap, string); 103 vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap); 104 va_end(ap); 105 } 106 107 static int64_t load_kernel (CPUMIPSState *env) 108 { 109 int64_t kernel_entry, kernel_low, kernel_high, initrd_size; 110 int index = 0; 111 long kernel_size; 112 ram_addr_t initrd_offset; 113 uint32_t *prom_buf; 114 long prom_size; 115 116 kernel_size = load_elf(loaderparams.kernel_filename, NULL, 117 cpu_mips_kseg0_to_phys, NULL, 118 (uint64_t *)&kernel_entry, 119 (uint64_t *)&kernel_low, (uint64_t *)&kernel_high, 120 0, EM_MIPS, 1, 0); 121 if (kernel_size < 0) { 122 error_report("could not load kernel '%s': %s", 123 loaderparams.kernel_filename, 124 load_elf_strerror(kernel_size)); 125 exit(1); 126 } 127 128 /* load initrd */ 129 initrd_size = 0; 130 initrd_offset = 0; 131 if (loaderparams.initrd_filename) { 132 initrd_size = get_image_size (loaderparams.initrd_filename); 133 if (initrd_size > 0) { 134 initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK; 135 if (initrd_offset + initrd_size > ram_size) { 136 error_report("memory too small for initial ram disk '%s'", 137 loaderparams.initrd_filename); 138 exit(1); 139 } 140 initrd_size = load_image_targphys(loaderparams.initrd_filename, 141 initrd_offset, ram_size - initrd_offset); 142 } 143 if (initrd_size == (target_ulong) -1) { 144 error_report("could not load initial ram disk '%s'", 145 loaderparams.initrd_filename); 146 exit(1); 147 } 148 } 149 150 /* Setup prom parameters. */ 151 prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE); 152 prom_buf = g_malloc(prom_size); 153 154 prom_set(prom_buf, index++, "%s", loaderparams.kernel_filename); 155 if (initrd_size > 0) { 156 prom_set(prom_buf, index++, "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s", 157 cpu_mips_phys_to_kseg0(NULL, initrd_offset), initrd_size, 158 loaderparams.kernel_cmdline); 159 } else { 160 prom_set(prom_buf, index++, "%s", loaderparams.kernel_cmdline); 161 } 162 163 /* Setup minimum environment variables */ 164 prom_set(prom_buf, index++, "busclock=33000000"); 165 prom_set(prom_buf, index++, "cpuclock=100000000"); 166 prom_set(prom_buf, index++, "memsize=%"PRIi64, loaderparams.ram_size / MiB); 167 prom_set(prom_buf, index++, "modetty0=38400n8r"); 168 prom_set(prom_buf, index++, NULL); 169 170 rom_add_blob_fixed("prom", prom_buf, prom_size, 171 cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR)); 172 173 g_free(prom_buf); 174 return kernel_entry; 175 } 176 177 static void write_bootloader (CPUMIPSState *env, uint8_t *base, int64_t kernel_addr) 178 { 179 uint32_t *p; 180 181 /* Small bootloader */ 182 p = (uint32_t *) base; 183 184 stl_p(p++, 0x0bf00010); /* j 0x1fc00040 */ 185 stl_p(p++, 0x00000000); /* nop */ 186 187 /* Second part of the bootloader */ 188 p = (uint32_t *) (base + 0x040); 189 190 stl_p(p++, 0x3c040000); /* lui a0, 0 */ 191 stl_p(p++, 0x34840002); /* ori a0, a0, 2 */ 192 stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */ 193 stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a0, low(ENVP_ADDR) */ 194 stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */ 195 stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */ 196 stl_p(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* lui a3, high(env->ram_size) */ 197 stl_p(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(env->ram_size) */ 198 stl_p(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff)); /* lui ra, high(kernel_addr) */; 199 stl_p(p++, 0x37ff0000 | (kernel_addr & 0xffff)); /* ori ra, ra, low(kernel_addr) */ 200 stl_p(p++, 0x03e00008); /* jr ra */ 201 stl_p(p++, 0x00000000); /* nop */ 202 } 203 204 205 static void main_cpu_reset(void *opaque) 206 { 207 MIPSCPU *cpu = opaque; 208 CPUMIPSState *env = &cpu->env; 209 210 cpu_reset(CPU(cpu)); 211 /* TODO: 2E reset stuff */ 212 if (loaderparams.kernel_filename) { 213 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL)); 214 } 215 } 216 217 static const uint8_t eeprom_spd[0x80] = { 218 0x80,0x08,0x07,0x0d,0x09,0x02,0x40,0x00,0x04,0x70, 219 0x70,0x00,0x82,0x10,0x00,0x01,0x0e,0x04,0x0c,0x01, 220 0x02,0x20,0x80,0x75,0x70,0x00,0x00,0x50,0x3c,0x50, 221 0x2d,0x20,0xb0,0xb0,0x50,0x50,0x00,0x00,0x00,0x00, 222 0x00,0x41,0x48,0x3c,0x32,0x75,0x00,0x00,0x00,0x00, 223 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 224 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 225 0x00,0x00,0x00,0x9c,0x7b,0x07,0x00,0x00,0x00,0x00, 226 0x00,0x00,0x00,0x00,0x48,0x42,0x35,0x34,0x41,0x32, 227 0x35,0x36,0x38,0x4b,0x4e,0x2d,0x41,0x37,0x35,0x42, 228 0x20,0x30,0x20 229 }; 230 231 static void vt82c686b_southbridge_init(PCIBus *pci_bus, int slot, qemu_irq intc, 232 I2CBus **i2c_bus, ISABus **p_isa_bus) 233 { 234 qemu_irq *i8259; 235 ISABus *isa_bus; 236 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 237 238 isa_bus = vt82c686b_isa_init(pci_bus, PCI_DEVFN(slot, 0)); 239 if (!isa_bus) { 240 fprintf(stderr, "vt82c686b_init error\n"); 241 exit(1); 242 } 243 *p_isa_bus = isa_bus; 244 /* Interrupt controller */ 245 /* The 8259 -> IP5 */ 246 i8259 = i8259_init(isa_bus, intc); 247 isa_bus_irqs(isa_bus, i8259); 248 /* init other devices */ 249 i8254_pit_init(isa_bus, 0x40, 0, NULL); 250 i8257_dma_init(isa_bus, 0); 251 /* Super I/O */ 252 isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO); 253 254 ide_drive_get(hd, ARRAY_SIZE(hd)); 255 via_ide_init(pci_bus, hd, PCI_DEVFN(slot, 1)); 256 257 pci_create_simple(pci_bus, PCI_DEVFN(slot, 2), "vt82c686b-usb-uhci"); 258 pci_create_simple(pci_bus, PCI_DEVFN(slot, 3), "vt82c686b-usb-uhci"); 259 260 *i2c_bus = vt82c686b_pm_init(pci_bus, PCI_DEVFN(slot, 4), 0xeee1, NULL); 261 262 /* Audio support */ 263 vt82c686b_ac97_init(pci_bus, PCI_DEVFN(slot, 5)); 264 vt82c686b_mc97_init(pci_bus, PCI_DEVFN(slot, 6)); 265 } 266 267 /* Network support */ 268 static void network_init (PCIBus *pci_bus) 269 { 270 int i; 271 272 for(i = 0; i < nb_nics; i++) { 273 NICInfo *nd = &nd_table[i]; 274 const char *default_devaddr = NULL; 275 276 if (i == 0 && (!nd->model || strcmp(nd->model, "rtl8139") == 0)) { 277 /* The fulong board has a RTL8139 card using PCI SLOT 7 */ 278 default_devaddr = "07"; 279 } 280 281 pci_nic_init_nofail(nd, pci_bus, "rtl8139", default_devaddr); 282 } 283 } 284 285 static void mips_fulong2e_init(MachineState *machine) 286 { 287 ram_addr_t ram_size = machine->ram_size; 288 const char *kernel_filename = machine->kernel_filename; 289 const char *kernel_cmdline = machine->kernel_cmdline; 290 const char *initrd_filename = machine->initrd_filename; 291 char *filename; 292 MemoryRegion *address_space_mem = get_system_memory(); 293 MemoryRegion *ram = g_new(MemoryRegion, 1); 294 MemoryRegion *bios = g_new(MemoryRegion, 1); 295 long bios_size; 296 int64_t kernel_entry; 297 PCIBus *pci_bus; 298 ISABus *isa_bus; 299 I2CBus *smbus; 300 MIPSCPU *cpu; 301 CPUMIPSState *env; 302 303 /* init CPUs */ 304 cpu = MIPS_CPU(cpu_create(machine->cpu_type)); 305 env = &cpu->env; 306 307 qemu_register_reset(main_cpu_reset, cpu); 308 309 /* fulong 2e has 256M ram. */ 310 ram_size = 256 * MiB; 311 312 /* allocate RAM */ 313 memory_region_allocate_system_memory(ram, NULL, "fulong2e.ram", ram_size); 314 memory_region_init_ram(bios, NULL, "fulong2e.bios", BIOS_SIZE, 315 &error_fatal); 316 memory_region_set_readonly(bios, true); 317 318 memory_region_add_subregion(address_space_mem, 0, ram); 319 memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios); 320 321 /* We do not support flash operation, just loading pmon.bin as raw BIOS. 322 * Please use -L to set the BIOS path and -bios to set bios name. */ 323 324 if (kernel_filename) { 325 loaderparams.ram_size = ram_size; 326 loaderparams.kernel_filename = kernel_filename; 327 loaderparams.kernel_cmdline = kernel_cmdline; 328 loaderparams.initrd_filename = initrd_filename; 329 kernel_entry = load_kernel (env); 330 write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry); 331 } else { 332 if (bios_name == NULL) { 333 bios_name = FULONG_BIOSNAME; 334 } 335 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 336 if (filename) { 337 bios_size = load_image_targphys(filename, 0x1fc00000LL, 338 BIOS_SIZE); 339 g_free(filename); 340 } else { 341 bios_size = -1; 342 } 343 344 if ((bios_size < 0 || bios_size > BIOS_SIZE) && 345 !kernel_filename && !qtest_enabled()) { 346 error_report("Could not load MIPS bios '%s'", bios_name); 347 exit(1); 348 } 349 } 350 351 /* Init internal devices */ 352 cpu_mips_irq_init_cpu(cpu); 353 cpu_mips_clock_init(cpu); 354 355 /* North bridge, Bonito --> IP2 */ 356 pci_bus = bonito_init((qemu_irq *)&(env->irq[2])); 357 358 /* South bridge -> IP5 */ 359 vt82c686b_southbridge_init(pci_bus, FULONG2E_VIA_SLOT, env->irq[5], 360 &smbus, &isa_bus); 361 362 /* TODO: Populate SPD eeprom data. */ 363 smbus_eeprom_init(smbus, 1, eeprom_spd, sizeof(eeprom_spd)); 364 365 mc146818_rtc_init(isa_bus, 2000, NULL); 366 367 /* Network card: RTL8139D */ 368 network_init(pci_bus); 369 } 370 371 static void mips_fulong2e_machine_init(MachineClass *mc) 372 { 373 mc->desc = "Fulong 2e mini pc"; 374 mc->init = mips_fulong2e_init; 375 mc->block_default_type = IF_IDE; 376 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("Loongson-2E"); 377 } 378 379 DEFINE_MACHINE("fulong2e", mips_fulong2e_machine_init) 380