1 /* 2 * Coherent Processing System emulation. 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "hw/mips/cps.h" 23 #include "hw/mips/mips.h" 24 #include "hw/mips/cpudevs.h" 25 26 qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number) 27 { 28 MIPSCPU *cpu = MIPS_CPU(first_cpu); 29 CPUMIPSState *env = &cpu->env; 30 31 assert(pin_number < s->num_irq); 32 33 /* TODO: return GIC pins once implemented */ 34 return env->irq[pin_number]; 35 } 36 37 static void mips_cps_init(Object *obj) 38 { 39 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 40 MIPSCPSState *s = MIPS_CPS(obj); 41 42 /* Cover entire address space as there do not seem to be any 43 * constraints for the base address of CPC and GIC. */ 44 memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX); 45 sysbus_init_mmio(sbd, &s->container); 46 } 47 48 static void main_cpu_reset(void *opaque) 49 { 50 MIPSCPU *cpu = opaque; 51 CPUState *cs = CPU(cpu); 52 53 cpu_reset(cs); 54 55 /* All VPs are halted on reset. Leave powering up to CPC. */ 56 cs->halted = 1; 57 } 58 59 static void mips_cps_realize(DeviceState *dev, Error **errp) 60 { 61 MIPSCPSState *s = MIPS_CPS(dev); 62 CPUMIPSState *env; 63 MIPSCPU *cpu; 64 int i; 65 Error *err = NULL; 66 target_ulong gcr_base; 67 68 for (i = 0; i < s->num_vp; i++) { 69 cpu = cpu_mips_init(s->cpu_model); 70 if (cpu == NULL) { 71 error_setg(errp, "%s: CPU initialization failed\n", __func__); 72 return; 73 } 74 env = &cpu->env; 75 76 /* Init internal devices */ 77 cpu_mips_irq_init_cpu(env); 78 cpu_mips_clock_init(env); 79 qemu_register_reset(main_cpu_reset, cpu); 80 } 81 82 cpu = MIPS_CPU(first_cpu); 83 env = &cpu->env; 84 85 /* Global Configuration Registers */ 86 gcr_base = env->CP0_CMGCRBase << 4; 87 88 object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR); 89 qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default()); 90 91 object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err); 92 object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err); 93 object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err); 94 object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err); 95 if (err != NULL) { 96 error_propagate(errp, err); 97 return; 98 } 99 100 memory_region_add_subregion(&s->container, gcr_base, 101 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0)); 102 } 103 104 static Property mips_cps_properties[] = { 105 DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1), 106 DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 8), 107 DEFINE_PROP_STRING("cpu-model", MIPSCPSState, cpu_model), 108 DEFINE_PROP_END_OF_LIST() 109 }; 110 111 static void mips_cps_class_init(ObjectClass *klass, void *data) 112 { 113 DeviceClass *dc = DEVICE_CLASS(klass); 114 115 dc->realize = mips_cps_realize; 116 dc->props = mips_cps_properties; 117 } 118 119 static const TypeInfo mips_cps_info = { 120 .name = TYPE_MIPS_CPS, 121 .parent = TYPE_SYS_BUS_DEVICE, 122 .instance_size = sizeof(MIPSCPSState), 123 .instance_init = mips_cps_init, 124 .class_init = mips_cps_class_init, 125 }; 126 127 static void mips_cps_register_types(void) 128 { 129 type_register_static(&mips_cps_info); 130 } 131 132 type_init(mips_cps_register_types) 133