1 /* 2 * MIPS Boston development board emulation. 3 * 4 * Copyright (c) 2016 Imagination Technologies 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 23 #include "elf.h" 24 #include "hw/boards.h" 25 #include "hw/char/serial.h" 26 #include "hw/ide/pci.h" 27 #include "hw/ide/ahci.h" 28 #include "hw/loader.h" 29 #include "hw/loader-fit.h" 30 #include "hw/mips/bootloader.h" 31 #include "hw/mips/cps.h" 32 #include "hw/pci-host/xilinx-pcie.h" 33 #include "hw/qdev-clock.h" 34 #include "hw/qdev-properties.h" 35 #include "qapi/error.h" 36 #include "qemu/error-report.h" 37 #include "qemu/log.h" 38 #include "chardev/char.h" 39 #include "sysemu/device_tree.h" 40 #include "sysemu/sysemu.h" 41 #include "sysemu/qtest.h" 42 #include "sysemu/runstate.h" 43 44 #include <libfdt.h> 45 #include "qom/object.h" 46 47 #define TYPE_BOSTON "mips-boston" 48 typedef struct BostonState BostonState; 49 DECLARE_INSTANCE_CHECKER(BostonState, BOSTON, 50 TYPE_BOSTON) 51 52 struct BostonState { 53 SysBusDevice parent_obj; 54 55 MachineState *mach; 56 MIPSCPSState cps; 57 SerialMM *uart; 58 Clock *cpuclk; 59 60 CharBackend lcd_display; 61 char lcd_content[8]; 62 bool lcd_inited; 63 64 hwaddr kernel_entry; 65 hwaddr fdt_base; 66 }; 67 68 enum { 69 BOSTON_LOWDDR, 70 BOSTON_PCIE0, 71 BOSTON_PCIE1, 72 BOSTON_PCIE2, 73 BOSTON_PCIE2_MMIO, 74 BOSTON_CM, 75 BOSTON_GIC, 76 BOSTON_CDMM, 77 BOSTON_CPC, 78 BOSTON_PLATREG, 79 BOSTON_UART, 80 BOSTON_LCD, 81 BOSTON_FLASH, 82 BOSTON_PCIE1_MMIO, 83 BOSTON_PCIE0_MMIO, 84 BOSTON_HIGHDDR, 85 }; 86 87 static const MemMapEntry boston_memmap[] = { 88 [BOSTON_LOWDDR] = { 0x0, 0x10000000 }, 89 [BOSTON_PCIE0] = { 0x10000000, 0x2000000 }, 90 [BOSTON_PCIE1] = { 0x12000000, 0x2000000 }, 91 [BOSTON_PCIE2] = { 0x14000000, 0x2000000 }, 92 [BOSTON_PCIE2_MMIO] = { 0x16000000, 0x100000 }, 93 [BOSTON_CM] = { 0x16100000, 0x20000 }, 94 [BOSTON_GIC] = { 0x16120000, 0x20000 }, 95 [BOSTON_CDMM] = { 0x16140000, 0x8000 }, 96 [BOSTON_CPC] = { 0x16200000, 0x8000 }, 97 [BOSTON_PLATREG] = { 0x17ffd000, 0x1000 }, 98 [BOSTON_UART] = { 0x17ffe000, 0x20 }, 99 [BOSTON_LCD] = { 0x17fff000, 0x8 }, 100 [BOSTON_FLASH] = { 0x18000000, 0x8000000 }, 101 [BOSTON_PCIE1_MMIO] = { 0x20000000, 0x20000000 }, 102 [BOSTON_PCIE0_MMIO] = { 0x40000000, 0x40000000 }, 103 [BOSTON_HIGHDDR] = { 0x80000000, 0x0 }, 104 }; 105 106 enum boston_plat_reg { 107 PLAT_FPGA_BUILD = 0x00, 108 PLAT_CORE_CL = 0x04, 109 PLAT_WRAPPER_CL = 0x08, 110 PLAT_SYSCLK_STATUS = 0x0c, 111 PLAT_SOFTRST_CTL = 0x10, 112 #define PLAT_SOFTRST_CTL_SYSRESET (1 << 4) 113 PLAT_DDR3_STATUS = 0x14, 114 #define PLAT_DDR3_STATUS_LOCKED (1 << 0) 115 #define PLAT_DDR3_STATUS_CALIBRATED (1 << 2) 116 PLAT_PCIE_STATUS = 0x18, 117 #define PLAT_PCIE_STATUS_PCIE0_LOCKED (1 << 0) 118 #define PLAT_PCIE_STATUS_PCIE1_LOCKED (1 << 8) 119 #define PLAT_PCIE_STATUS_PCIE2_LOCKED (1 << 16) 120 PLAT_FLASH_CTL = 0x1c, 121 PLAT_SPARE0 = 0x20, 122 PLAT_SPARE1 = 0x24, 123 PLAT_SPARE2 = 0x28, 124 PLAT_SPARE3 = 0x2c, 125 PLAT_MMCM_DIV = 0x30, 126 #define PLAT_MMCM_DIV_CLK0DIV_SHIFT 0 127 #define PLAT_MMCM_DIV_INPUT_SHIFT 8 128 #define PLAT_MMCM_DIV_MUL_SHIFT 16 129 #define PLAT_MMCM_DIV_CLK1DIV_SHIFT 24 130 PLAT_BUILD_CFG = 0x34, 131 #define PLAT_BUILD_CFG_IOCU_EN (1 << 0) 132 #define PLAT_BUILD_CFG_PCIE0_EN (1 << 1) 133 #define PLAT_BUILD_CFG_PCIE1_EN (1 << 2) 134 #define PLAT_BUILD_CFG_PCIE2_EN (1 << 3) 135 PLAT_DDR_CFG = 0x38, 136 #define PLAT_DDR_CFG_SIZE (0xf << 0) 137 #define PLAT_DDR_CFG_MHZ (0xfff << 4) 138 PLAT_NOC_PCIE0_ADDR = 0x3c, 139 PLAT_NOC_PCIE1_ADDR = 0x40, 140 PLAT_NOC_PCIE2_ADDR = 0x44, 141 PLAT_SYS_CTL = 0x48, 142 }; 143 144 static void boston_lcd_event(void *opaque, QEMUChrEvent event) 145 { 146 BostonState *s = opaque; 147 if (event == CHR_EVENT_OPENED && !s->lcd_inited) { 148 qemu_chr_fe_printf(&s->lcd_display, " "); 149 s->lcd_inited = true; 150 } 151 } 152 153 static uint64_t boston_lcd_read(void *opaque, hwaddr addr, 154 unsigned size) 155 { 156 BostonState *s = opaque; 157 uint64_t val = 0; 158 159 switch (size) { 160 case 8: 161 val |= (uint64_t)s->lcd_content[(addr + 7) & 0x7] << 56; 162 val |= (uint64_t)s->lcd_content[(addr + 6) & 0x7] << 48; 163 val |= (uint64_t)s->lcd_content[(addr + 5) & 0x7] << 40; 164 val |= (uint64_t)s->lcd_content[(addr + 4) & 0x7] << 32; 165 /* fall through */ 166 case 4: 167 val |= (uint64_t)s->lcd_content[(addr + 3) & 0x7] << 24; 168 val |= (uint64_t)s->lcd_content[(addr + 2) & 0x7] << 16; 169 /* fall through */ 170 case 2: 171 val |= (uint64_t)s->lcd_content[(addr + 1) & 0x7] << 8; 172 /* fall through */ 173 case 1: 174 val |= (uint64_t)s->lcd_content[(addr + 0) & 0x7]; 175 break; 176 } 177 178 return val; 179 } 180 181 static void boston_lcd_write(void *opaque, hwaddr addr, 182 uint64_t val, unsigned size) 183 { 184 BostonState *s = opaque; 185 186 switch (size) { 187 case 8: 188 s->lcd_content[(addr + 7) & 0x7] = val >> 56; 189 s->lcd_content[(addr + 6) & 0x7] = val >> 48; 190 s->lcd_content[(addr + 5) & 0x7] = val >> 40; 191 s->lcd_content[(addr + 4) & 0x7] = val >> 32; 192 /* fall through */ 193 case 4: 194 s->lcd_content[(addr + 3) & 0x7] = val >> 24; 195 s->lcd_content[(addr + 2) & 0x7] = val >> 16; 196 /* fall through */ 197 case 2: 198 s->lcd_content[(addr + 1) & 0x7] = val >> 8; 199 /* fall through */ 200 case 1: 201 s->lcd_content[(addr + 0) & 0x7] = val; 202 break; 203 } 204 205 qemu_chr_fe_printf(&s->lcd_display, 206 "\r%-8.8s", s->lcd_content); 207 } 208 209 static const MemoryRegionOps boston_lcd_ops = { 210 .read = boston_lcd_read, 211 .write = boston_lcd_write, 212 .endianness = DEVICE_NATIVE_ENDIAN, 213 }; 214 215 static uint64_t boston_platreg_read(void *opaque, hwaddr addr, 216 unsigned size) 217 { 218 BostonState *s = opaque; 219 uint32_t gic_freq, val; 220 221 if (size != 4) { 222 qemu_log_mask(LOG_UNIMP, "%uB platform register read\n", size); 223 return 0; 224 } 225 226 switch (addr & 0xffff) { 227 case PLAT_FPGA_BUILD: 228 case PLAT_CORE_CL: 229 case PLAT_WRAPPER_CL: 230 return 0; 231 case PLAT_DDR3_STATUS: 232 return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED; 233 case PLAT_MMCM_DIV: 234 gic_freq = mips_gictimer_get_freq(s->cps.gic.gic_timer) / 1000000; 235 val = gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT; 236 val |= 1 << PLAT_MMCM_DIV_MUL_SHIFT; 237 val |= 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT; 238 val |= 1 << PLAT_MMCM_DIV_CLK1DIV_SHIFT; 239 return val; 240 case PLAT_BUILD_CFG: 241 val = PLAT_BUILD_CFG_PCIE0_EN; 242 val |= PLAT_BUILD_CFG_PCIE1_EN; 243 val |= PLAT_BUILD_CFG_PCIE2_EN; 244 return val; 245 case PLAT_DDR_CFG: 246 val = s->mach->ram_size / GiB; 247 assert(!(val & ~PLAT_DDR_CFG_SIZE)); 248 val |= PLAT_DDR_CFG_MHZ; 249 return val; 250 default: 251 qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx "\n", 252 addr & 0xffff); 253 return 0; 254 } 255 } 256 257 static void boston_platreg_write(void *opaque, hwaddr addr, 258 uint64_t val, unsigned size) 259 { 260 if (size != 4) { 261 qemu_log_mask(LOG_UNIMP, "%uB platform register write\n", size); 262 return; 263 } 264 265 switch (addr & 0xffff) { 266 case PLAT_FPGA_BUILD: 267 case PLAT_CORE_CL: 268 case PLAT_WRAPPER_CL: 269 case PLAT_DDR3_STATUS: 270 case PLAT_PCIE_STATUS: 271 case PLAT_MMCM_DIV: 272 case PLAT_BUILD_CFG: 273 case PLAT_DDR_CFG: 274 /* read only */ 275 break; 276 case PLAT_SOFTRST_CTL: 277 if (val & PLAT_SOFTRST_CTL_SYSRESET) { 278 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 279 } 280 break; 281 default: 282 qemu_log_mask(LOG_UNIMP, "Write platform register 0x%" HWADDR_PRIx 283 " = 0x%" PRIx64 "\n", addr & 0xffff, val); 284 break; 285 } 286 } 287 288 static const MemoryRegionOps boston_platreg_ops = { 289 .read = boston_platreg_read, 290 .write = boston_platreg_write, 291 .endianness = DEVICE_NATIVE_ENDIAN, 292 }; 293 294 static void mips_boston_instance_init(Object *obj) 295 { 296 BostonState *s = BOSTON(obj); 297 298 s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); 299 clock_set_hz(s->cpuclk, 1000000000); /* 1 GHz */ 300 } 301 302 static const TypeInfo boston_device = { 303 .name = TYPE_BOSTON, 304 .parent = TYPE_SYS_BUS_DEVICE, 305 .instance_size = sizeof(BostonState), 306 .instance_init = mips_boston_instance_init, 307 }; 308 309 static void boston_register_types(void) 310 { 311 type_register_static(&boston_device); 312 } 313 type_init(boston_register_types) 314 315 static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr) 316 { 317 uint64_t regaddr; 318 319 /* Move CM GCRs */ 320 regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS), 321 bl_gen_write_ulong(&p, regaddr, 322 boston_memmap[BOSTON_CM].base); 323 324 /* Move & enable GIC GCRs */ 325 regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base 326 + GCR_GIC_BASE_OFS), 327 bl_gen_write_ulong(&p, regaddr, 328 boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK); 329 330 /* Move & enable CPC GCRs */ 331 regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base 332 + GCR_CPC_BASE_OFS), 333 bl_gen_write_ulong(&p, regaddr, 334 boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK); 335 336 /* 337 * Setup argument registers to follow the UHI boot protocol: 338 * 339 * a0/$4 = -2 340 * a1/$5 = virtual address of FDT 341 * a2/$6 = 0 342 * a3/$7 = 0 343 */ 344 bl_gen_jump_kernel(&p, 0, (int32_t)-2, fdt_addr, 0, 0, kernel_entry); 345 } 346 347 static const void *boston_fdt_filter(void *opaque, const void *fdt_orig, 348 const void *match_data, hwaddr *load_addr) 349 { 350 BostonState *s = BOSTON(opaque); 351 MachineState *machine = s->mach; 352 const char *cmdline; 353 int err; 354 size_t ram_low_sz, ram_high_sz; 355 size_t fdt_sz = fdt_totalsize(fdt_orig) * 2; 356 g_autofree void *fdt = g_malloc0(fdt_sz); 357 358 err = fdt_open_into(fdt_orig, fdt, fdt_sz); 359 if (err) { 360 fprintf(stderr, "unable to open FDT\n"); 361 return NULL; 362 } 363 364 cmdline = (machine->kernel_cmdline && machine->kernel_cmdline[0]) 365 ? machine->kernel_cmdline : " "; 366 err = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 367 if (err < 0) { 368 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 369 return NULL; 370 } 371 372 ram_low_sz = MIN(256 * MiB, machine->ram_size); 373 ram_high_sz = machine->ram_size - ram_low_sz; 374 qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg", 375 1, boston_memmap[BOSTON_LOWDDR].base, 1, ram_low_sz, 376 1, boston_memmap[BOSTON_HIGHDDR].base + ram_low_sz, 377 1, ram_high_sz); 378 379 fdt = g_realloc(fdt, fdt_totalsize(fdt)); 380 qemu_fdt_dumpdtb(fdt, fdt_sz); 381 382 s->fdt_base = *load_addr; 383 384 return g_steal_pointer(&fdt); 385 } 386 387 static const void *boston_kernel_filter(void *opaque, const void *kernel, 388 hwaddr *load_addr, hwaddr *entry_addr) 389 { 390 BostonState *s = BOSTON(opaque); 391 392 s->kernel_entry = *entry_addr; 393 394 return kernel; 395 } 396 397 static const struct fit_loader_match boston_matches[] = { 398 { "img,boston" }, 399 { NULL }, 400 }; 401 402 static const struct fit_loader boston_fit_loader = { 403 .matches = boston_matches, 404 .addr_to_phys = cpu_mips_kseg0_to_phys, 405 .fdt_filter = boston_fdt_filter, 406 .kernel_filter = boston_kernel_filter, 407 }; 408 409 static inline XilinxPCIEHost * 410 xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr, 411 hwaddr cfg_base, uint64_t cfg_size, 412 hwaddr mmio_base, uint64_t mmio_size, 413 qemu_irq irq, bool link_up) 414 { 415 DeviceState *dev; 416 MemoryRegion *cfg, *mmio; 417 418 dev = qdev_new(TYPE_XILINX_PCIE_HOST); 419 420 qdev_prop_set_uint32(dev, "bus_nr", bus_nr); 421 qdev_prop_set_uint64(dev, "cfg_base", cfg_base); 422 qdev_prop_set_uint64(dev, "cfg_size", cfg_size); 423 qdev_prop_set_uint64(dev, "mmio_base", mmio_base); 424 qdev_prop_set_uint64(dev, "mmio_size", mmio_size); 425 qdev_prop_set_bit(dev, "link_up", link_up); 426 427 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 428 429 cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 430 memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0); 431 432 mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 433 memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0); 434 435 qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq); 436 437 return XILINX_PCIE_HOST(dev); 438 } 439 440 static void boston_mach_init(MachineState *machine) 441 { 442 DeviceState *dev; 443 BostonState *s; 444 MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg; 445 MemoryRegion *sys_mem = get_system_memory(); 446 XilinxPCIEHost *pcie2; 447 PCIDevice *ahci; 448 DriveInfo *hd[6]; 449 Chardev *chr; 450 int fw_size, fit_err; 451 452 if ((machine->ram_size % GiB) || 453 (machine->ram_size > (2 * GiB))) { 454 error_report("Memory size must be 1GB or 2GB"); 455 exit(1); 456 } 457 458 dev = qdev_new(TYPE_BOSTON); 459 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 460 461 s = BOSTON(dev); 462 s->mach = machine; 463 464 if (!cpu_type_supports_cps_smp(machine->cpu_type)) { 465 error_report("Boston requires CPUs which support CPS"); 466 exit(1); 467 } 468 469 object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS); 470 object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, 471 &error_fatal); 472 object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus, 473 &error_fatal); 474 qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", 475 qdev_get_clock_out(dev, "cpu-refclk")); 476 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); 477 478 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); 479 480 flash = g_new(MemoryRegion, 1); 481 memory_region_init_rom(flash, NULL, "boston.flash", 482 boston_memmap[BOSTON_FLASH].size, &error_fatal); 483 memory_region_add_subregion_overlap(sys_mem, 484 boston_memmap[BOSTON_FLASH].base, 485 flash, 0); 486 487 memory_region_add_subregion_overlap(sys_mem, 488 boston_memmap[BOSTON_HIGHDDR].base, 489 machine->ram, 0); 490 491 ddr_low_alias = g_new(MemoryRegion, 1); 492 memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", 493 machine->ram, 0, 494 MIN(machine->ram_size, (256 * MiB))); 495 memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); 496 497 xilinx_pcie_init(sys_mem, 0, 498 boston_memmap[BOSTON_PCIE0].base, 499 boston_memmap[BOSTON_PCIE0].size, 500 boston_memmap[BOSTON_PCIE0_MMIO].base, 501 boston_memmap[BOSTON_PCIE0_MMIO].size, 502 get_cps_irq(&s->cps, 2), false); 503 504 xilinx_pcie_init(sys_mem, 1, 505 boston_memmap[BOSTON_PCIE1].base, 506 boston_memmap[BOSTON_PCIE1].size, 507 boston_memmap[BOSTON_PCIE1_MMIO].base, 508 boston_memmap[BOSTON_PCIE1_MMIO].size, 509 get_cps_irq(&s->cps, 1), false); 510 511 pcie2 = xilinx_pcie_init(sys_mem, 2, 512 boston_memmap[BOSTON_PCIE2].base, 513 boston_memmap[BOSTON_PCIE2].size, 514 boston_memmap[BOSTON_PCIE2_MMIO].base, 515 boston_memmap[BOSTON_PCIE2_MMIO].size, 516 get_cps_irq(&s->cps, 0), true); 517 518 platreg = g_new(MemoryRegion, 1); 519 memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, 520 "boston-platregs", 521 boston_memmap[BOSTON_PLATREG].size); 522 memory_region_add_subregion_overlap(sys_mem, 523 boston_memmap[BOSTON_PLATREG].base, platreg, 0); 524 525 s->uart = serial_mm_init(sys_mem, boston_memmap[BOSTON_UART].base, 2, 526 get_cps_irq(&s->cps, 3), 10000000, 527 serial_hd(0), DEVICE_NATIVE_ENDIAN); 528 529 lcd = g_new(MemoryRegion, 1); 530 memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8); 531 memory_region_add_subregion_overlap(sys_mem, 532 boston_memmap[BOSTON_LCD].base, lcd, 0); 533 534 chr = qemu_chr_new("lcd", "vc:320x240", NULL); 535 qemu_chr_fe_init(&s->lcd_display, chr, NULL); 536 qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL, 537 boston_lcd_event, NULL, s, NULL, true); 538 539 ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, 540 PCI_DEVFN(0, 0), 541 true, TYPE_ICH9_AHCI); 542 g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(ahci)); 543 ide_drive_get(hd, ahci_get_num_ports(ahci)); 544 ahci_ide_create_devs(ahci, hd); 545 546 if (machine->firmware) { 547 fw_size = load_image_targphys(machine->firmware, 548 0x1fc00000, 4 * MiB); 549 if (fw_size == -1) { 550 error_report("unable to load firmware image '%s'", 551 machine->firmware); 552 exit(1); 553 } 554 } else if (machine->kernel_filename) { 555 uint64_t kernel_entry, kernel_high, kernel_size; 556 557 kernel_size = load_elf(machine->kernel_filename, NULL, 558 cpu_mips_kseg0_to_phys, NULL, 559 &kernel_entry, NULL, &kernel_high, 560 NULL, 0, EM_MIPS, 1, 0); 561 562 if (kernel_size) { 563 hwaddr dtb_paddr = QEMU_ALIGN_UP(kernel_high, 64 * KiB); 564 hwaddr dtb_vaddr = cpu_mips_phys_to_kseg0(NULL, dtb_paddr); 565 566 s->kernel_entry = kernel_entry; 567 if (machine->dtb) { 568 int dt_size; 569 g_autofree const void *dtb_file_data, *dtb_load_data; 570 571 dtb_file_data = load_device_tree(machine->dtb, &dt_size); 572 dtb_load_data = boston_fdt_filter(s, dtb_file_data, 573 NULL, &dtb_vaddr); 574 575 /* Calculate real fdt size after filter */ 576 dt_size = fdt_totalsize(dtb_load_data); 577 rom_add_blob_fixed("dtb", dtb_load_data, dt_size, dtb_paddr); 578 } 579 } else { 580 /* Try to load file as FIT */ 581 fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s); 582 if (fit_err) { 583 error_report("unable to load kernel image"); 584 exit(1); 585 } 586 } 587 588 gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000, 589 s->kernel_entry, s->fdt_base); 590 } else if (!qtest_enabled()) { 591 error_report("Please provide either a -kernel or -bios argument"); 592 exit(1); 593 } 594 } 595 596 static void boston_mach_class_init(MachineClass *mc) 597 { 598 mc->desc = "MIPS Boston"; 599 mc->init = boston_mach_init; 600 mc->block_default_type = IF_IDE; 601 mc->default_ram_size = 1 * GiB; 602 mc->default_ram_id = "boston.ddr"; 603 mc->max_cpus = 16; 604 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400"); 605 } 606 607 DEFINE_MACHINE("boston", boston_mach_class_init) 608