1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/sysemu.h" 14 #include "sysemu/qtest.h" 15 #include "sysemu/runstate.h" 16 #include "sysemu/reset.h" 17 #include "sysemu/rtc.h" 18 #include "hw/loongarch/virt.h" 19 #include "exec/address-spaces.h" 20 #include "hw/irq.h" 21 #include "net/net.h" 22 #include "hw/loader.h" 23 #include "elf.h" 24 #include "hw/intc/loongarch_ipi.h" 25 #include "hw/intc/loongarch_extioi.h" 26 #include "hw/intc/loongarch_pch_pic.h" 27 #include "hw/intc/loongarch_pch_msi.h" 28 #include "hw/pci-host/ls7a.h" 29 #include "hw/pci-host/gpex.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/loongarch/fw_cfg.h" 32 #include "target/loongarch/cpu.h" 33 #include "hw/firmware/smbios.h" 34 #include "hw/acpi/aml-build.h" 35 #include "qapi/qapi-visit-common.h" 36 #include "hw/acpi/generic_event_device.h" 37 #include "hw/mem/nvdimm.h" 38 #include "sysemu/device_tree.h" 39 #include <libfdt.h> 40 #include "hw/core/sysbus-fdt.h" 41 #include "hw/platform-bus.h" 42 #include "hw/display/ramfb.h" 43 44 static void create_fdt(LoongArchMachineState *lams) 45 { 46 MachineState *ms = MACHINE(lams); 47 48 ms->fdt = create_device_tree(&lams->fdt_size); 49 if (!ms->fdt) { 50 error_report("create_device_tree() failed"); 51 exit(1); 52 } 53 54 /* Header */ 55 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 56 "linux,dummy-loongson3"); 57 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 58 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 59 } 60 61 static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) 62 { 63 int num; 64 const MachineState *ms = MACHINE(lams); 65 int smp_cpus = ms->smp.cpus; 66 67 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 68 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 69 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 70 71 /* cpu nodes */ 72 for (num = smp_cpus - 1; num >= 0; num--) { 73 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 74 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 75 76 qemu_fdt_add_subnode(ms->fdt, nodename); 77 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 78 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 79 cpu->dtb_compatible); 80 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 81 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 82 qemu_fdt_alloc_phandle(ms->fdt)); 83 g_free(nodename); 84 } 85 86 /*cpu map */ 87 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 88 89 for (num = smp_cpus - 1; num >= 0; num--) { 90 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 91 char *map_path; 92 93 if (ms->smp.threads > 1) { 94 map_path = g_strdup_printf( 95 "/cpus/cpu-map/socket%d/core%d/thread%d", 96 num / (ms->smp.cores * ms->smp.threads), 97 (num / ms->smp.threads) % ms->smp.cores, 98 num % ms->smp.threads); 99 } else { 100 map_path = g_strdup_printf( 101 "/cpus/cpu-map/socket%d/core%d", 102 num / ms->smp.cores, 103 num % ms->smp.cores); 104 } 105 qemu_fdt_add_path(ms->fdt, map_path); 106 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 107 108 g_free(map_path); 109 g_free(cpu_path); 110 } 111 } 112 113 static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) 114 { 115 char *nodename; 116 hwaddr base = VIRT_FWCFG_BASE; 117 const MachineState *ms = MACHINE(lams); 118 119 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 120 qemu_fdt_add_subnode(ms->fdt, nodename); 121 qemu_fdt_setprop_string(ms->fdt, nodename, 122 "compatible", "qemu,fw-cfg-mmio"); 123 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 124 2, base, 2, 0x18); 125 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 126 g_free(nodename); 127 } 128 129 static void fdt_add_pcie_node(const LoongArchMachineState *lams) 130 { 131 char *nodename; 132 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 133 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 134 hwaddr base_pio = VIRT_PCI_IO_BASE; 135 hwaddr size_pio = VIRT_PCI_IO_SIZE; 136 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 137 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 138 hwaddr base = base_pcie; 139 140 const MachineState *ms = MACHINE(lams); 141 142 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 143 qemu_fdt_add_subnode(ms->fdt, nodename); 144 qemu_fdt_setprop_string(ms->fdt, nodename, 145 "compatible", "pci-host-ecam-generic"); 146 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 147 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 148 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 149 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 150 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 151 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 152 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 153 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 154 2, base_pcie, 2, size_pcie); 155 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 156 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 157 2, base_pio, 2, size_pio, 158 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 159 2, base_mmio, 2, size_mmio); 160 g_free(nodename); 161 qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size); 162 } 163 164 static void fdt_add_irqchip_node(LoongArchMachineState *lams) 165 { 166 MachineState *ms = MACHINE(lams); 167 char *nodename; 168 uint32_t irqchip_phandle; 169 170 irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt); 171 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle); 172 173 nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE); 174 qemu_fdt_add_subnode(ms->fdt, nodename); 175 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 176 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 177 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 178 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 179 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 180 181 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 182 "loongarch,ls7a"); 183 184 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 185 2, VIRT_IOAPIC_REG_BASE, 186 2, PCH_PIC_ROUTE_ENTRY_OFFSET); 187 188 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle); 189 g_free(nodename); 190 } 191 192 #define PM_BASE 0x10080000 193 #define PM_SIZE 0x100 194 #define PM_CTRL 0x10 195 196 static void virt_build_smbios(LoongArchMachineState *lams) 197 { 198 MachineState *ms = MACHINE(lams); 199 MachineClass *mc = MACHINE_GET_CLASS(lams); 200 uint8_t *smbios_tables, *smbios_anchor; 201 size_t smbios_tables_len, smbios_anchor_len; 202 const char *product = "QEMU Virtual Machine"; 203 204 if (!lams->fw_cfg) { 205 return; 206 } 207 208 smbios_set_defaults("QEMU", product, mc->name, false, 209 true, SMBIOS_ENTRY_POINT_TYPE_64); 210 211 smbios_get_tables(ms, NULL, 0, &smbios_tables, &smbios_tables_len, 212 &smbios_anchor, &smbios_anchor_len, &error_fatal); 213 214 if (smbios_anchor) { 215 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", 216 smbios_tables, smbios_tables_len); 217 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", 218 smbios_anchor, smbios_anchor_len); 219 } 220 } 221 222 static void virt_machine_done(Notifier *notifier, void *data) 223 { 224 LoongArchMachineState *lams = container_of(notifier, 225 LoongArchMachineState, machine_done); 226 virt_build_smbios(lams); 227 loongarch_acpi_setup(lams); 228 } 229 230 struct memmap_entry { 231 uint64_t address; 232 uint64_t length; 233 uint32_t type; 234 uint32_t reserved; 235 }; 236 237 static struct memmap_entry *memmap_table; 238 static unsigned memmap_entries; 239 240 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 241 { 242 /* Ensure there are no duplicate entries. */ 243 for (unsigned i = 0; i < memmap_entries; i++) { 244 assert(memmap_table[i].address != address); 245 } 246 247 memmap_table = g_renew(struct memmap_entry, memmap_table, 248 memmap_entries + 1); 249 memmap_table[memmap_entries].address = cpu_to_le64(address); 250 memmap_table[memmap_entries].length = cpu_to_le64(length); 251 memmap_table[memmap_entries].type = cpu_to_le32(type); 252 memmap_table[memmap_entries].reserved = 0; 253 memmap_entries++; 254 } 255 256 /* 257 * This is a placeholder for missing ACPI, 258 * and will eventually be replaced. 259 */ 260 static uint64_t loongarch_virt_pm_read(void *opaque, hwaddr addr, unsigned size) 261 { 262 return 0; 263 } 264 265 static void loongarch_virt_pm_write(void *opaque, hwaddr addr, 266 uint64_t val, unsigned size) 267 { 268 if (addr != PM_CTRL) { 269 return; 270 } 271 272 switch (val) { 273 case 0x00: 274 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 275 return; 276 case 0xff: 277 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 278 return; 279 default: 280 return; 281 } 282 } 283 284 static const MemoryRegionOps loongarch_virt_pm_ops = { 285 .read = loongarch_virt_pm_read, 286 .write = loongarch_virt_pm_write, 287 .endianness = DEVICE_NATIVE_ENDIAN, 288 .valid = { 289 .min_access_size = 1, 290 .max_access_size = 1 291 } 292 }; 293 294 static struct _loaderparams { 295 uint64_t ram_size; 296 const char *kernel_filename; 297 const char *kernel_cmdline; 298 const char *initrd_filename; 299 } loaderparams; 300 301 static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr) 302 { 303 return addr & 0x1fffffffll; 304 } 305 306 static int64_t load_kernel_info(void) 307 { 308 uint64_t kernel_entry, kernel_low, kernel_high; 309 ssize_t kernel_size; 310 311 kernel_size = load_elf(loaderparams.kernel_filename, NULL, 312 cpu_loongarch_virt_to_phys, NULL, 313 &kernel_entry, &kernel_low, 314 &kernel_high, NULL, 0, 315 EM_LOONGARCH, 1, 0); 316 317 if (kernel_size < 0) { 318 error_report("could not load kernel '%s': %s", 319 loaderparams.kernel_filename, 320 load_elf_strerror(kernel_size)); 321 exit(1); 322 } 323 return kernel_entry; 324 } 325 326 static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams) 327 { 328 DeviceState *dev; 329 MachineState *ms = MACHINE(lams); 330 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 331 332 if (ms->ram_slots) { 333 event |= ACPI_GED_MEM_HOTPLUG_EVT; 334 } 335 dev = qdev_new(TYPE_ACPI_GED); 336 qdev_prop_set_uint32(dev, "ged-event", event); 337 338 /* ged event */ 339 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 340 /* memory hotplug */ 341 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 342 /* ged regs used for reset and power down */ 343 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 344 345 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 346 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - PCH_PIC_IRQ_OFFSET)); 347 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 348 return dev; 349 } 350 351 static DeviceState *create_platform_bus(DeviceState *pch_pic) 352 { 353 DeviceState *dev; 354 SysBusDevice *sysbus; 355 int i, irq; 356 MemoryRegion *sysmem = get_system_memory(); 357 358 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 359 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 360 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 361 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 362 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 363 364 sysbus = SYS_BUS_DEVICE(dev); 365 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 366 irq = VIRT_PLATFORM_BUS_IRQ - PCH_PIC_IRQ_OFFSET + i; 367 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 368 } 369 370 memory_region_add_subregion(sysmem, 371 VIRT_PLATFORM_BUS_BASEADDRESS, 372 sysbus_mmio_get_region(sysbus, 0)); 373 return dev; 374 } 375 376 static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams) 377 { 378 DeviceState *gpex_dev; 379 SysBusDevice *d; 380 PCIBus *pci_bus; 381 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 382 MemoryRegion *mmio_alias, *mmio_reg, *pm_mem; 383 int i; 384 385 gpex_dev = qdev_new(TYPE_GPEX_HOST); 386 d = SYS_BUS_DEVICE(gpex_dev); 387 sysbus_realize_and_unref(d, &error_fatal); 388 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 389 390 /* Map only part size_ecam bytes of ECAM space */ 391 ecam_alias = g_new0(MemoryRegion, 1); 392 ecam_reg = sysbus_mmio_get_region(d, 0); 393 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 394 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 395 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 396 ecam_alias); 397 398 /* Map PCI mem space */ 399 mmio_alias = g_new0(MemoryRegion, 1); 400 mmio_reg = sysbus_mmio_get_region(d, 1); 401 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 402 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 403 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 404 mmio_alias); 405 406 /* Map PCI IO port space. */ 407 pio_alias = g_new0(MemoryRegion, 1); 408 pio_reg = sysbus_mmio_get_region(d, 2); 409 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 410 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 411 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 412 pio_alias); 413 414 for (i = 0; i < GPEX_NUM_IRQS; i++) { 415 sysbus_connect_irq(d, i, 416 qdev_get_gpio_in(pch_pic, 16 + i)); 417 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 418 } 419 420 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 421 qdev_get_gpio_in(pch_pic, 422 VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET), 423 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 424 425 /* Network init */ 426 for (i = 0; i < nb_nics; i++) { 427 NICInfo *nd = &nd_table[i]; 428 429 if (!nd->model) { 430 nd->model = g_strdup("virtio"); 431 } 432 433 pci_nic_init_nofail(nd, pci_bus, nd->model, NULL); 434 } 435 436 /* 437 * There are some invalid guest memory access. 438 * Create some unimplemented devices to emulate this. 439 */ 440 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 441 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 442 qdev_get_gpio_in(pch_pic, 443 VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET)); 444 445 pm_mem = g_new(MemoryRegion, 1); 446 memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops, 447 NULL, "loongarch_virt_pm", PM_SIZE); 448 memory_region_add_subregion(get_system_memory(), PM_BASE, pm_mem); 449 /* acpi ged */ 450 lams->acpi_ged = create_acpi_ged(pch_pic, lams); 451 /* platform bus */ 452 lams->platform_bus_dev = create_platform_bus(pch_pic); 453 } 454 455 static void loongarch_irq_init(LoongArchMachineState *lams) 456 { 457 MachineState *ms = MACHINE(lams); 458 DeviceState *pch_pic, *pch_msi, *cpudev; 459 DeviceState *ipi, *extioi; 460 SysBusDevice *d; 461 LoongArchCPU *lacpu; 462 CPULoongArchState *env; 463 CPUState *cpu_state; 464 int cpu, pin, i; 465 466 ipi = qdev_new(TYPE_LOONGARCH_IPI); 467 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 468 469 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 470 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 471 472 /* 473 * The connection of interrupts: 474 * +-----+ +---------+ +-------+ 475 * | IPI |--> | CPUINTC | <-- | Timer | 476 * +-----+ +---------+ +-------+ 477 * ^ 478 * | 479 * +---------+ 480 * | EIOINTC | 481 * +---------+ 482 * ^ ^ 483 * | | 484 * +---------+ +---------+ 485 * | PCH-PIC | | PCH-MSI | 486 * +---------+ +---------+ 487 * ^ ^ ^ 488 * | | | 489 * +--------+ +---------+ +---------+ 490 * | UARTs | | Devices | | Devices | 491 * +--------+ +---------+ +---------+ 492 */ 493 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 494 cpu_state = qemu_get_cpu(cpu); 495 cpudev = DEVICE(cpu_state); 496 lacpu = LOONGARCH_CPU(cpu_state); 497 env = &(lacpu->env); 498 499 /* connect ipi irq to cpu irq */ 500 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); 501 /* IPI iocsr memory region */ 502 memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX, 503 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 504 cpu * 2)); 505 memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR, 506 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 507 cpu * 2 + 1)); 508 /* extioi iocsr memory region */ 509 memory_region_add_subregion(&env->system_iocsr, APIC_BASE, 510 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 511 cpu)); 512 } 513 514 /* 515 * connect ext irq to the cpu irq 516 * cpu_pin[9:2] <= intc_pin[7:0] 517 */ 518 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 519 cpudev = DEVICE(qemu_get_cpu(cpu)); 520 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 521 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 522 qdev_get_gpio_in(cpudev, pin + 2)); 523 } 524 } 525 526 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 527 d = SYS_BUS_DEVICE(pch_pic); 528 sysbus_realize_and_unref(d, &error_fatal); 529 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 530 sysbus_mmio_get_region(d, 0)); 531 memory_region_add_subregion(get_system_memory(), 532 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 533 sysbus_mmio_get_region(d, 1)); 534 memory_region_add_subregion(get_system_memory(), 535 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 536 sysbus_mmio_get_region(d, 2)); 537 538 /* Connect 64 pch_pic irqs to extioi */ 539 for (int i = 0; i < PCH_PIC_IRQ_NUM; i++) { 540 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 541 } 542 543 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 544 qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START); 545 d = SYS_BUS_DEVICE(pch_msi); 546 sysbus_realize_and_unref(d, &error_fatal); 547 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 548 for (i = 0; i < PCH_MSI_IRQ_NUM; i++) { 549 /* Connect 192 pch_msi irqs to extioi */ 550 qdev_connect_gpio_out(DEVICE(d), i, 551 qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START)); 552 } 553 554 loongarch_devices_init(pch_pic, lams); 555 } 556 557 static void loongarch_firmware_init(LoongArchMachineState *lams) 558 { 559 char *filename = MACHINE(lams)->firmware; 560 char *bios_name = NULL; 561 int bios_size; 562 563 lams->bios_loaded = false; 564 if (filename) { 565 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 566 if (!bios_name) { 567 error_report("Could not find ROM image '%s'", filename); 568 exit(1); 569 } 570 571 bios_size = load_image_targphys(bios_name, VIRT_BIOS_BASE, VIRT_BIOS_SIZE); 572 if (bios_size < 0) { 573 error_report("Could not load ROM image '%s'", bios_name); 574 exit(1); 575 } 576 577 g_free(bios_name); 578 579 memory_region_init_ram(&lams->bios, NULL, "loongarch.bios", 580 VIRT_BIOS_SIZE, &error_fatal); 581 memory_region_set_readonly(&lams->bios, true); 582 memory_region_add_subregion(get_system_memory(), VIRT_BIOS_BASE, &lams->bios); 583 lams->bios_loaded = true; 584 } 585 586 } 587 588 static void reset_load_elf(void *opaque) 589 { 590 LoongArchCPU *cpu = opaque; 591 CPULoongArchState *env = &cpu->env; 592 593 cpu_reset(CPU(cpu)); 594 if (env->load_elf) { 595 cpu_set_pc(CPU(cpu), env->elf_address); 596 } 597 } 598 599 /* Load an image file into an fw_cfg entry identified by key. */ 600 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 601 uint16_t data_key, const char *image_name, 602 bool try_decompress) 603 { 604 size_t size = -1; 605 uint8_t *data; 606 607 if (image_name == NULL) { 608 return; 609 } 610 611 if (try_decompress) { 612 size = load_image_gzipped_buffer(image_name, 613 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 614 } 615 616 if (size == (size_t)-1) { 617 gchar *contents; 618 gsize length; 619 620 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 621 error_report("failed to load \"%s\"", image_name); 622 exit(1); 623 } 624 size = length; 625 data = (uint8_t *)contents; 626 } 627 628 fw_cfg_add_i32(fw_cfg, size_key, size); 629 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 630 } 631 632 static void fw_cfg_add_kernel_info(FWCfgState *fw_cfg) 633 { 634 /* 635 * Expose the kernel, the command line, and the initrd in fw_cfg. 636 * We don't process them here at all, it's all left to the 637 * firmware. 638 */ 639 load_image_to_fw_cfg(fw_cfg, 640 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 641 loaderparams.kernel_filename, 642 false); 643 644 if (loaderparams.initrd_filename) { 645 load_image_to_fw_cfg(fw_cfg, 646 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 647 loaderparams.initrd_filename, false); 648 } 649 650 if (loaderparams.kernel_cmdline) { 651 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 652 strlen(loaderparams.kernel_cmdline) + 1); 653 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 654 loaderparams.kernel_cmdline); 655 } 656 } 657 658 static void loongarch_firmware_boot(LoongArchMachineState *lams) 659 { 660 fw_cfg_add_kernel_info(lams->fw_cfg); 661 } 662 663 static void loongarch_direct_kernel_boot(LoongArchMachineState *lams) 664 { 665 MachineState *machine = MACHINE(lams); 666 int64_t kernel_addr = 0; 667 LoongArchCPU *lacpu; 668 int i; 669 670 kernel_addr = load_kernel_info(); 671 if (!machine->firmware) { 672 for (i = 0; i < machine->smp.cpus; i++) { 673 lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); 674 lacpu->env.load_elf = true; 675 lacpu->env.elf_address = kernel_addr; 676 } 677 } 678 } 679 680 static void loongarch_init(MachineState *machine) 681 { 682 LoongArchCPU *lacpu; 683 const char *cpu_model = machine->cpu_type; 684 ram_addr_t offset = 0; 685 ram_addr_t ram_size = machine->ram_size; 686 uint64_t highram_size = 0; 687 MemoryRegion *address_space_mem = get_system_memory(); 688 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 689 int i; 690 691 if (!cpu_model) { 692 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 693 } 694 695 if (!strstr(cpu_model, "la464")) { 696 error_report("LoongArch/TCG needs cpu type la464"); 697 exit(1); 698 } 699 700 if (ram_size < 1 * GiB) { 701 error_report("ram_size must be greater than 1G."); 702 exit(1); 703 } 704 create_fdt(lams); 705 /* Init CPUs */ 706 for (i = 0; i < machine->smp.cpus; i++) { 707 cpu_create(machine->cpu_type); 708 } 709 fdt_add_cpu_nodes(lams); 710 /* Add memory region */ 711 memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram", 712 machine->ram, 0, 256 * MiB); 713 memory_region_add_subregion(address_space_mem, offset, &lams->lowmem); 714 offset += 256 * MiB; 715 memmap_add_entry(0, 256 * MiB, 1); 716 highram_size = ram_size - 256 * MiB; 717 memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem", 718 machine->ram, offset, highram_size); 719 memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem); 720 memmap_add_entry(0x90000000, highram_size, 1); 721 /* Add isa io region */ 722 memory_region_init_alias(&lams->isa_io, NULL, "isa-io", 723 get_system_io(), 0, VIRT_ISA_IO_SIZE); 724 memory_region_add_subregion(address_space_mem, VIRT_ISA_IO_BASE, 725 &lams->isa_io); 726 /* load the BIOS image. */ 727 loongarch_firmware_init(lams); 728 729 /* fw_cfg init */ 730 lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine); 731 rom_set_fw(lams->fw_cfg); 732 if (lams->fw_cfg != NULL) { 733 fw_cfg_add_file(lams->fw_cfg, "etc/memmap", 734 memmap_table, 735 sizeof(struct memmap_entry) * (memmap_entries)); 736 } 737 fdt_add_fw_cfg_node(lams); 738 loaderparams.ram_size = ram_size; 739 loaderparams.kernel_filename = machine->kernel_filename; 740 loaderparams.kernel_cmdline = machine->kernel_cmdline; 741 loaderparams.initrd_filename = machine->initrd_filename; 742 /* load the kernel. */ 743 if (loaderparams.kernel_filename) { 744 if (lams->bios_loaded) { 745 loongarch_firmware_boot(lams); 746 } else { 747 loongarch_direct_kernel_boot(lams); 748 } 749 } 750 /* register reset function */ 751 for (i = 0; i < machine->smp.cpus; i++) { 752 lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); 753 qemu_register_reset(reset_load_elf, lacpu); 754 } 755 /* Initialize the IO interrupt subsystem */ 756 loongarch_irq_init(lams); 757 fdt_add_irqchip_node(lams); 758 platform_bus_add_all_fdt_nodes(machine->fdt, "/intc", 759 VIRT_PLATFORM_BUS_BASEADDRESS, 760 VIRT_PLATFORM_BUS_SIZE, 761 VIRT_PLATFORM_BUS_IRQ); 762 lams->machine_done.notify = virt_machine_done; 763 qemu_add_machine_init_done_notifier(&lams->machine_done); 764 fdt_add_pcie_node(lams); 765 766 /* load fdt */ 767 MemoryRegion *fdt_rom = g_new(MemoryRegion, 1); 768 memory_region_init_rom(fdt_rom, NULL, "fdt", VIRT_FDT_SIZE, &error_fatal); 769 memory_region_add_subregion(get_system_memory(), VIRT_FDT_BASE, fdt_rom); 770 rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, VIRT_FDT_BASE); 771 } 772 773 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) 774 { 775 if (lams->acpi == ON_OFF_AUTO_OFF) { 776 return false; 777 } 778 return true; 779 } 780 781 static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, 782 void *opaque, Error **errp) 783 { 784 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 785 OnOffAuto acpi = lams->acpi; 786 787 visit_type_OnOffAuto(v, name, &acpi, errp); 788 } 789 790 static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, 791 void *opaque, Error **errp) 792 { 793 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 794 795 visit_type_OnOffAuto(v, name, &lams->acpi, errp); 796 } 797 798 static void loongarch_machine_initfn(Object *obj) 799 { 800 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 801 802 lams->acpi = ON_OFF_AUTO_AUTO; 803 lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 804 lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 805 } 806 807 static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev, 808 DeviceState *dev, Error **errp) 809 { 810 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 811 MachineClass *mc = MACHINE_GET_CLASS(lams); 812 813 if (device_is_dynamic_sysbus(mc, dev)) { 814 if (lams->platform_bus_dev) { 815 platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev), 816 SYS_BUS_DEVICE(dev)); 817 } 818 } 819 } 820 821 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 822 DeviceState *dev) 823 { 824 MachineClass *mc = MACHINE_GET_CLASS(machine); 825 826 if (device_is_dynamic_sysbus(mc, dev)) { 827 return HOTPLUG_HANDLER(machine); 828 } 829 return NULL; 830 } 831 832 static void loongarch_class_init(ObjectClass *oc, void *data) 833 { 834 MachineClass *mc = MACHINE_CLASS(oc); 835 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 836 837 mc->desc = "Loongson-3A5000 LS7A1000 machine"; 838 mc->init = loongarch_init; 839 mc->default_ram_size = 1 * GiB; 840 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 841 mc->default_ram_id = "loongarch.ram"; 842 mc->max_cpus = LOONGARCH_MAX_VCPUS; 843 mc->is_default = 1; 844 mc->default_kernel_irqchip_split = false; 845 mc->block_default_type = IF_VIRTIO; 846 mc->default_boot_order = "c"; 847 mc->no_cdrom = 1; 848 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 849 hc->plug = loongarch_machine_device_plug_cb; 850 851 object_class_property_add(oc, "acpi", "OnOffAuto", 852 loongarch_get_acpi, loongarch_set_acpi, 853 NULL, NULL); 854 object_class_property_set_description(oc, "acpi", 855 "Enable ACPI"); 856 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 857 } 858 859 static const TypeInfo loongarch_machine_types[] = { 860 { 861 .name = TYPE_LOONGARCH_MACHINE, 862 .parent = TYPE_MACHINE, 863 .instance_size = sizeof(LoongArchMachineState), 864 .class_init = loongarch_class_init, 865 .instance_init = loongarch_machine_initfn, 866 .interfaces = (InterfaceInfo[]) { 867 { TYPE_HOTPLUG_HANDLER }, 868 { } 869 }, 870 } 871 }; 872 873 DEFINE_TYPES(loongarch_machine_types) 874