1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/sysemu.h" 14 #include "sysemu/qtest.h" 15 #include "sysemu/runstate.h" 16 #include "sysemu/reset.h" 17 #include "sysemu/rtc.h" 18 #include "hw/loongarch/virt.h" 19 #include "exec/address-spaces.h" 20 #include "hw/irq.h" 21 #include "net/net.h" 22 #include "hw/loader.h" 23 #include "elf.h" 24 #include "hw/intc/loongarch_ipi.h" 25 #include "hw/intc/loongarch_extioi.h" 26 #include "hw/intc/loongarch_pch_pic.h" 27 #include "hw/intc/loongarch_pch_msi.h" 28 #include "hw/pci-host/ls7a.h" 29 #include "hw/pci-host/gpex.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/loongarch/fw_cfg.h" 32 #include "target/loongarch/cpu.h" 33 #include "hw/firmware/smbios.h" 34 #include "hw/acpi/aml-build.h" 35 #include "qapi/qapi-visit-common.h" 36 #include "hw/acpi/generic_event_device.h" 37 #include "hw/mem/nvdimm.h" 38 #include "sysemu/device_tree.h" 39 #include <libfdt.h> 40 41 static void create_fdt(LoongArchMachineState *lams) 42 { 43 MachineState *ms = MACHINE(lams); 44 45 ms->fdt = create_device_tree(&lams->fdt_size); 46 if (!ms->fdt) { 47 error_report("create_device_tree() failed"); 48 exit(1); 49 } 50 51 /* Header */ 52 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 53 "linux,dummy-loongson3"); 54 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 55 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 56 } 57 58 static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) 59 { 60 int num; 61 const MachineState *ms = MACHINE(lams); 62 int smp_cpus = ms->smp.cpus; 63 64 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 65 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 66 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 67 68 /* cpu nodes */ 69 for (num = smp_cpus - 1; num >= 0; num--) { 70 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 71 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 72 73 qemu_fdt_add_subnode(ms->fdt, nodename); 74 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 75 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 76 cpu->dtb_compatible); 77 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 78 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 79 qemu_fdt_alloc_phandle(ms->fdt)); 80 g_free(nodename); 81 } 82 83 /*cpu map */ 84 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 85 86 for (num = smp_cpus - 1; num >= 0; num--) { 87 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 88 char *map_path; 89 90 if (ms->smp.threads > 1) { 91 map_path = g_strdup_printf( 92 "/cpus/cpu-map/socket%d/core%d/thread%d", 93 num / (ms->smp.cores * ms->smp.threads), 94 (num / ms->smp.threads) % ms->smp.cores, 95 num % ms->smp.threads); 96 } else { 97 map_path = g_strdup_printf( 98 "/cpus/cpu-map/socket%d/core%d", 99 num / ms->smp.cores, 100 num % ms->smp.cores); 101 } 102 qemu_fdt_add_path(ms->fdt, map_path); 103 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 104 105 g_free(map_path); 106 g_free(cpu_path); 107 } 108 } 109 110 static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) 111 { 112 char *nodename; 113 hwaddr base = VIRT_FWCFG_BASE; 114 const MachineState *ms = MACHINE(lams); 115 116 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 117 qemu_fdt_add_subnode(ms->fdt, nodename); 118 qemu_fdt_setprop_string(ms->fdt, nodename, 119 "compatible", "qemu,fw-cfg-mmio"); 120 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 121 2, base, 2, 0x18); 122 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 123 g_free(nodename); 124 } 125 126 static void fdt_add_pcie_node(const LoongArchMachineState *lams) 127 { 128 char *nodename; 129 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 130 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 131 hwaddr base_pio = VIRT_PCI_IO_BASE; 132 hwaddr size_pio = VIRT_PCI_IO_SIZE; 133 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 134 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 135 hwaddr base = base_pcie; 136 137 const MachineState *ms = MACHINE(lams); 138 139 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 140 qemu_fdt_add_subnode(ms->fdt, nodename); 141 qemu_fdt_setprop_string(ms->fdt, nodename, 142 "compatible", "pci-host-ecam-generic"); 143 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 144 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 145 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 146 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 147 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 148 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 149 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 150 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 151 2, base_pcie, 2, size_pcie); 152 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 153 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 154 2, base_pio, 2, size_pio, 155 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 156 2, base_mmio, 2, size_mmio); 157 g_free(nodename); 158 qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size); 159 } 160 161 static void fdt_add_irqchip_node(LoongArchMachineState *lams) 162 { 163 MachineState *ms = MACHINE(lams); 164 char *nodename; 165 uint32_t irqchip_phandle; 166 167 irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt); 168 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle); 169 170 nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE); 171 qemu_fdt_add_subnode(ms->fdt, nodename); 172 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 173 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 174 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 175 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 176 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 177 178 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 179 "loongarch,ls7a"); 180 181 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 182 2, VIRT_IOAPIC_REG_BASE, 183 2, PCH_PIC_ROUTE_ENTRY_OFFSET); 184 185 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle); 186 g_free(nodename); 187 } 188 189 #define PM_BASE 0x10080000 190 #define PM_SIZE 0x100 191 #define PM_CTRL 0x10 192 193 static void virt_build_smbios(LoongArchMachineState *lams) 194 { 195 MachineState *ms = MACHINE(lams); 196 MachineClass *mc = MACHINE_GET_CLASS(lams); 197 uint8_t *smbios_tables, *smbios_anchor; 198 size_t smbios_tables_len, smbios_anchor_len; 199 const char *product = "QEMU Virtual Machine"; 200 201 if (!lams->fw_cfg) { 202 return; 203 } 204 205 smbios_set_defaults("QEMU", product, mc->name, false, 206 true, SMBIOS_ENTRY_POINT_TYPE_64); 207 208 smbios_get_tables(ms, NULL, 0, &smbios_tables, &smbios_tables_len, 209 &smbios_anchor, &smbios_anchor_len, &error_fatal); 210 211 if (smbios_anchor) { 212 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", 213 smbios_tables, smbios_tables_len); 214 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", 215 smbios_anchor, smbios_anchor_len); 216 } 217 } 218 219 static void virt_machine_done(Notifier *notifier, void *data) 220 { 221 LoongArchMachineState *lams = container_of(notifier, 222 LoongArchMachineState, machine_done); 223 virt_build_smbios(lams); 224 loongarch_acpi_setup(lams); 225 } 226 227 struct memmap_entry { 228 uint64_t address; 229 uint64_t length; 230 uint32_t type; 231 uint32_t reserved; 232 }; 233 234 static struct memmap_entry *memmap_table; 235 static unsigned memmap_entries; 236 237 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 238 { 239 /* Ensure there are no duplicate entries. */ 240 for (unsigned i = 0; i < memmap_entries; i++) { 241 assert(memmap_table[i].address != address); 242 } 243 244 memmap_table = g_renew(struct memmap_entry, memmap_table, 245 memmap_entries + 1); 246 memmap_table[memmap_entries].address = cpu_to_le64(address); 247 memmap_table[memmap_entries].length = cpu_to_le64(length); 248 memmap_table[memmap_entries].type = cpu_to_le32(type); 249 memmap_table[memmap_entries].reserved = 0; 250 memmap_entries++; 251 } 252 253 /* 254 * This is a placeholder for missing ACPI, 255 * and will eventually be replaced. 256 */ 257 static uint64_t loongarch_virt_pm_read(void *opaque, hwaddr addr, unsigned size) 258 { 259 return 0; 260 } 261 262 static void loongarch_virt_pm_write(void *opaque, hwaddr addr, 263 uint64_t val, unsigned size) 264 { 265 if (addr != PM_CTRL) { 266 return; 267 } 268 269 switch (val) { 270 case 0x00: 271 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 272 return; 273 case 0xff: 274 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 275 return; 276 default: 277 return; 278 } 279 } 280 281 static const MemoryRegionOps loongarch_virt_pm_ops = { 282 .read = loongarch_virt_pm_read, 283 .write = loongarch_virt_pm_write, 284 .endianness = DEVICE_NATIVE_ENDIAN, 285 .valid = { 286 .min_access_size = 1, 287 .max_access_size = 1 288 } 289 }; 290 291 static struct _loaderparams { 292 uint64_t ram_size; 293 const char *kernel_filename; 294 const char *kernel_cmdline; 295 const char *initrd_filename; 296 } loaderparams; 297 298 static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr) 299 { 300 return addr & 0x1fffffffll; 301 } 302 303 static int64_t load_kernel_info(void) 304 { 305 uint64_t kernel_entry, kernel_low, kernel_high; 306 ssize_t kernel_size; 307 308 kernel_size = load_elf(loaderparams.kernel_filename, NULL, 309 cpu_loongarch_virt_to_phys, NULL, 310 &kernel_entry, &kernel_low, 311 &kernel_high, NULL, 0, 312 EM_LOONGARCH, 1, 0); 313 314 if (kernel_size < 0) { 315 error_report("could not load kernel '%s': %s", 316 loaderparams.kernel_filename, 317 load_elf_strerror(kernel_size)); 318 exit(1); 319 } 320 return kernel_entry; 321 } 322 323 static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams) 324 { 325 DeviceState *dev; 326 MachineState *ms = MACHINE(lams); 327 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 328 329 if (ms->ram_slots) { 330 event |= ACPI_GED_MEM_HOTPLUG_EVT; 331 } 332 dev = qdev_new(TYPE_ACPI_GED); 333 qdev_prop_set_uint32(dev, "ged-event", event); 334 335 /* ged event */ 336 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 337 /* memory hotplug */ 338 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 339 /* ged regs used for reset and power down */ 340 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 341 342 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 343 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - PCH_PIC_IRQ_OFFSET)); 344 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 345 return dev; 346 } 347 348 static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams) 349 { 350 DeviceState *gpex_dev; 351 SysBusDevice *d; 352 PCIBus *pci_bus; 353 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 354 MemoryRegion *mmio_alias, *mmio_reg, *pm_mem; 355 int i; 356 357 gpex_dev = qdev_new(TYPE_GPEX_HOST); 358 d = SYS_BUS_DEVICE(gpex_dev); 359 sysbus_realize_and_unref(d, &error_fatal); 360 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 361 362 /* Map only part size_ecam bytes of ECAM space */ 363 ecam_alias = g_new0(MemoryRegion, 1); 364 ecam_reg = sysbus_mmio_get_region(d, 0); 365 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 366 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 367 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 368 ecam_alias); 369 370 /* Map PCI mem space */ 371 mmio_alias = g_new0(MemoryRegion, 1); 372 mmio_reg = sysbus_mmio_get_region(d, 1); 373 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 374 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 375 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 376 mmio_alias); 377 378 /* Map PCI IO port space. */ 379 pio_alias = g_new0(MemoryRegion, 1); 380 pio_reg = sysbus_mmio_get_region(d, 2); 381 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 382 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 383 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 384 pio_alias); 385 386 for (i = 0; i < GPEX_NUM_IRQS; i++) { 387 sysbus_connect_irq(d, i, 388 qdev_get_gpio_in(pch_pic, 16 + i)); 389 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 390 } 391 392 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 393 qdev_get_gpio_in(pch_pic, 394 VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET), 395 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 396 397 /* Network init */ 398 for (i = 0; i < nb_nics; i++) { 399 NICInfo *nd = &nd_table[i]; 400 401 if (!nd->model) { 402 nd->model = g_strdup("virtio"); 403 } 404 405 pci_nic_init_nofail(nd, pci_bus, nd->model, NULL); 406 } 407 408 /* 409 * There are some invalid guest memory access. 410 * Create some unimplemented devices to emulate this. 411 */ 412 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 413 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 414 qdev_get_gpio_in(pch_pic, 415 VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET)); 416 417 pm_mem = g_new(MemoryRegion, 1); 418 memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops, 419 NULL, "loongarch_virt_pm", PM_SIZE); 420 memory_region_add_subregion(get_system_memory(), PM_BASE, pm_mem); 421 /* acpi ged */ 422 lams->acpi_ged = create_acpi_ged(pch_pic, lams); 423 } 424 425 static void loongarch_irq_init(LoongArchMachineState *lams) 426 { 427 MachineState *ms = MACHINE(lams); 428 DeviceState *pch_pic, *pch_msi, *cpudev; 429 DeviceState *ipi, *extioi; 430 SysBusDevice *d; 431 LoongArchCPU *lacpu; 432 CPULoongArchState *env; 433 CPUState *cpu_state; 434 int cpu, pin, i; 435 436 ipi = qdev_new(TYPE_LOONGARCH_IPI); 437 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 438 439 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 440 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 441 442 /* 443 * The connection of interrupts: 444 * +-----+ +---------+ +-------+ 445 * | IPI |--> | CPUINTC | <-- | Timer | 446 * +-----+ +---------+ +-------+ 447 * ^ 448 * | 449 * +---------+ 450 * | EIOINTC | 451 * +---------+ 452 * ^ ^ 453 * | | 454 * +---------+ +---------+ 455 * | PCH-PIC | | PCH-MSI | 456 * +---------+ +---------+ 457 * ^ ^ ^ 458 * | | | 459 * +--------+ +---------+ +---------+ 460 * | UARTs | | Devices | | Devices | 461 * +--------+ +---------+ +---------+ 462 */ 463 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 464 cpu_state = qemu_get_cpu(cpu); 465 cpudev = DEVICE(cpu_state); 466 lacpu = LOONGARCH_CPU(cpu_state); 467 env = &(lacpu->env); 468 469 /* connect ipi irq to cpu irq */ 470 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); 471 /* IPI iocsr memory region */ 472 memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX, 473 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 474 cpu * 2)); 475 memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR, 476 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 477 cpu * 2 + 1)); 478 /* extioi iocsr memory region */ 479 memory_region_add_subregion(&env->system_iocsr, APIC_BASE, 480 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 481 cpu)); 482 } 483 484 /* 485 * connect ext irq to the cpu irq 486 * cpu_pin[9:2] <= intc_pin[7:0] 487 */ 488 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 489 cpudev = DEVICE(qemu_get_cpu(cpu)); 490 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 491 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 492 qdev_get_gpio_in(cpudev, pin + 2)); 493 } 494 } 495 496 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 497 d = SYS_BUS_DEVICE(pch_pic); 498 sysbus_realize_and_unref(d, &error_fatal); 499 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 500 sysbus_mmio_get_region(d, 0)); 501 memory_region_add_subregion(get_system_memory(), 502 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 503 sysbus_mmio_get_region(d, 1)); 504 memory_region_add_subregion(get_system_memory(), 505 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 506 sysbus_mmio_get_region(d, 2)); 507 508 /* Connect 64 pch_pic irqs to extioi */ 509 for (int i = 0; i < PCH_PIC_IRQ_NUM; i++) { 510 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 511 } 512 513 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 514 qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START); 515 d = SYS_BUS_DEVICE(pch_msi); 516 sysbus_realize_and_unref(d, &error_fatal); 517 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 518 for (i = 0; i < PCH_MSI_IRQ_NUM; i++) { 519 /* Connect 192 pch_msi irqs to extioi */ 520 qdev_connect_gpio_out(DEVICE(d), i, 521 qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START)); 522 } 523 524 loongarch_devices_init(pch_pic, lams); 525 } 526 527 static void loongarch_firmware_init(LoongArchMachineState *lams) 528 { 529 char *filename = MACHINE(lams)->firmware; 530 char *bios_name = NULL; 531 int bios_size; 532 533 lams->bios_loaded = false; 534 if (filename) { 535 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 536 if (!bios_name) { 537 error_report("Could not find ROM image '%s'", filename); 538 exit(1); 539 } 540 541 bios_size = load_image_targphys(bios_name, VIRT_BIOS_BASE, VIRT_BIOS_SIZE); 542 if (bios_size < 0) { 543 error_report("Could not load ROM image '%s'", bios_name); 544 exit(1); 545 } 546 547 g_free(bios_name); 548 549 memory_region_init_ram(&lams->bios, NULL, "loongarch.bios", 550 VIRT_BIOS_SIZE, &error_fatal); 551 memory_region_set_readonly(&lams->bios, true); 552 memory_region_add_subregion(get_system_memory(), VIRT_BIOS_BASE, &lams->bios); 553 lams->bios_loaded = true; 554 } 555 556 } 557 558 static void reset_load_elf(void *opaque) 559 { 560 LoongArchCPU *cpu = opaque; 561 CPULoongArchState *env = &cpu->env; 562 563 cpu_reset(CPU(cpu)); 564 if (env->load_elf) { 565 cpu_set_pc(CPU(cpu), env->elf_address); 566 } 567 } 568 569 /* Load an image file into an fw_cfg entry identified by key. */ 570 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, 571 uint16_t data_key, const char *image_name, 572 bool try_decompress) 573 { 574 size_t size = -1; 575 uint8_t *data; 576 577 if (image_name == NULL) { 578 return; 579 } 580 581 if (try_decompress) { 582 size = load_image_gzipped_buffer(image_name, 583 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); 584 } 585 586 if (size == (size_t)-1) { 587 gchar *contents; 588 gsize length; 589 590 if (!g_file_get_contents(image_name, &contents, &length, NULL)) { 591 error_report("failed to load \"%s\"", image_name); 592 exit(1); 593 } 594 size = length; 595 data = (uint8_t *)contents; 596 } 597 598 fw_cfg_add_i32(fw_cfg, size_key, size); 599 fw_cfg_add_bytes(fw_cfg, data_key, data, size); 600 } 601 602 static void fw_cfg_add_kernel_info(FWCfgState *fw_cfg) 603 { 604 /* 605 * Expose the kernel, the command line, and the initrd in fw_cfg. 606 * We don't process them here at all, it's all left to the 607 * firmware. 608 */ 609 load_image_to_fw_cfg(fw_cfg, 610 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 611 loaderparams.kernel_filename, 612 false); 613 614 if (loaderparams.initrd_filename) { 615 load_image_to_fw_cfg(fw_cfg, 616 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 617 loaderparams.initrd_filename, false); 618 } 619 620 if (loaderparams.kernel_cmdline) { 621 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 622 strlen(loaderparams.kernel_cmdline) + 1); 623 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 624 loaderparams.kernel_cmdline); 625 } 626 } 627 628 static void loongarch_firmware_boot(LoongArchMachineState *lams) 629 { 630 fw_cfg_add_kernel_info(lams->fw_cfg); 631 } 632 633 static void loongarch_direct_kernel_boot(LoongArchMachineState *lams) 634 { 635 MachineState *machine = MACHINE(lams); 636 int64_t kernel_addr = 0; 637 LoongArchCPU *lacpu; 638 int i; 639 640 kernel_addr = load_kernel_info(); 641 if (!machine->firmware) { 642 for (i = 0; i < machine->smp.cpus; i++) { 643 lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); 644 lacpu->env.load_elf = true; 645 lacpu->env.elf_address = kernel_addr; 646 } 647 } 648 } 649 650 static void loongarch_init(MachineState *machine) 651 { 652 LoongArchCPU *lacpu; 653 const char *cpu_model = machine->cpu_type; 654 ram_addr_t offset = 0; 655 ram_addr_t ram_size = machine->ram_size; 656 uint64_t highram_size = 0; 657 MemoryRegion *address_space_mem = get_system_memory(); 658 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 659 int i; 660 661 if (!cpu_model) { 662 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 663 } 664 665 if (!strstr(cpu_model, "la464")) { 666 error_report("LoongArch/TCG needs cpu type la464"); 667 exit(1); 668 } 669 670 if (ram_size < 1 * GiB) { 671 error_report("ram_size must be greater than 1G."); 672 exit(1); 673 } 674 create_fdt(lams); 675 /* Init CPUs */ 676 for (i = 0; i < machine->smp.cpus; i++) { 677 cpu_create(machine->cpu_type); 678 } 679 fdt_add_cpu_nodes(lams); 680 /* Add memory region */ 681 memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram", 682 machine->ram, 0, 256 * MiB); 683 memory_region_add_subregion(address_space_mem, offset, &lams->lowmem); 684 offset += 256 * MiB; 685 memmap_add_entry(0, 256 * MiB, 1); 686 highram_size = ram_size - 256 * MiB; 687 memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem", 688 machine->ram, offset, highram_size); 689 memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem); 690 memmap_add_entry(0x90000000, highram_size, 1); 691 /* Add isa io region */ 692 memory_region_init_alias(&lams->isa_io, NULL, "isa-io", 693 get_system_io(), 0, VIRT_ISA_IO_SIZE); 694 memory_region_add_subregion(address_space_mem, VIRT_ISA_IO_BASE, 695 &lams->isa_io); 696 /* load the BIOS image. */ 697 loongarch_firmware_init(lams); 698 699 /* fw_cfg init */ 700 lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine); 701 rom_set_fw(lams->fw_cfg); 702 if (lams->fw_cfg != NULL) { 703 fw_cfg_add_file(lams->fw_cfg, "etc/memmap", 704 memmap_table, 705 sizeof(struct memmap_entry) * (memmap_entries)); 706 } 707 fdt_add_fw_cfg_node(lams); 708 loaderparams.ram_size = ram_size; 709 loaderparams.kernel_filename = machine->kernel_filename; 710 loaderparams.kernel_cmdline = machine->kernel_cmdline; 711 loaderparams.initrd_filename = machine->initrd_filename; 712 /* load the kernel. */ 713 if (loaderparams.kernel_filename) { 714 if (lams->bios_loaded) { 715 loongarch_firmware_boot(lams); 716 } else { 717 loongarch_direct_kernel_boot(lams); 718 } 719 } 720 /* register reset function */ 721 for (i = 0; i < machine->smp.cpus; i++) { 722 lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); 723 qemu_register_reset(reset_load_elf, lacpu); 724 } 725 /* Initialize the IO interrupt subsystem */ 726 loongarch_irq_init(lams); 727 fdt_add_irqchip_node(lams); 728 lams->machine_done.notify = virt_machine_done; 729 qemu_add_machine_init_done_notifier(&lams->machine_done); 730 fdt_add_pcie_node(lams); 731 732 /* load fdt */ 733 MemoryRegion *fdt_rom = g_new(MemoryRegion, 1); 734 memory_region_init_rom(fdt_rom, NULL, "fdt", VIRT_FDT_SIZE, &error_fatal); 735 memory_region_add_subregion(get_system_memory(), VIRT_FDT_BASE, fdt_rom); 736 rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, VIRT_FDT_BASE); 737 } 738 739 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) 740 { 741 if (lams->acpi == ON_OFF_AUTO_OFF) { 742 return false; 743 } 744 return true; 745 } 746 747 static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, 748 void *opaque, Error **errp) 749 { 750 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 751 OnOffAuto acpi = lams->acpi; 752 753 visit_type_OnOffAuto(v, name, &acpi, errp); 754 } 755 756 static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, 757 void *opaque, Error **errp) 758 { 759 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 760 761 visit_type_OnOffAuto(v, name, &lams->acpi, errp); 762 } 763 764 static void loongarch_machine_initfn(Object *obj) 765 { 766 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 767 768 lams->acpi = ON_OFF_AUTO_AUTO; 769 lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 770 lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 771 } 772 773 static void loongarch_class_init(ObjectClass *oc, void *data) 774 { 775 MachineClass *mc = MACHINE_CLASS(oc); 776 777 mc->desc = "Loongson-3A5000 LS7A1000 machine"; 778 mc->init = loongarch_init; 779 mc->default_ram_size = 1 * GiB; 780 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 781 mc->default_ram_id = "loongarch.ram"; 782 mc->max_cpus = LOONGARCH_MAX_VCPUS; 783 mc->is_default = 1; 784 mc->default_kernel_irqchip_split = false; 785 mc->block_default_type = IF_VIRTIO; 786 mc->default_boot_order = "c"; 787 mc->no_cdrom = 1; 788 789 object_class_property_add(oc, "acpi", "OnOffAuto", 790 loongarch_get_acpi, loongarch_set_acpi, 791 NULL, NULL); 792 object_class_property_set_description(oc, "acpi", 793 "Enable ACPI"); 794 } 795 796 static const TypeInfo loongarch_machine_types[] = { 797 { 798 .name = TYPE_LOONGARCH_MACHINE, 799 .parent = TYPE_MACHINE, 800 .instance_size = sizeof(LoongArchMachineState), 801 .class_init = loongarch_class_init, 802 .instance_init = loongarch_machine_initfn, 803 } 804 }; 805 806 DEFINE_TYPES(loongarch_machine_types) 807