1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/kvm.h" 14 #include "sysemu/sysemu.h" 15 #include "sysemu/qtest.h" 16 #include "sysemu/runstate.h" 17 #include "sysemu/reset.h" 18 #include "sysemu/rtc.h" 19 #include "hw/loongarch/virt.h" 20 #include "exec/address-spaces.h" 21 #include "hw/irq.h" 22 #include "net/net.h" 23 #include "hw/loader.h" 24 #include "elf.h" 25 #include "hw/intc/loongson_ipi.h" 26 #include "hw/intc/loongarch_extioi.h" 27 #include "hw/intc/loongarch_pch_pic.h" 28 #include "hw/intc/loongarch_pch_msi.h" 29 #include "hw/pci-host/ls7a.h" 30 #include "hw/pci-host/gpex.h" 31 #include "hw/misc/unimp.h" 32 #include "hw/loongarch/fw_cfg.h" 33 #include "target/loongarch/cpu.h" 34 #include "hw/firmware/smbios.h" 35 #include "hw/acpi/aml-build.h" 36 #include "qapi/qapi-visit-common.h" 37 #include "hw/acpi/generic_event_device.h" 38 #include "hw/mem/nvdimm.h" 39 #include "sysemu/device_tree.h" 40 #include <libfdt.h> 41 #include "hw/core/sysbus-fdt.h" 42 #include "hw/platform-bus.h" 43 #include "hw/display/ramfb.h" 44 #include "hw/mem/pc-dimm.h" 45 #include "sysemu/tpm.h" 46 #include "sysemu/block-backend.h" 47 #include "hw/block/flash.h" 48 #include "hw/virtio/virtio-iommu.h" 49 #include "qemu/error-report.h" 50 51 static PFlashCFI01 *virt_flash_create1(LoongArchVirtMachineState *lvms, 52 const char *name, 53 const char *alias_prop_name) 54 { 55 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 56 57 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 58 qdev_prop_set_uint8(dev, "width", 4); 59 qdev_prop_set_uint8(dev, "device-width", 2); 60 qdev_prop_set_bit(dev, "big-endian", false); 61 qdev_prop_set_uint16(dev, "id0", 0x89); 62 qdev_prop_set_uint16(dev, "id1", 0x18); 63 qdev_prop_set_uint16(dev, "id2", 0x00); 64 qdev_prop_set_uint16(dev, "id3", 0x00); 65 qdev_prop_set_string(dev, "name", name); 66 object_property_add_child(OBJECT(lvms), name, OBJECT(dev)); 67 object_property_add_alias(OBJECT(lvms), alias_prop_name, 68 OBJECT(dev), "drive"); 69 return PFLASH_CFI01(dev); 70 } 71 72 static void virt_flash_create(LoongArchVirtMachineState *lvms) 73 { 74 lvms->flash[0] = virt_flash_create1(lvms, "virt.flash0", "pflash0"); 75 lvms->flash[1] = virt_flash_create1(lvms, "virt.flash1", "pflash1"); 76 } 77 78 static void virt_flash_map1(PFlashCFI01 *flash, 79 hwaddr base, hwaddr size, 80 MemoryRegion *sysmem) 81 { 82 DeviceState *dev = DEVICE(flash); 83 BlockBackend *blk; 84 hwaddr real_size = size; 85 86 blk = pflash_cfi01_get_blk(flash); 87 if (blk) { 88 real_size = blk_getlength(blk); 89 assert(real_size && real_size <= size); 90 } 91 92 assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE)); 93 assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 94 95 qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE); 96 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 97 memory_region_add_subregion(sysmem, base, 98 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 99 } 100 101 static void virt_flash_map(LoongArchVirtMachineState *lvms, 102 MemoryRegion *sysmem) 103 { 104 PFlashCFI01 *flash0 = lvms->flash[0]; 105 PFlashCFI01 *flash1 = lvms->flash[1]; 106 107 virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem); 108 virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem); 109 } 110 111 static void fdt_add_cpuic_node(LoongArchVirtMachineState *lvms, 112 uint32_t *cpuintc_phandle) 113 { 114 MachineState *ms = MACHINE(lvms); 115 char *nodename; 116 117 *cpuintc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 118 nodename = g_strdup_printf("/cpuic"); 119 qemu_fdt_add_subnode(ms->fdt, nodename); 120 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *cpuintc_phandle); 121 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 122 "loongson,cpu-interrupt-controller"); 123 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 124 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 125 g_free(nodename); 126 } 127 128 static void fdt_add_eiointc_node(LoongArchVirtMachineState *lvms, 129 uint32_t *cpuintc_phandle, 130 uint32_t *eiointc_phandle) 131 { 132 MachineState *ms = MACHINE(lvms); 133 char *nodename; 134 hwaddr extioi_base = APIC_BASE; 135 hwaddr extioi_size = EXTIOI_SIZE; 136 137 *eiointc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 138 nodename = g_strdup_printf("/eiointc@%" PRIx64, extioi_base); 139 qemu_fdt_add_subnode(ms->fdt, nodename); 140 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *eiointc_phandle); 141 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 142 "loongson,ls2k2000-eiointc"); 143 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 144 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 145 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 146 *cpuintc_phandle); 147 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", 3); 148 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, 149 extioi_base, 0x0, extioi_size); 150 g_free(nodename); 151 } 152 153 static void fdt_add_pch_pic_node(LoongArchVirtMachineState *lvms, 154 uint32_t *eiointc_phandle, 155 uint32_t *pch_pic_phandle) 156 { 157 MachineState *ms = MACHINE(lvms); 158 char *nodename; 159 hwaddr pch_pic_base = VIRT_PCH_REG_BASE; 160 hwaddr pch_pic_size = VIRT_PCH_REG_SIZE; 161 162 *pch_pic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 163 nodename = g_strdup_printf("/platic@%" PRIx64, pch_pic_base); 164 qemu_fdt_add_subnode(ms->fdt, nodename); 165 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_pic_phandle); 166 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 167 "loongson,pch-pic-1.0"); 168 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, 169 pch_pic_base, 0, pch_pic_size); 170 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 171 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 2); 172 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 173 *eiointc_phandle); 174 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,pic-base-vec", 0); 175 g_free(nodename); 176 } 177 178 static void fdt_add_pch_msi_node(LoongArchVirtMachineState *lvms, 179 uint32_t *eiointc_phandle, 180 uint32_t *pch_msi_phandle) 181 { 182 MachineState *ms = MACHINE(lvms); 183 char *nodename; 184 hwaddr pch_msi_base = VIRT_PCH_MSI_ADDR_LOW; 185 hwaddr pch_msi_size = VIRT_PCH_MSI_SIZE; 186 187 *pch_msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 188 nodename = g_strdup_printf("/msi@%" PRIx64, pch_msi_base); 189 qemu_fdt_add_subnode(ms->fdt, nodename); 190 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_msi_phandle); 191 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 192 "loongson,pch-msi-1.0"); 193 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 194 0, pch_msi_base, 195 0, pch_msi_size); 196 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 197 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 198 *eiointc_phandle); 199 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-base-vec", 200 VIRT_PCH_PIC_IRQ_NUM); 201 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-num-vecs", 202 EXTIOI_IRQS - VIRT_PCH_PIC_IRQ_NUM); 203 g_free(nodename); 204 } 205 206 static void fdt_add_flash_node(LoongArchVirtMachineState *lvms) 207 { 208 MachineState *ms = MACHINE(lvms); 209 char *nodename; 210 MemoryRegion *flash_mem; 211 212 hwaddr flash0_base; 213 hwaddr flash0_size; 214 215 hwaddr flash1_base; 216 hwaddr flash1_size; 217 218 flash_mem = pflash_cfi01_get_memory(lvms->flash[0]); 219 flash0_base = flash_mem->addr; 220 flash0_size = memory_region_size(flash_mem); 221 222 flash_mem = pflash_cfi01_get_memory(lvms->flash[1]); 223 flash1_base = flash_mem->addr; 224 flash1_size = memory_region_size(flash_mem); 225 226 nodename = g_strdup_printf("/flash@%" PRIx64, flash0_base); 227 qemu_fdt_add_subnode(ms->fdt, nodename); 228 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 229 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 230 2, flash0_base, 2, flash0_size, 231 2, flash1_base, 2, flash1_size); 232 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 233 g_free(nodename); 234 } 235 236 static void fdt_add_rtc_node(LoongArchVirtMachineState *lvms, 237 uint32_t *pch_pic_phandle) 238 { 239 char *nodename; 240 hwaddr base = VIRT_RTC_REG_BASE; 241 hwaddr size = VIRT_RTC_LEN; 242 MachineState *ms = MACHINE(lvms); 243 244 nodename = g_strdup_printf("/rtc@%" PRIx64, base); 245 qemu_fdt_add_subnode(ms->fdt, nodename); 246 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 247 "loongson,ls7a-rtc"); 248 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 249 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 250 VIRT_RTC_IRQ - VIRT_GSI_BASE , 0x4); 251 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 252 *pch_pic_phandle); 253 g_free(nodename); 254 } 255 256 static void fdt_add_uart_node(LoongArchVirtMachineState *lvms, 257 uint32_t *pch_pic_phandle) 258 { 259 char *nodename; 260 hwaddr base = VIRT_UART_BASE; 261 hwaddr size = VIRT_UART_SIZE; 262 MachineState *ms = MACHINE(lvms); 263 264 nodename = g_strdup_printf("/serial@%" PRIx64, base); 265 qemu_fdt_add_subnode(ms->fdt, nodename); 266 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); 267 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); 268 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); 269 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 270 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 271 VIRT_UART_IRQ - VIRT_GSI_BASE, 0x4); 272 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 273 *pch_pic_phandle); 274 g_free(nodename); 275 } 276 277 static void create_fdt(LoongArchVirtMachineState *lvms) 278 { 279 MachineState *ms = MACHINE(lvms); 280 281 ms->fdt = create_device_tree(&lvms->fdt_size); 282 if (!ms->fdt) { 283 error_report("create_device_tree() failed"); 284 exit(1); 285 } 286 287 /* Header */ 288 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 289 "linux,dummy-loongson3"); 290 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 291 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 292 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 293 } 294 295 static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms) 296 { 297 int num; 298 const MachineState *ms = MACHINE(lvms); 299 int smp_cpus = ms->smp.cpus; 300 301 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 302 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 303 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 304 305 /* cpu nodes */ 306 for (num = smp_cpus - 1; num >= 0; num--) { 307 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 308 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 309 CPUState *cs = CPU(cpu); 310 311 qemu_fdt_add_subnode(ms->fdt, nodename); 312 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 313 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 314 cpu->dtb_compatible); 315 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 316 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 317 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 318 } 319 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 320 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 321 qemu_fdt_alloc_phandle(ms->fdt)); 322 g_free(nodename); 323 } 324 325 /*cpu map */ 326 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 327 328 for (num = smp_cpus - 1; num >= 0; num--) { 329 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 330 char *map_path; 331 332 if (ms->smp.threads > 1) { 333 map_path = g_strdup_printf( 334 "/cpus/cpu-map/socket%d/core%d/thread%d", 335 num / (ms->smp.cores * ms->smp.threads), 336 (num / ms->smp.threads) % ms->smp.cores, 337 num % ms->smp.threads); 338 } else { 339 map_path = g_strdup_printf( 340 "/cpus/cpu-map/socket%d/core%d", 341 num / ms->smp.cores, 342 num % ms->smp.cores); 343 } 344 qemu_fdt_add_path(ms->fdt, map_path); 345 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 346 347 g_free(map_path); 348 g_free(cpu_path); 349 } 350 } 351 352 static void fdt_add_fw_cfg_node(const LoongArchVirtMachineState *lvms) 353 { 354 char *nodename; 355 hwaddr base = VIRT_FWCFG_BASE; 356 const MachineState *ms = MACHINE(lvms); 357 358 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 359 qemu_fdt_add_subnode(ms->fdt, nodename); 360 qemu_fdt_setprop_string(ms->fdt, nodename, 361 "compatible", "qemu,fw-cfg-mmio"); 362 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 363 2, base, 2, 0x18); 364 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 365 g_free(nodename); 366 } 367 368 static void fdt_add_pcie_irq_map_node(const LoongArchVirtMachineState *lvms, 369 char *nodename, 370 uint32_t *pch_pic_phandle) 371 { 372 int pin, dev; 373 uint32_t irq_map_stride = 0; 374 uint32_t full_irq_map[GPEX_NUM_IRQS *GPEX_NUM_IRQS * 10] = {}; 375 uint32_t *irq_map = full_irq_map; 376 const MachineState *ms = MACHINE(lvms); 377 378 /* This code creates a standard swizzle of interrupts such that 379 * each device's first interrupt is based on it's PCI_SLOT number. 380 * (See pci_swizzle_map_irq_fn()) 381 * 382 * We only need one entry per interrupt in the table (not one per 383 * possible slot) seeing the interrupt-map-mask will allow the table 384 * to wrap to any number of devices. 385 */ 386 387 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 388 int devfn = dev * 0x8; 389 390 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 391 int irq_nr = 16 + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 392 int i = 0; 393 394 /* Fill PCI address cells */ 395 irq_map[i] = cpu_to_be32(devfn << 8); 396 i += 3; 397 398 /* Fill PCI Interrupt cells */ 399 irq_map[i] = cpu_to_be32(pin + 1); 400 i += 1; 401 402 /* Fill interrupt controller phandle and cells */ 403 irq_map[i++] = cpu_to_be32(*pch_pic_phandle); 404 irq_map[i++] = cpu_to_be32(irq_nr); 405 406 if (!irq_map_stride) { 407 irq_map_stride = i; 408 } 409 irq_map += irq_map_stride; 410 } 411 } 412 413 414 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", full_irq_map, 415 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 416 irq_map_stride * sizeof(uint32_t)); 417 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 418 0x1800, 0, 0, 0x7); 419 } 420 421 static void fdt_add_pcie_node(const LoongArchVirtMachineState *lvms, 422 uint32_t *pch_pic_phandle, 423 uint32_t *pch_msi_phandle) 424 { 425 char *nodename; 426 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 427 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 428 hwaddr base_pio = VIRT_PCI_IO_BASE; 429 hwaddr size_pio = VIRT_PCI_IO_SIZE; 430 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 431 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 432 hwaddr base = base_pcie; 433 434 const MachineState *ms = MACHINE(lvms); 435 436 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 437 qemu_fdt_add_subnode(ms->fdt, nodename); 438 qemu_fdt_setprop_string(ms->fdt, nodename, 439 "compatible", "pci-host-ecam-generic"); 440 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 441 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 442 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 443 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 444 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 445 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 446 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 447 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 448 2, base_pcie, 2, size_pcie); 449 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 450 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 451 2, base_pio, 2, size_pio, 452 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 453 2, base_mmio, 2, size_mmio); 454 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 455 0, *pch_msi_phandle, 0, 0x10000); 456 457 fdt_add_pcie_irq_map_node(lvms, nodename, pch_pic_phandle); 458 459 g_free(nodename); 460 } 461 462 static void fdt_add_memory_node(MachineState *ms, 463 uint64_t base, uint64_t size, int node_id) 464 { 465 char *nodename = g_strdup_printf("/memory@%" PRIx64, base); 466 467 qemu_fdt_add_subnode(ms->fdt, nodename); 468 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", base >> 32, base, 469 size >> 32, size); 470 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 471 472 if (ms->numa_state && ms->numa_state->num_nodes) { 473 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); 474 } 475 476 g_free(nodename); 477 } 478 479 static void fdt_add_memory_nodes(MachineState *ms) 480 { 481 hwaddr base, size, ram_size, gap; 482 int i, nb_numa_nodes, nodes; 483 NodeInfo *numa_info; 484 485 ram_size = ms->ram_size; 486 base = VIRT_LOWMEM_BASE; 487 gap = VIRT_LOWMEM_SIZE; 488 nodes = nb_numa_nodes = ms->numa_state->num_nodes; 489 numa_info = ms->numa_state->nodes; 490 if (!nodes) { 491 nodes = 1; 492 } 493 494 for (i = 0; i < nodes; i++) { 495 if (nb_numa_nodes) { 496 size = numa_info[i].node_mem; 497 } else { 498 size = ram_size; 499 } 500 501 /* 502 * memory for the node splited into two part 503 * lowram: [base, +gap) 504 * highram: [VIRT_HIGHMEM_BASE, +(len - gap)) 505 */ 506 if (size >= gap) { 507 fdt_add_memory_node(ms, base, gap, i); 508 size -= gap; 509 base = VIRT_HIGHMEM_BASE; 510 gap = ram_size - VIRT_LOWMEM_SIZE; 511 } 512 513 if (size) { 514 fdt_add_memory_node(ms, base, size, i); 515 base += size; 516 gap -= size; 517 } 518 } 519 } 520 521 static void virt_build_smbios(LoongArchVirtMachineState *lvms) 522 { 523 MachineState *ms = MACHINE(lvms); 524 MachineClass *mc = MACHINE_GET_CLASS(lvms); 525 uint8_t *smbios_tables, *smbios_anchor; 526 size_t smbios_tables_len, smbios_anchor_len; 527 const char *product = "QEMU Virtual Machine"; 528 529 if (!lvms->fw_cfg) { 530 return; 531 } 532 533 smbios_set_defaults("QEMU", product, mc->name, true); 534 535 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 536 NULL, 0, 537 &smbios_tables, &smbios_tables_len, 538 &smbios_anchor, &smbios_anchor_len, &error_fatal); 539 540 if (smbios_anchor) { 541 fw_cfg_add_file(lvms->fw_cfg, "etc/smbios/smbios-tables", 542 smbios_tables, smbios_tables_len); 543 fw_cfg_add_file(lvms->fw_cfg, "etc/smbios/smbios-anchor", 544 smbios_anchor, smbios_anchor_len); 545 } 546 } 547 548 static void virt_done(Notifier *notifier, void *data) 549 { 550 LoongArchVirtMachineState *lvms = container_of(notifier, 551 LoongArchVirtMachineState, machine_done); 552 virt_build_smbios(lvms); 553 loongarch_acpi_setup(lvms); 554 } 555 556 static void virt_powerdown_req(Notifier *notifier, void *opaque) 557 { 558 LoongArchVirtMachineState *s; 559 560 s = container_of(notifier, LoongArchVirtMachineState, powerdown_notifier); 561 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 562 } 563 564 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 565 { 566 /* Ensure there are no duplicate entries. */ 567 for (unsigned i = 0; i < memmap_entries; i++) { 568 assert(memmap_table[i].address != address); 569 } 570 571 memmap_table = g_renew(struct memmap_entry, memmap_table, 572 memmap_entries + 1); 573 memmap_table[memmap_entries].address = cpu_to_le64(address); 574 memmap_table[memmap_entries].length = cpu_to_le64(length); 575 memmap_table[memmap_entries].type = cpu_to_le32(type); 576 memmap_table[memmap_entries].reserved = 0; 577 memmap_entries++; 578 } 579 580 static DeviceState *create_acpi_ged(DeviceState *pch_pic, 581 LoongArchVirtMachineState *lvms) 582 { 583 DeviceState *dev; 584 MachineState *ms = MACHINE(lvms); 585 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 586 587 if (ms->ram_slots) { 588 event |= ACPI_GED_MEM_HOTPLUG_EVT; 589 } 590 dev = qdev_new(TYPE_ACPI_GED); 591 qdev_prop_set_uint32(dev, "ged-event", event); 592 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 593 594 /* ged event */ 595 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 596 /* memory hotplug */ 597 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 598 /* ged regs used for reset and power down */ 599 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 600 601 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 602 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 603 return dev; 604 } 605 606 static DeviceState *create_platform_bus(DeviceState *pch_pic) 607 { 608 DeviceState *dev; 609 SysBusDevice *sysbus; 610 int i, irq; 611 MemoryRegion *sysmem = get_system_memory(); 612 613 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 614 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 615 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 616 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 617 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 618 619 sysbus = SYS_BUS_DEVICE(dev); 620 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 621 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 622 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 623 } 624 625 memory_region_add_subregion(sysmem, 626 VIRT_PLATFORM_BUS_BASEADDRESS, 627 sysbus_mmio_get_region(sysbus, 0)); 628 return dev; 629 } 630 631 static void virt_devices_init(DeviceState *pch_pic, 632 LoongArchVirtMachineState *lvms, 633 uint32_t *pch_pic_phandle, 634 uint32_t *pch_msi_phandle) 635 { 636 MachineClass *mc = MACHINE_GET_CLASS(lvms); 637 DeviceState *gpex_dev; 638 SysBusDevice *d; 639 PCIBus *pci_bus; 640 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 641 MemoryRegion *mmio_alias, *mmio_reg; 642 int i; 643 644 gpex_dev = qdev_new(TYPE_GPEX_HOST); 645 d = SYS_BUS_DEVICE(gpex_dev); 646 sysbus_realize_and_unref(d, &error_fatal); 647 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 648 lvms->pci_bus = pci_bus; 649 650 /* Map only part size_ecam bytes of ECAM space */ 651 ecam_alias = g_new0(MemoryRegion, 1); 652 ecam_reg = sysbus_mmio_get_region(d, 0); 653 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 654 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 655 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 656 ecam_alias); 657 658 /* Map PCI mem space */ 659 mmio_alias = g_new0(MemoryRegion, 1); 660 mmio_reg = sysbus_mmio_get_region(d, 1); 661 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 662 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 663 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 664 mmio_alias); 665 666 /* Map PCI IO port space. */ 667 pio_alias = g_new0(MemoryRegion, 1); 668 pio_reg = sysbus_mmio_get_region(d, 2); 669 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 670 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 671 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 672 pio_alias); 673 674 for (i = 0; i < GPEX_NUM_IRQS; i++) { 675 sysbus_connect_irq(d, i, 676 qdev_get_gpio_in(pch_pic, 16 + i)); 677 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 678 } 679 680 /* Add pcie node */ 681 fdt_add_pcie_node(lvms, pch_pic_phandle, pch_msi_phandle); 682 683 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 684 qdev_get_gpio_in(pch_pic, 685 VIRT_UART_IRQ - VIRT_GSI_BASE), 686 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 687 fdt_add_uart_node(lvms, pch_pic_phandle); 688 689 /* Network init */ 690 pci_init_nic_devices(pci_bus, mc->default_nic); 691 692 /* 693 * There are some invalid guest memory access. 694 * Create some unimplemented devices to emulate this. 695 */ 696 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 697 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 698 qdev_get_gpio_in(pch_pic, 699 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 700 fdt_add_rtc_node(lvms, pch_pic_phandle); 701 702 /* acpi ged */ 703 lvms->acpi_ged = create_acpi_ged(pch_pic, lvms); 704 /* platform bus */ 705 lvms->platform_bus_dev = create_platform_bus(pch_pic); 706 } 707 708 static void virt_irq_init(LoongArchVirtMachineState *lvms) 709 { 710 MachineState *ms = MACHINE(lvms); 711 DeviceState *pch_pic, *pch_msi, *cpudev; 712 DeviceState *ipi, *extioi; 713 SysBusDevice *d; 714 LoongArchCPU *lacpu; 715 CPULoongArchState *env; 716 CPUState *cpu_state; 717 int cpu, pin, i, start, num; 718 uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle; 719 720 /* 721 * Extended IRQ model. 722 * | 723 * +-----------+ +-------------|--------+ +-----------+ 724 * | IPI/Timer | --> | CPUINTC(0-3)|(4-255) | <-- | IPI/Timer | 725 * +-----------+ +-------------|--------+ +-----------+ 726 * ^ | 727 * | 728 * +---------+ 729 * | EIOINTC | 730 * +---------+ 731 * ^ ^ 732 * | | 733 * +---------+ +---------+ 734 * | PCH-PIC | | PCH-MSI | 735 * +---------+ +---------+ 736 * ^ ^ ^ 737 * | | | 738 * +--------+ +---------+ +---------+ 739 * | UARTs | | Devices | | Devices | 740 * +--------+ +---------+ +---------+ 741 * 742 * Virt extended IRQ model. 743 * 744 * +-----+ +---------------+ +-------+ 745 * | IPI |--> | CPUINTC(0-255)| <-- | Timer | 746 * +-----+ +---------------+ +-------+ 747 * ^ 748 * | 749 * +-----------+ 750 * | V-EIOINTC | 751 * +-----------+ 752 * ^ ^ 753 * | | 754 * +---------+ +---------+ 755 * | PCH-PIC | | PCH-MSI | 756 * +---------+ +---------+ 757 * ^ ^ ^ 758 * | | | 759 * +--------+ +---------+ +---------+ 760 * | UARTs | | Devices | | Devices | 761 * +--------+ +---------+ +---------+ 762 */ 763 764 /* Create IPI device */ 765 ipi = qdev_new(TYPE_LOONGSON_IPI); 766 qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); 767 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 768 769 /* IPI iocsr memory region */ 770 memory_region_add_subregion(&lvms->system_iocsr, SMP_IPI_MAILBOX, 771 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); 772 memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR, 773 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); 774 775 /* Add cpu interrupt-controller */ 776 fdt_add_cpuic_node(lvms, &cpuintc_phandle); 777 778 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 779 cpu_state = qemu_get_cpu(cpu); 780 cpudev = DEVICE(cpu_state); 781 lacpu = LOONGARCH_CPU(cpu_state); 782 env = &(lacpu->env); 783 env->address_space_iocsr = &lvms->as_iocsr; 784 785 /* connect ipi irq to cpu irq */ 786 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); 787 env->ipistate = ipi; 788 } 789 790 /* Create EXTIOI device */ 791 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 792 qdev_prop_set_uint32(extioi, "num-cpu", ms->smp.cpus); 793 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 794 memory_region_add_subregion(&lvms->system_iocsr, APIC_BASE, 795 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); 796 797 /* 798 * connect ext irq to the cpu irq 799 * cpu_pin[9:2] <= intc_pin[7:0] 800 */ 801 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 802 cpudev = DEVICE(qemu_get_cpu(cpu)); 803 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 804 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 805 qdev_get_gpio_in(cpudev, pin + 2)); 806 } 807 } 808 809 /* Add Extend I/O Interrupt Controller node */ 810 fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle); 811 812 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 813 num = VIRT_PCH_PIC_IRQ_NUM; 814 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 815 d = SYS_BUS_DEVICE(pch_pic); 816 sysbus_realize_and_unref(d, &error_fatal); 817 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 818 sysbus_mmio_get_region(d, 0)); 819 memory_region_add_subregion(get_system_memory(), 820 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 821 sysbus_mmio_get_region(d, 1)); 822 memory_region_add_subregion(get_system_memory(), 823 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 824 sysbus_mmio_get_region(d, 2)); 825 826 /* Connect pch_pic irqs to extioi */ 827 for (i = 0; i < num; i++) { 828 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 829 } 830 831 /* Add PCH PIC node */ 832 fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle); 833 834 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 835 start = num; 836 num = EXTIOI_IRQS - start; 837 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 838 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 839 d = SYS_BUS_DEVICE(pch_msi); 840 sysbus_realize_and_unref(d, &error_fatal); 841 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 842 for (i = 0; i < num; i++) { 843 /* Connect pch_msi irqs to extioi */ 844 qdev_connect_gpio_out(DEVICE(d), i, 845 qdev_get_gpio_in(extioi, i + start)); 846 } 847 848 /* Add PCH MSI node */ 849 fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle); 850 851 virt_devices_init(pch_pic, lvms, &pch_pic_phandle, &pch_msi_phandle); 852 } 853 854 static void virt_firmware_init(LoongArchVirtMachineState *lvms) 855 { 856 char *filename = MACHINE(lvms)->firmware; 857 char *bios_name = NULL; 858 int bios_size, i; 859 BlockBackend *pflash_blk0; 860 MemoryRegion *mr; 861 862 lvms->bios_loaded = false; 863 864 /* Map legacy -drive if=pflash to machine properties */ 865 for (i = 0; i < ARRAY_SIZE(lvms->flash); i++) { 866 pflash_cfi01_legacy_drive(lvms->flash[i], 867 drive_get(IF_PFLASH, 0, i)); 868 } 869 870 virt_flash_map(lvms, get_system_memory()); 871 872 pflash_blk0 = pflash_cfi01_get_blk(lvms->flash[0]); 873 874 if (pflash_blk0) { 875 if (filename) { 876 error_report("cannot use both '-bios' and '-drive if=pflash'" 877 "options at once"); 878 exit(1); 879 } 880 lvms->bios_loaded = true; 881 return; 882 } 883 884 if (filename) { 885 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 886 if (!bios_name) { 887 error_report("Could not find ROM image '%s'", filename); 888 exit(1); 889 } 890 891 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lvms->flash[0]), 0); 892 bios_size = load_image_mr(bios_name, mr); 893 if (bios_size < 0) { 894 error_report("Could not load ROM image '%s'", bios_name); 895 exit(1); 896 } 897 g_free(bios_name); 898 lvms->bios_loaded = true; 899 } 900 } 901 902 903 static void virt_iocsr_misc_write(void *opaque, hwaddr addr, 904 uint64_t val, unsigned size) 905 { 906 } 907 908 static uint64_t virt_iocsr_misc_read(void *opaque, hwaddr addr, unsigned size) 909 { 910 uint64_t ret; 911 912 switch (addr) { 913 case VERSION_REG: 914 return 0x11ULL; 915 case FEATURE_REG: 916 ret = BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); 917 if (kvm_enabled()) { 918 ret |= BIT(IOCSRF_VM); 919 } 920 return ret; 921 case VENDOR_REG: 922 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 923 case CPUNAME_REG: 924 return 0x303030354133ULL; /* "3A5000" */ 925 case MISC_FUNC_REG: 926 return BIT_ULL(IOCSRM_EXTIOI_EN); 927 } 928 return 0ULL; 929 } 930 931 static const MemoryRegionOps virt_iocsr_misc_ops = { 932 .read = virt_iocsr_misc_read, 933 .write = virt_iocsr_misc_write, 934 .endianness = DEVICE_LITTLE_ENDIAN, 935 .valid = { 936 .min_access_size = 4, 937 .max_access_size = 8, 938 }, 939 .impl = { 940 .min_access_size = 8, 941 .max_access_size = 8, 942 }, 943 }; 944 945 static void fw_cfg_add_memory(MachineState *ms) 946 { 947 hwaddr base, size, ram_size, gap; 948 int nb_numa_nodes, nodes; 949 NodeInfo *numa_info; 950 951 ram_size = ms->ram_size; 952 base = VIRT_LOWMEM_BASE; 953 gap = VIRT_LOWMEM_SIZE; 954 nodes = nb_numa_nodes = ms->numa_state->num_nodes; 955 numa_info = ms->numa_state->nodes; 956 if (!nodes) { 957 nodes = 1; 958 } 959 960 /* add fw_cfg memory map of node0 */ 961 if (nb_numa_nodes) { 962 size = numa_info[0].node_mem; 963 } else { 964 size = ram_size; 965 } 966 967 if (size >= gap) { 968 memmap_add_entry(base, gap, 1); 969 size -= gap; 970 base = VIRT_HIGHMEM_BASE; 971 gap = ram_size - VIRT_LOWMEM_SIZE; 972 } 973 974 if (size) { 975 memmap_add_entry(base, size, 1); 976 base += size; 977 } 978 979 if (nodes < 2) { 980 return; 981 } 982 983 /* add fw_cfg memory map of other nodes */ 984 size = ram_size - numa_info[0].node_mem; 985 gap = VIRT_LOWMEM_BASE + VIRT_LOWMEM_SIZE; 986 if (base < gap && (base + size) > gap) { 987 /* 988 * memory map for the maining nodes splited into two part 989 * lowram: [base, +(gap - base)) 990 * highram: [VIRT_HIGHMEM_BASE, +(size - (gap - base))) 991 */ 992 memmap_add_entry(base, gap - base, 1); 993 size -= gap - base; 994 base = VIRT_HIGHMEM_BASE; 995 } 996 997 if (size) 998 memmap_add_entry(base, size, 1); 999 } 1000 1001 static void virt_init(MachineState *machine) 1002 { 1003 LoongArchCPU *lacpu; 1004 const char *cpu_model = machine->cpu_type; 1005 MemoryRegion *address_space_mem = get_system_memory(); 1006 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine); 1007 int i; 1008 hwaddr base, size, ram_size = machine->ram_size; 1009 const CPUArchIdList *possible_cpus; 1010 MachineClass *mc = MACHINE_GET_CLASS(machine); 1011 CPUState *cpu; 1012 1013 if (!cpu_model) { 1014 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 1015 } 1016 1017 create_fdt(lvms); 1018 1019 /* Create IOCSR space */ 1020 memory_region_init_io(&lvms->system_iocsr, OBJECT(machine), NULL, 1021 machine, "iocsr", UINT64_MAX); 1022 address_space_init(&lvms->as_iocsr, &lvms->system_iocsr, "IOCSR"); 1023 memory_region_init_io(&lvms->iocsr_mem, OBJECT(machine), 1024 &virt_iocsr_misc_ops, 1025 machine, "iocsr_misc", 0x428); 1026 memory_region_add_subregion(&lvms->system_iocsr, 0, &lvms->iocsr_mem); 1027 1028 /* Init CPUs */ 1029 possible_cpus = mc->possible_cpu_arch_ids(machine); 1030 for (i = 0; i < possible_cpus->len; i++) { 1031 cpu = cpu_create(machine->cpu_type); 1032 cpu->cpu_index = i; 1033 machine->possible_cpus->cpus[i].cpu = cpu; 1034 lacpu = LOONGARCH_CPU(cpu); 1035 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; 1036 } 1037 fdt_add_cpu_nodes(lvms); 1038 fdt_add_memory_nodes(machine); 1039 fw_cfg_add_memory(machine); 1040 1041 /* Node0 memory */ 1042 size = ram_size; 1043 base = VIRT_LOWMEM_BASE; 1044 if (size > VIRT_LOWMEM_SIZE) { 1045 size = VIRT_LOWMEM_SIZE; 1046 } 1047 1048 memory_region_init_alias(&lvms->lowmem, NULL, "loongarch.lowram", 1049 machine->ram, base, size); 1050 memory_region_add_subregion(address_space_mem, base, &lvms->lowmem); 1051 base += size; 1052 if (ram_size - size) { 1053 base = VIRT_HIGHMEM_BASE; 1054 memory_region_init_alias(&lvms->highmem, NULL, "loongarch.highram", 1055 machine->ram, VIRT_LOWMEM_BASE + size, ram_size - size); 1056 memory_region_add_subregion(address_space_mem, base, &lvms->highmem); 1057 base += ram_size - size; 1058 } 1059 1060 /* initialize device memory address space */ 1061 if (machine->ram_size < machine->maxram_size) { 1062 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 1063 1064 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1065 error_report("unsupported amount of memory slots: %"PRIu64, 1066 machine->ram_slots); 1067 exit(EXIT_FAILURE); 1068 } 1069 1070 if (QEMU_ALIGN_UP(machine->maxram_size, 1071 TARGET_PAGE_SIZE) != machine->maxram_size) { 1072 error_report("maximum memory size must by aligned to multiple of " 1073 "%d bytes", TARGET_PAGE_SIZE); 1074 exit(EXIT_FAILURE); 1075 } 1076 machine_memory_devices_init(machine, base, device_mem_size); 1077 } 1078 1079 /* load the BIOS image. */ 1080 virt_firmware_init(lvms); 1081 1082 /* fw_cfg init */ 1083 lvms->fw_cfg = virt_fw_cfg_init(ram_size, machine); 1084 rom_set_fw(lvms->fw_cfg); 1085 if (lvms->fw_cfg != NULL) { 1086 fw_cfg_add_file(lvms->fw_cfg, "etc/memmap", 1087 memmap_table, 1088 sizeof(struct memmap_entry) * (memmap_entries)); 1089 } 1090 fdt_add_fw_cfg_node(lvms); 1091 fdt_add_flash_node(lvms); 1092 1093 /* Initialize the IO interrupt subsystem */ 1094 virt_irq_init(lvms); 1095 platform_bus_add_all_fdt_nodes(machine->fdt, "/platic", 1096 VIRT_PLATFORM_BUS_BASEADDRESS, 1097 VIRT_PLATFORM_BUS_SIZE, 1098 VIRT_PLATFORM_BUS_IRQ); 1099 lvms->machine_done.notify = virt_done; 1100 qemu_add_machine_init_done_notifier(&lvms->machine_done); 1101 /* connect powerdown request */ 1102 lvms->powerdown_notifier.notify = virt_powerdown_req; 1103 qemu_register_powerdown_notifier(&lvms->powerdown_notifier); 1104 1105 /* 1106 * Since lowmem region starts from 0 and Linux kernel legacy start address 1107 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer 1108 * access. FDT size limit with 1 MiB. 1109 * Put the FDT into the memory map as a ROM image: this will ensure 1110 * the FDT is copied again upon reset, even if addr points into RAM. 1111 */ 1112 qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size); 1113 rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE, 1114 &address_space_memory); 1115 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 1116 rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size)); 1117 1118 lvms->bootinfo.ram_size = ram_size; 1119 loongarch_load_kernel(machine, &lvms->bootinfo); 1120 } 1121 1122 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1123 void *opaque, Error **errp) 1124 { 1125 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 1126 OnOffAuto acpi = lvms->acpi; 1127 1128 visit_type_OnOffAuto(v, name, &acpi, errp); 1129 } 1130 1131 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1132 void *opaque, Error **errp) 1133 { 1134 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 1135 1136 visit_type_OnOffAuto(v, name, &lvms->acpi, errp); 1137 } 1138 1139 static void virt_initfn(Object *obj) 1140 { 1141 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 1142 1143 lvms->acpi = ON_OFF_AUTO_AUTO; 1144 lvms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1145 lvms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1146 virt_flash_create(lvms); 1147 } 1148 1149 static bool memhp_type_supported(DeviceState *dev) 1150 { 1151 /* we only support pc dimm now */ 1152 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 1153 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1154 } 1155 1156 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1157 Error **errp) 1158 { 1159 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 1160 } 1161 1162 static void virt_device_pre_plug(HotplugHandler *hotplug_dev, 1163 DeviceState *dev, Error **errp) 1164 { 1165 if (memhp_type_supported(dev)) { 1166 virt_mem_pre_plug(hotplug_dev, dev, errp); 1167 } 1168 } 1169 1170 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 1171 DeviceState *dev, Error **errp) 1172 { 1173 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 1174 1175 /* the acpi ged is always exist */ 1176 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lvms->acpi_ged), dev, 1177 errp); 1178 } 1179 1180 static void virt_device_unplug_request(HotplugHandler *hotplug_dev, 1181 DeviceState *dev, Error **errp) 1182 { 1183 if (memhp_type_supported(dev)) { 1184 virt_mem_unplug_request(hotplug_dev, dev, errp); 1185 } 1186 } 1187 1188 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 1189 DeviceState *dev, Error **errp) 1190 { 1191 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 1192 1193 hotplug_handler_unplug(HOTPLUG_HANDLER(lvms->acpi_ged), dev, errp); 1194 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lvms)); 1195 qdev_unrealize(dev); 1196 } 1197 1198 static void virt_device_unplug(HotplugHandler *hotplug_dev, 1199 DeviceState *dev, Error **errp) 1200 { 1201 if (memhp_type_supported(dev)) { 1202 virt_mem_unplug(hotplug_dev, dev, errp); 1203 } 1204 } 1205 1206 static void virt_mem_plug(HotplugHandler *hotplug_dev, 1207 DeviceState *dev, Error **errp) 1208 { 1209 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 1210 1211 pc_dimm_plug(PC_DIMM(dev), MACHINE(lvms)); 1212 hotplug_handler_plug(HOTPLUG_HANDLER(lvms->acpi_ged), 1213 dev, &error_abort); 1214 } 1215 1216 static void virt_device_plug_cb(HotplugHandler *hotplug_dev, 1217 DeviceState *dev, Error **errp) 1218 { 1219 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 1220 MachineClass *mc = MACHINE_GET_CLASS(lvms); 1221 PlatformBusDevice *pbus; 1222 1223 if (device_is_dynamic_sysbus(mc, dev)) { 1224 if (lvms->platform_bus_dev) { 1225 pbus = PLATFORM_BUS_DEVICE(lvms->platform_bus_dev); 1226 platform_bus_link_device(pbus, SYS_BUS_DEVICE(dev)); 1227 } 1228 } else if (memhp_type_supported(dev)) { 1229 virt_mem_plug(hotplug_dev, dev, errp); 1230 } 1231 } 1232 1233 static HotplugHandler *virt_get_hotplug_handler(MachineState *machine, 1234 DeviceState *dev) 1235 { 1236 MachineClass *mc = MACHINE_GET_CLASS(machine); 1237 1238 if (device_is_dynamic_sysbus(mc, dev) || 1239 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1240 memhp_type_supported(dev)) { 1241 return HOTPLUG_HANDLER(machine); 1242 } 1243 return NULL; 1244 } 1245 1246 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1247 { 1248 int n; 1249 unsigned int max_cpus = ms->smp.max_cpus; 1250 1251 if (ms->possible_cpus) { 1252 assert(ms->possible_cpus->len == max_cpus); 1253 return ms->possible_cpus; 1254 } 1255 1256 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1257 sizeof(CPUArchId) * max_cpus); 1258 ms->possible_cpus->len = max_cpus; 1259 for (n = 0; n < ms->possible_cpus->len; n++) { 1260 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1261 ms->possible_cpus->cpus[n].arch_id = n; 1262 1263 ms->possible_cpus->cpus[n].props.has_socket_id = true; 1264 ms->possible_cpus->cpus[n].props.socket_id = 1265 n / (ms->smp.cores * ms->smp.threads); 1266 ms->possible_cpus->cpus[n].props.has_core_id = true; 1267 ms->possible_cpus->cpus[n].props.core_id = 1268 n / ms->smp.threads % ms->smp.cores; 1269 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1270 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 1271 } 1272 return ms->possible_cpus; 1273 } 1274 1275 static CpuInstanceProperties virt_cpu_index_to_props(MachineState *ms, 1276 unsigned cpu_index) 1277 { 1278 MachineClass *mc = MACHINE_GET_CLASS(ms); 1279 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1280 1281 assert(cpu_index < possible_cpus->len); 1282 return possible_cpus->cpus[cpu_index].props; 1283 } 1284 1285 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1286 { 1287 int64_t socket_id; 1288 1289 if (ms->numa_state->num_nodes) { 1290 socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 1291 return socket_id % ms->numa_state->num_nodes; 1292 } else { 1293 return 0; 1294 } 1295 } 1296 1297 static void virt_class_init(ObjectClass *oc, void *data) 1298 { 1299 MachineClass *mc = MACHINE_CLASS(oc); 1300 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1301 1302 mc->init = virt_init; 1303 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 1304 mc->default_ram_id = "loongarch.ram"; 1305 mc->max_cpus = LOONGARCH_MAX_CPUS; 1306 mc->is_default = 1; 1307 mc->default_kernel_irqchip_split = false; 1308 mc->block_default_type = IF_VIRTIO; 1309 mc->default_boot_order = "c"; 1310 mc->no_cdrom = 1; 1311 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1312 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1313 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1314 mc->numa_mem_supported = true; 1315 mc->auto_enable_numa_with_memhp = true; 1316 mc->auto_enable_numa_with_memdev = true; 1317 mc->get_hotplug_handler = virt_get_hotplug_handler; 1318 mc->default_nic = "virtio-net-pci"; 1319 hc->plug = virt_device_plug_cb; 1320 hc->pre_plug = virt_device_pre_plug; 1321 hc->unplug_request = virt_device_unplug_request; 1322 hc->unplug = virt_device_unplug; 1323 1324 object_class_property_add(oc, "acpi", "OnOffAuto", 1325 virt_get_acpi, virt_set_acpi, 1326 NULL, NULL); 1327 object_class_property_set_description(oc, "acpi", 1328 "Enable ACPI"); 1329 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1330 #ifdef CONFIG_TPM 1331 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1332 #endif 1333 } 1334 1335 static const TypeInfo virt_machine_types[] = { 1336 { 1337 .name = TYPE_LOONGARCH_VIRT_MACHINE, 1338 .parent = TYPE_MACHINE, 1339 .instance_size = sizeof(LoongArchVirtMachineState), 1340 .class_init = virt_class_init, 1341 .instance_init = virt_initfn, 1342 .interfaces = (InterfaceInfo[]) { 1343 { TYPE_HOTPLUG_HANDLER }, 1344 { } 1345 }, 1346 } 1347 }; 1348 1349 DEFINE_TYPES(virt_machine_types) 1350