1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial-mm.h" 13 #include "system/kvm.h" 14 #include "system/tcg.h" 15 #include "system/system.h" 16 #include "system/qtest.h" 17 #include "system/runstate.h" 18 #include "system/reset.h" 19 #include "system/rtc.h" 20 #include "hw/loongarch/virt.h" 21 #include "exec/address-spaces.h" 22 #include "hw/irq.h" 23 #include "net/net.h" 24 #include "hw/loader.h" 25 #include "elf.h" 26 #include "hw/intc/loongarch_ipi.h" 27 #include "hw/intc/loongarch_extioi.h" 28 #include "hw/intc/loongarch_pch_pic.h" 29 #include "hw/intc/loongarch_pch_msi.h" 30 #include "hw/pci-host/ls7a.h" 31 #include "hw/pci-host/gpex.h" 32 #include "hw/misc/unimp.h" 33 #include "hw/loongarch/fw_cfg.h" 34 #include "target/loongarch/cpu.h" 35 #include "hw/firmware/smbios.h" 36 #include "hw/acpi/aml-build.h" 37 #include "qapi/qapi-visit-common.h" 38 #include "hw/acpi/generic_event_device.h" 39 #include "hw/mem/nvdimm.h" 40 #include "system/device_tree.h" 41 #include <libfdt.h> 42 #include "hw/core/sysbus-fdt.h" 43 #include "hw/platform-bus.h" 44 #include "hw/display/ramfb.h" 45 #include "hw/mem/pc-dimm.h" 46 #include "system/tpm.h" 47 #include "system/block-backend.h" 48 #include "hw/block/flash.h" 49 #include "hw/virtio/virtio-iommu.h" 50 #include "qemu/error-report.h" 51 #include "qemu/guest-random.h" 52 53 static bool virt_is_veiointc_enabled(LoongArchVirtMachineState *lvms) 54 { 55 if (lvms->veiointc == ON_OFF_AUTO_OFF) { 56 return false; 57 } 58 return true; 59 } 60 61 static void virt_get_veiointc(Object *obj, Visitor *v, const char *name, 62 void *opaque, Error **errp) 63 { 64 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 65 OnOffAuto veiointc = lvms->veiointc; 66 67 visit_type_OnOffAuto(v, name, &veiointc, errp); 68 } 69 70 static void virt_set_veiointc(Object *obj, Visitor *v, const char *name, 71 void *opaque, Error **errp) 72 { 73 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 74 75 visit_type_OnOffAuto(v, name, &lvms->veiointc, errp); 76 } 77 78 static PFlashCFI01 *virt_flash_create1(LoongArchVirtMachineState *lvms, 79 const char *name, 80 const char *alias_prop_name) 81 { 82 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 83 84 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 85 qdev_prop_set_uint8(dev, "width", 4); 86 qdev_prop_set_uint8(dev, "device-width", 2); 87 qdev_prop_set_bit(dev, "big-endian", false); 88 qdev_prop_set_uint16(dev, "id0", 0x89); 89 qdev_prop_set_uint16(dev, "id1", 0x18); 90 qdev_prop_set_uint16(dev, "id2", 0x00); 91 qdev_prop_set_uint16(dev, "id3", 0x00); 92 qdev_prop_set_string(dev, "name", name); 93 object_property_add_child(OBJECT(lvms), name, OBJECT(dev)); 94 object_property_add_alias(OBJECT(lvms), alias_prop_name, 95 OBJECT(dev), "drive"); 96 return PFLASH_CFI01(dev); 97 } 98 99 static void virt_flash_create(LoongArchVirtMachineState *lvms) 100 { 101 lvms->flash[0] = virt_flash_create1(lvms, "virt.flash0", "pflash0"); 102 lvms->flash[1] = virt_flash_create1(lvms, "virt.flash1", "pflash1"); 103 } 104 105 static void virt_flash_map1(PFlashCFI01 *flash, 106 hwaddr base, hwaddr size, 107 MemoryRegion *sysmem) 108 { 109 DeviceState *dev = DEVICE(flash); 110 BlockBackend *blk; 111 hwaddr real_size = size; 112 113 blk = pflash_cfi01_get_blk(flash); 114 if (blk) { 115 real_size = blk_getlength(blk); 116 assert(real_size && real_size <= size); 117 } 118 119 assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE)); 120 assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 121 122 qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE); 123 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 124 memory_region_add_subregion(sysmem, base, 125 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 126 } 127 128 static void virt_flash_map(LoongArchVirtMachineState *lvms, 129 MemoryRegion *sysmem) 130 { 131 PFlashCFI01 *flash0 = lvms->flash[0]; 132 PFlashCFI01 *flash1 = lvms->flash[1]; 133 134 virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem); 135 virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem); 136 } 137 138 static void fdt_add_cpuic_node(LoongArchVirtMachineState *lvms, 139 uint32_t *cpuintc_phandle) 140 { 141 MachineState *ms = MACHINE(lvms); 142 char *nodename; 143 144 *cpuintc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 145 nodename = g_strdup_printf("/cpuic"); 146 qemu_fdt_add_subnode(ms->fdt, nodename); 147 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *cpuintc_phandle); 148 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 149 "loongson,cpu-interrupt-controller"); 150 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 151 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 152 g_free(nodename); 153 } 154 155 static void fdt_add_eiointc_node(LoongArchVirtMachineState *lvms, 156 uint32_t *cpuintc_phandle, 157 uint32_t *eiointc_phandle) 158 { 159 MachineState *ms = MACHINE(lvms); 160 char *nodename; 161 hwaddr extioi_base = APIC_BASE; 162 hwaddr extioi_size = EXTIOI_SIZE; 163 164 *eiointc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 165 nodename = g_strdup_printf("/eiointc@%" PRIx64, extioi_base); 166 qemu_fdt_add_subnode(ms->fdt, nodename); 167 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *eiointc_phandle); 168 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 169 "loongson,ls2k2000-eiointc"); 170 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 171 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 172 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 173 *cpuintc_phandle); 174 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", 3); 175 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, 176 extioi_base, 0x0, extioi_size); 177 g_free(nodename); 178 } 179 180 static void fdt_add_pch_pic_node(LoongArchVirtMachineState *lvms, 181 uint32_t *eiointc_phandle, 182 uint32_t *pch_pic_phandle) 183 { 184 MachineState *ms = MACHINE(lvms); 185 char *nodename; 186 hwaddr pch_pic_base = VIRT_PCH_REG_BASE; 187 hwaddr pch_pic_size = VIRT_PCH_REG_SIZE; 188 189 *pch_pic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 190 nodename = g_strdup_printf("/platic@%" PRIx64, pch_pic_base); 191 qemu_fdt_add_subnode(ms->fdt, nodename); 192 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_pic_phandle); 193 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 194 "loongson,pch-pic-1.0"); 195 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, 196 pch_pic_base, 0, pch_pic_size); 197 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 198 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 2); 199 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 200 *eiointc_phandle); 201 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,pic-base-vec", 0); 202 g_free(nodename); 203 } 204 205 static void fdt_add_pch_msi_node(LoongArchVirtMachineState *lvms, 206 uint32_t *eiointc_phandle, 207 uint32_t *pch_msi_phandle) 208 { 209 MachineState *ms = MACHINE(lvms); 210 char *nodename; 211 hwaddr pch_msi_base = VIRT_PCH_MSI_ADDR_LOW; 212 hwaddr pch_msi_size = VIRT_PCH_MSI_SIZE; 213 214 *pch_msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 215 nodename = g_strdup_printf("/msi@%" PRIx64, pch_msi_base); 216 qemu_fdt_add_subnode(ms->fdt, nodename); 217 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_msi_phandle); 218 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 219 "loongson,pch-msi-1.0"); 220 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 221 0, pch_msi_base, 222 0, pch_msi_size); 223 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 224 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 225 *eiointc_phandle); 226 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-base-vec", 227 VIRT_PCH_PIC_IRQ_NUM); 228 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-num-vecs", 229 EXTIOI_IRQS - VIRT_PCH_PIC_IRQ_NUM); 230 g_free(nodename); 231 } 232 233 static void fdt_add_flash_node(LoongArchVirtMachineState *lvms) 234 { 235 MachineState *ms = MACHINE(lvms); 236 char *nodename; 237 MemoryRegion *flash_mem; 238 239 hwaddr flash0_base; 240 hwaddr flash0_size; 241 242 hwaddr flash1_base; 243 hwaddr flash1_size; 244 245 flash_mem = pflash_cfi01_get_memory(lvms->flash[0]); 246 flash0_base = flash_mem->addr; 247 flash0_size = memory_region_size(flash_mem); 248 249 flash_mem = pflash_cfi01_get_memory(lvms->flash[1]); 250 flash1_base = flash_mem->addr; 251 flash1_size = memory_region_size(flash_mem); 252 253 nodename = g_strdup_printf("/flash@%" PRIx64, flash0_base); 254 qemu_fdt_add_subnode(ms->fdt, nodename); 255 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 256 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 257 2, flash0_base, 2, flash0_size, 258 2, flash1_base, 2, flash1_size); 259 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 260 g_free(nodename); 261 } 262 263 static void fdt_add_rtc_node(LoongArchVirtMachineState *lvms, 264 uint32_t *pch_pic_phandle) 265 { 266 char *nodename; 267 hwaddr base = VIRT_RTC_REG_BASE; 268 hwaddr size = VIRT_RTC_LEN; 269 MachineState *ms = MACHINE(lvms); 270 271 nodename = g_strdup_printf("/rtc@%" PRIx64, base); 272 qemu_fdt_add_subnode(ms->fdt, nodename); 273 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 274 "loongson,ls7a-rtc"); 275 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 276 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 277 VIRT_RTC_IRQ - VIRT_GSI_BASE , 0x4); 278 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 279 *pch_pic_phandle); 280 g_free(nodename); 281 } 282 283 static void fdt_add_ged_reset(LoongArchVirtMachineState *lvms) 284 { 285 char *name; 286 uint32_t ged_handle; 287 MachineState *ms = MACHINE(lvms); 288 hwaddr base = VIRT_GED_REG_ADDR; 289 hwaddr size = ACPI_GED_REG_COUNT; 290 291 ged_handle = qemu_fdt_alloc_phandle(ms->fdt); 292 name = g_strdup_printf("/ged@%" PRIx64, base); 293 qemu_fdt_add_subnode(ms->fdt, name); 294 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon"); 295 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, base, 0x0, size); 296 /* 8 bit registers */ 297 qemu_fdt_setprop_cell(ms->fdt, name, "reg-shift", 0); 298 qemu_fdt_setprop_cell(ms->fdt, name, "reg-io-width", 1); 299 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", ged_handle); 300 ged_handle = qemu_fdt_get_phandle(ms->fdt, name); 301 g_free(name); 302 303 name = g_strdup_printf("/reboot"); 304 qemu_fdt_add_subnode(ms->fdt, name); 305 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 306 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", ged_handle); 307 qemu_fdt_setprop_cell(ms->fdt, name, "offset", ACPI_GED_REG_RESET); 308 qemu_fdt_setprop_cell(ms->fdt, name, "value", ACPI_GED_RESET_VALUE); 309 g_free(name); 310 311 name = g_strdup_printf("/poweroff"); 312 qemu_fdt_add_subnode(ms->fdt, name); 313 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 314 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", ged_handle); 315 qemu_fdt_setprop_cell(ms->fdt, name, "offset", ACPI_GED_REG_SLEEP_CTL); 316 qemu_fdt_setprop_cell(ms->fdt, name, "value", ACPI_GED_SLP_EN | 317 (ACPI_GED_SLP_TYP_S5 << ACPI_GED_SLP_TYP_POS)); 318 g_free(name); 319 } 320 321 static void fdt_add_uart_node(LoongArchVirtMachineState *lvms, 322 uint32_t *pch_pic_phandle, hwaddr base, 323 int irq, bool chosen) 324 { 325 char *nodename; 326 hwaddr size = VIRT_UART_SIZE; 327 MachineState *ms = MACHINE(lvms); 328 329 nodename = g_strdup_printf("/serial@%" PRIx64, base); 330 qemu_fdt_add_subnode(ms->fdt, nodename); 331 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); 332 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); 333 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); 334 if (chosen) 335 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 336 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", irq, 0x4); 337 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 338 *pch_pic_phandle); 339 g_free(nodename); 340 } 341 342 static void create_fdt(LoongArchVirtMachineState *lvms) 343 { 344 MachineState *ms = MACHINE(lvms); 345 uint8_t rng_seed[32]; 346 347 ms->fdt = create_device_tree(&lvms->fdt_size); 348 if (!ms->fdt) { 349 error_report("create_device_tree() failed"); 350 exit(1); 351 } 352 353 /* Header */ 354 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 355 "linux,dummy-loongson3"); 356 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 357 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 358 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 359 360 /* Pass seed to RNG */ 361 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 362 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); 363 } 364 365 static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms) 366 { 367 int num; 368 MachineState *ms = MACHINE(lvms); 369 MachineClass *mc = MACHINE_GET_CLASS(ms); 370 const CPUArchIdList *possible_cpus; 371 LoongArchCPU *cpu; 372 CPUState *cs; 373 char *nodename, *map_path; 374 375 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 376 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 377 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 378 379 /* cpu nodes */ 380 possible_cpus = mc->possible_cpu_arch_ids(ms); 381 for (num = 0; num < possible_cpus->len; num++) { 382 cs = possible_cpus->cpus[num].cpu; 383 if (cs == NULL) { 384 continue; 385 } 386 387 nodename = g_strdup_printf("/cpus/cpu@%d", num); 388 cpu = LOONGARCH_CPU(cs); 389 390 qemu_fdt_add_subnode(ms->fdt, nodename); 391 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 392 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 393 cpu->dtb_compatible); 394 if (possible_cpus->cpus[num].props.has_node_id) { 395 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 396 possible_cpus->cpus[num].props.node_id); 397 } 398 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 399 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 400 qemu_fdt_alloc_phandle(ms->fdt)); 401 g_free(nodename); 402 } 403 404 /*cpu map */ 405 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 406 for (num = 0; num < possible_cpus->len; num++) { 407 cs = possible_cpus->cpus[num].cpu; 408 if (cs == NULL) { 409 continue; 410 } 411 412 nodename = g_strdup_printf("/cpus/cpu@%d", num); 413 if (ms->smp.threads > 1) { 414 map_path = g_strdup_printf( 415 "/cpus/cpu-map/socket%d/core%d/thread%d", 416 num / (ms->smp.cores * ms->smp.threads), 417 (num / ms->smp.threads) % ms->smp.cores, 418 num % ms->smp.threads); 419 } else { 420 map_path = g_strdup_printf( 421 "/cpus/cpu-map/socket%d/core%d", 422 num / ms->smp.cores, 423 num % ms->smp.cores); 424 } 425 qemu_fdt_add_path(ms->fdt, map_path); 426 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", nodename); 427 428 g_free(map_path); 429 g_free(nodename); 430 } 431 } 432 433 static void fdt_add_fw_cfg_node(const LoongArchVirtMachineState *lvms) 434 { 435 char *nodename; 436 hwaddr base = VIRT_FWCFG_BASE; 437 const MachineState *ms = MACHINE(lvms); 438 439 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 440 qemu_fdt_add_subnode(ms->fdt, nodename); 441 qemu_fdt_setprop_string(ms->fdt, nodename, 442 "compatible", "qemu,fw-cfg-mmio"); 443 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 444 2, base, 2, 0x18); 445 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 446 g_free(nodename); 447 } 448 449 static void fdt_add_pcie_irq_map_node(const LoongArchVirtMachineState *lvms, 450 char *nodename, 451 uint32_t *pch_pic_phandle) 452 { 453 int pin, dev; 454 uint32_t irq_map_stride = 0; 455 uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS * 10] = {}; 456 uint32_t *irq_map = full_irq_map; 457 const MachineState *ms = MACHINE(lvms); 458 459 /* This code creates a standard swizzle of interrupts such that 460 * each device's first interrupt is based on it's PCI_SLOT number. 461 * (See pci_swizzle_map_irq_fn()) 462 * 463 * We only need one entry per interrupt in the table (not one per 464 * possible slot) seeing the interrupt-map-mask will allow the table 465 * to wrap to any number of devices. 466 */ 467 468 for (dev = 0; dev < PCI_NUM_PINS; dev++) { 469 int devfn = dev * 0x8; 470 471 for (pin = 0; pin < PCI_NUM_PINS; pin++) { 472 int irq_nr = 16 + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 473 int i = 0; 474 475 /* Fill PCI address cells */ 476 irq_map[i] = cpu_to_be32(devfn << 8); 477 i += 3; 478 479 /* Fill PCI Interrupt cells */ 480 irq_map[i] = cpu_to_be32(pin + 1); 481 i += 1; 482 483 /* Fill interrupt controller phandle and cells */ 484 irq_map[i++] = cpu_to_be32(*pch_pic_phandle); 485 irq_map[i++] = cpu_to_be32(irq_nr); 486 487 if (!irq_map_stride) { 488 irq_map_stride = i; 489 } 490 irq_map += irq_map_stride; 491 } 492 } 493 494 495 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", full_irq_map, 496 PCI_NUM_PINS * PCI_NUM_PINS * 497 irq_map_stride * sizeof(uint32_t)); 498 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 499 0x1800, 0, 0, 0x7); 500 } 501 502 static void fdt_add_pcie_node(const LoongArchVirtMachineState *lvms, 503 uint32_t *pch_pic_phandle, 504 uint32_t *pch_msi_phandle) 505 { 506 char *nodename; 507 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 508 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 509 hwaddr base_pio = VIRT_PCI_IO_BASE; 510 hwaddr size_pio = VIRT_PCI_IO_SIZE; 511 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 512 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 513 hwaddr base = base_pcie; 514 515 const MachineState *ms = MACHINE(lvms); 516 517 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 518 qemu_fdt_add_subnode(ms->fdt, nodename); 519 qemu_fdt_setprop_string(ms->fdt, nodename, 520 "compatible", "pci-host-ecam-generic"); 521 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 522 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 523 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 524 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 525 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 526 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 527 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 528 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 529 2, base_pcie, 2, size_pcie); 530 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 531 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 532 2, base_pio, 2, size_pio, 533 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 534 2, base_mmio, 2, size_mmio); 535 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 536 0, *pch_msi_phandle, 0, 0x10000); 537 538 fdt_add_pcie_irq_map_node(lvms, nodename, pch_pic_phandle); 539 540 g_free(nodename); 541 } 542 543 static void fdt_add_memory_node(MachineState *ms, 544 uint64_t base, uint64_t size, int node_id) 545 { 546 char *nodename = g_strdup_printf("/memory@%" PRIx64, base); 547 548 qemu_fdt_add_subnode(ms->fdt, nodename); 549 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", base >> 32, base, 550 size >> 32, size); 551 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 552 553 if (ms->numa_state && ms->numa_state->num_nodes) { 554 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); 555 } 556 557 g_free(nodename); 558 } 559 560 static void fdt_add_memory_nodes(MachineState *ms) 561 { 562 hwaddr base, size, ram_size, gap; 563 int i, nb_numa_nodes, nodes; 564 NodeInfo *numa_info; 565 566 ram_size = ms->ram_size; 567 base = VIRT_LOWMEM_BASE; 568 gap = VIRT_LOWMEM_SIZE; 569 nodes = nb_numa_nodes = ms->numa_state->num_nodes; 570 numa_info = ms->numa_state->nodes; 571 if (!nodes) { 572 nodes = 1; 573 } 574 575 for (i = 0; i < nodes; i++) { 576 if (nb_numa_nodes) { 577 size = numa_info[i].node_mem; 578 } else { 579 size = ram_size; 580 } 581 582 /* 583 * memory for the node splited into two part 584 * lowram: [base, +gap) 585 * highram: [VIRT_HIGHMEM_BASE, +(len - gap)) 586 */ 587 if (size >= gap) { 588 fdt_add_memory_node(ms, base, gap, i); 589 size -= gap; 590 base = VIRT_HIGHMEM_BASE; 591 gap = ram_size - VIRT_LOWMEM_SIZE; 592 } 593 594 if (size) { 595 fdt_add_memory_node(ms, base, size, i); 596 base += size; 597 gap -= size; 598 } 599 } 600 } 601 602 static void virt_build_smbios(LoongArchVirtMachineState *lvms) 603 { 604 MachineState *ms = MACHINE(lvms); 605 MachineClass *mc = MACHINE_GET_CLASS(lvms); 606 uint8_t *smbios_tables, *smbios_anchor; 607 size_t smbios_tables_len, smbios_anchor_len; 608 const char *product = "QEMU Virtual Machine"; 609 610 if (!lvms->fw_cfg) { 611 return; 612 } 613 614 smbios_set_defaults("QEMU", product, mc->name); 615 616 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 617 NULL, 0, 618 &smbios_tables, &smbios_tables_len, 619 &smbios_anchor, &smbios_anchor_len, &error_fatal); 620 621 if (smbios_anchor) { 622 fw_cfg_add_file(lvms->fw_cfg, "etc/smbios/smbios-tables", 623 smbios_tables, smbios_tables_len); 624 fw_cfg_add_file(lvms->fw_cfg, "etc/smbios/smbios-anchor", 625 smbios_anchor, smbios_anchor_len); 626 } 627 } 628 629 static void virt_fdt_setup(LoongArchVirtMachineState *lvms) 630 { 631 MachineState *machine = MACHINE(lvms); 632 uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle; 633 int i; 634 635 create_fdt(lvms); 636 fdt_add_cpu_nodes(lvms); 637 fdt_add_memory_nodes(machine); 638 fdt_add_fw_cfg_node(lvms); 639 fdt_add_flash_node(lvms); 640 641 /* Add cpu interrupt-controller */ 642 fdt_add_cpuic_node(lvms, &cpuintc_phandle); 643 /* Add Extend I/O Interrupt Controller node */ 644 fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle); 645 /* Add PCH PIC node */ 646 fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle); 647 /* Add PCH MSI node */ 648 fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle); 649 /* Add pcie node */ 650 fdt_add_pcie_node(lvms, &pch_pic_phandle, &pch_msi_phandle); 651 652 /* 653 * Create uart fdt node in reverse order so that they appear 654 * in the finished device tree lowest address first 655 */ 656 for (i = VIRT_UART_COUNT; i-- > 0;) { 657 hwaddr base = VIRT_UART_BASE + i * VIRT_UART_SIZE; 658 int irq = VIRT_UART_IRQ + i - VIRT_GSI_BASE; 659 fdt_add_uart_node(lvms, &pch_pic_phandle, base, irq, i == 0); 660 } 661 662 fdt_add_rtc_node(lvms, &pch_pic_phandle); 663 fdt_add_ged_reset(lvms); 664 platform_bus_add_all_fdt_nodes(machine->fdt, "/platic", 665 VIRT_PLATFORM_BUS_BASEADDRESS, 666 VIRT_PLATFORM_BUS_SIZE, 667 VIRT_PLATFORM_BUS_IRQ); 668 669 /* 670 * Since lowmem region starts from 0 and Linux kernel legacy start address 671 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer 672 * access. FDT size limit with 1 MiB. 673 * Put the FDT into the memory map as a ROM image: this will ensure 674 * the FDT is copied again upon reset, even if addr points into RAM. 675 */ 676 qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size); 677 rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE, 678 &address_space_memory); 679 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 680 rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size)); 681 } 682 683 static void virt_done(Notifier *notifier, void *data) 684 { 685 LoongArchVirtMachineState *lvms = container_of(notifier, 686 LoongArchVirtMachineState, machine_done); 687 virt_build_smbios(lvms); 688 loongarch_acpi_setup(lvms); 689 virt_fdt_setup(lvms); 690 } 691 692 static void virt_powerdown_req(Notifier *notifier, void *opaque) 693 { 694 LoongArchVirtMachineState *s; 695 696 s = container_of(notifier, LoongArchVirtMachineState, powerdown_notifier); 697 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 698 } 699 700 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 701 { 702 /* Ensure there are no duplicate entries. */ 703 for (unsigned i = 0; i < memmap_entries; i++) { 704 assert(memmap_table[i].address != address); 705 } 706 707 memmap_table = g_renew(struct memmap_entry, memmap_table, 708 memmap_entries + 1); 709 memmap_table[memmap_entries].address = cpu_to_le64(address); 710 memmap_table[memmap_entries].length = cpu_to_le64(length); 711 memmap_table[memmap_entries].type = cpu_to_le32(type); 712 memmap_table[memmap_entries].reserved = 0; 713 memmap_entries++; 714 } 715 716 static DeviceState *create_acpi_ged(DeviceState *pch_pic, 717 LoongArchVirtMachineState *lvms) 718 { 719 DeviceState *dev; 720 MachineState *ms = MACHINE(lvms); 721 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 722 723 if (ms->ram_slots) { 724 event |= ACPI_GED_MEM_HOTPLUG_EVT; 725 } 726 dev = qdev_new(TYPE_ACPI_GED); 727 qdev_prop_set_uint32(dev, "ged-event", event); 728 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 729 730 /* ged event */ 731 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 732 /* memory hotplug */ 733 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 734 /* ged regs used for reset and power down */ 735 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 736 737 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 738 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 739 return dev; 740 } 741 742 static DeviceState *create_platform_bus(DeviceState *pch_pic) 743 { 744 DeviceState *dev; 745 SysBusDevice *sysbus; 746 int i, irq; 747 MemoryRegion *sysmem = get_system_memory(); 748 749 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 750 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 751 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 752 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 753 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 754 755 sysbus = SYS_BUS_DEVICE(dev); 756 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 757 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 758 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 759 } 760 761 memory_region_add_subregion(sysmem, 762 VIRT_PLATFORM_BUS_BASEADDRESS, 763 sysbus_mmio_get_region(sysbus, 0)); 764 return dev; 765 } 766 767 static void virt_devices_init(DeviceState *pch_pic, 768 LoongArchVirtMachineState *lvms) 769 { 770 MachineClass *mc = MACHINE_GET_CLASS(lvms); 771 DeviceState *gpex_dev; 772 SysBusDevice *d; 773 PCIBus *pci_bus; 774 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 775 MemoryRegion *mmio_alias, *mmio_reg; 776 int i; 777 778 gpex_dev = qdev_new(TYPE_GPEX_HOST); 779 d = SYS_BUS_DEVICE(gpex_dev); 780 sysbus_realize_and_unref(d, &error_fatal); 781 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 782 lvms->pci_bus = pci_bus; 783 784 /* Map only part size_ecam bytes of ECAM space */ 785 ecam_alias = g_new0(MemoryRegion, 1); 786 ecam_reg = sysbus_mmio_get_region(d, 0); 787 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 788 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 789 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 790 ecam_alias); 791 792 /* Map PCI mem space */ 793 mmio_alias = g_new0(MemoryRegion, 1); 794 mmio_reg = sysbus_mmio_get_region(d, 1); 795 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 796 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 797 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 798 mmio_alias); 799 800 /* Map PCI IO port space. */ 801 pio_alias = g_new0(MemoryRegion, 1); 802 pio_reg = sysbus_mmio_get_region(d, 2); 803 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 804 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 805 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 806 pio_alias); 807 808 for (i = 0; i < PCI_NUM_PINS; i++) { 809 sysbus_connect_irq(d, i, 810 qdev_get_gpio_in(pch_pic, 16 + i)); 811 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 812 } 813 814 /* 815 * Create uart fdt node in reverse order so that they appear 816 * in the finished device tree lowest address first 817 */ 818 for (i = VIRT_UART_COUNT; i --> 0;) { 819 hwaddr base = VIRT_UART_BASE + i * VIRT_UART_SIZE; 820 int irq = VIRT_UART_IRQ + i - VIRT_GSI_BASE; 821 serial_mm_init(get_system_memory(), base, 0, 822 qdev_get_gpio_in(pch_pic, irq), 823 115200, serial_hd(i), DEVICE_LITTLE_ENDIAN); 824 } 825 826 /* Network init */ 827 pci_init_nic_devices(pci_bus, mc->default_nic); 828 829 /* 830 * There are some invalid guest memory access. 831 * Create some unimplemented devices to emulate this. 832 */ 833 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 834 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 835 qdev_get_gpio_in(pch_pic, 836 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 837 838 /* acpi ged */ 839 lvms->acpi_ged = create_acpi_ged(pch_pic, lvms); 840 /* platform bus */ 841 lvms->platform_bus_dev = create_platform_bus(pch_pic); 842 } 843 844 static void virt_irq_init(LoongArchVirtMachineState *lvms) 845 { 846 MachineState *ms = MACHINE(lvms); 847 DeviceState *pch_pic, *pch_msi, *cpudev; 848 DeviceState *ipi, *extioi; 849 SysBusDevice *d; 850 LoongArchCPU *lacpu; 851 CPULoongArchState *env; 852 CPUState *cpu_state; 853 int cpu, pin, i, start, num; 854 855 /* 856 * Extended IRQ model. 857 * | 858 * +-----------+ +-------------|--------+ +-----------+ 859 * | IPI/Timer | --> | CPUINTC(0-3)|(4-255) | <-- | IPI/Timer | 860 * +-----------+ +-------------|--------+ +-----------+ 861 * ^ | 862 * | 863 * +---------+ 864 * | EIOINTC | 865 * +---------+ 866 * ^ ^ 867 * | | 868 * +---------+ +---------+ 869 * | PCH-PIC | | PCH-MSI | 870 * +---------+ +---------+ 871 * ^ ^ ^ 872 * | | | 873 * +--------+ +---------+ +---------+ 874 * | UARTs | | Devices | | Devices | 875 * +--------+ +---------+ +---------+ 876 * 877 * Virt extended IRQ model. 878 * 879 * +-----+ +---------------+ +-------+ 880 * | IPI |--> | CPUINTC(0-255)| <-- | Timer | 881 * +-----+ +---------------+ +-------+ 882 * ^ 883 * | 884 * +-----------+ 885 * | V-EIOINTC | 886 * +-----------+ 887 * ^ ^ 888 * | | 889 * +---------+ +---------+ 890 * | PCH-PIC | | PCH-MSI | 891 * +---------+ +---------+ 892 * ^ ^ ^ 893 * | | | 894 * +--------+ +---------+ +---------+ 895 * | UARTs | | Devices | | Devices | 896 * +--------+ +---------+ +---------+ 897 */ 898 899 /* Create IPI device */ 900 ipi = qdev_new(TYPE_LOONGARCH_IPI); 901 qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); 902 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 903 904 /* IPI iocsr memory region */ 905 memory_region_add_subregion(&lvms->system_iocsr, SMP_IPI_MAILBOX, 906 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); 907 memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR, 908 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); 909 910 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 911 cpu_state = qemu_get_cpu(cpu); 912 cpudev = DEVICE(cpu_state); 913 lacpu = LOONGARCH_CPU(cpu_state); 914 env = &(lacpu->env); 915 env->address_space_iocsr = &lvms->as_iocsr; 916 917 /* connect ipi irq to cpu irq */ 918 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); 919 env->ipistate = ipi; 920 } 921 922 /* Create EXTIOI device */ 923 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 924 qdev_prop_set_uint32(extioi, "num-cpu", ms->smp.cpus); 925 if (virt_is_veiointc_enabled(lvms)) { 926 qdev_prop_set_bit(extioi, "has-virtualization-extension", true); 927 } 928 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 929 memory_region_add_subregion(&lvms->system_iocsr, APIC_BASE, 930 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); 931 if (virt_is_veiointc_enabled(lvms)) { 932 memory_region_add_subregion(&lvms->system_iocsr, EXTIOI_VIRT_BASE, 933 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 1)); 934 } 935 936 /* 937 * connect ext irq to the cpu irq 938 * cpu_pin[9:2] <= intc_pin[7:0] 939 */ 940 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 941 cpudev = DEVICE(qemu_get_cpu(cpu)); 942 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 943 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 944 qdev_get_gpio_in(cpudev, pin + 2)); 945 } 946 } 947 948 pch_pic = qdev_new(TYPE_LOONGARCH_PIC); 949 num = VIRT_PCH_PIC_IRQ_NUM; 950 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 951 d = SYS_BUS_DEVICE(pch_pic); 952 sysbus_realize_and_unref(d, &error_fatal); 953 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 954 sysbus_mmio_get_region(d, 0)); 955 memory_region_add_subregion(get_system_memory(), 956 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 957 sysbus_mmio_get_region(d, 1)); 958 memory_region_add_subregion(get_system_memory(), 959 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 960 sysbus_mmio_get_region(d, 2)); 961 962 /* Connect pch_pic irqs to extioi */ 963 for (i = 0; i < num; i++) { 964 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 965 } 966 967 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 968 start = num; 969 num = EXTIOI_IRQS - start; 970 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 971 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 972 d = SYS_BUS_DEVICE(pch_msi); 973 sysbus_realize_and_unref(d, &error_fatal); 974 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 975 for (i = 0; i < num; i++) { 976 /* Connect pch_msi irqs to extioi */ 977 qdev_connect_gpio_out(DEVICE(d), i, 978 qdev_get_gpio_in(extioi, i + start)); 979 } 980 981 virt_devices_init(pch_pic, lvms); 982 } 983 984 static void virt_firmware_init(LoongArchVirtMachineState *lvms) 985 { 986 char *filename = MACHINE(lvms)->firmware; 987 char *bios_name = NULL; 988 int bios_size, i; 989 BlockBackend *pflash_blk0; 990 MemoryRegion *mr; 991 992 lvms->bios_loaded = false; 993 994 /* Map legacy -drive if=pflash to machine properties */ 995 for (i = 0; i < ARRAY_SIZE(lvms->flash); i++) { 996 pflash_cfi01_legacy_drive(lvms->flash[i], 997 drive_get(IF_PFLASH, 0, i)); 998 } 999 1000 virt_flash_map(lvms, get_system_memory()); 1001 1002 pflash_blk0 = pflash_cfi01_get_blk(lvms->flash[0]); 1003 1004 if (pflash_blk0) { 1005 if (filename) { 1006 error_report("cannot use both '-bios' and '-drive if=pflash'" 1007 "options at once"); 1008 exit(1); 1009 } 1010 lvms->bios_loaded = true; 1011 return; 1012 } 1013 1014 if (filename) { 1015 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 1016 if (!bios_name) { 1017 error_report("Could not find ROM image '%s'", filename); 1018 exit(1); 1019 } 1020 1021 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lvms->flash[0]), 0); 1022 bios_size = load_image_mr(bios_name, mr); 1023 if (bios_size < 0) { 1024 error_report("Could not load ROM image '%s'", bios_name); 1025 exit(1); 1026 } 1027 g_free(bios_name); 1028 lvms->bios_loaded = true; 1029 } 1030 } 1031 1032 static MemTxResult virt_iocsr_misc_write(void *opaque, hwaddr addr, 1033 uint64_t val, unsigned size, 1034 MemTxAttrs attrs) 1035 { 1036 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(opaque); 1037 uint64_t features; 1038 1039 switch (addr) { 1040 case MISC_FUNC_REG: 1041 if (!virt_is_veiointc_enabled(lvms)) { 1042 return MEMTX_OK; 1043 } 1044 1045 features = address_space_ldl(&lvms->as_iocsr, 1046 EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, 1047 attrs, NULL); 1048 if (val & BIT_ULL(IOCSRM_EXTIOI_EN)) { 1049 features |= BIT(EXTIOI_ENABLE); 1050 } 1051 if (val & BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE)) { 1052 features |= BIT(EXTIOI_ENABLE_INT_ENCODE); 1053 } 1054 1055 address_space_stl(&lvms->as_iocsr, 1056 EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, 1057 features, attrs, NULL); 1058 break; 1059 default: 1060 g_assert_not_reached(); 1061 } 1062 1063 return MEMTX_OK; 1064 } 1065 1066 static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr, 1067 uint64_t *data, 1068 unsigned size, MemTxAttrs attrs) 1069 { 1070 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(opaque); 1071 uint64_t ret = 0; 1072 int features; 1073 1074 switch (addr) { 1075 case VERSION_REG: 1076 ret = 0x11ULL; 1077 break; 1078 case FEATURE_REG: 1079 ret = BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); 1080 if (kvm_enabled()) { 1081 ret |= BIT(IOCSRF_VM); 1082 } 1083 break; 1084 case VENDOR_REG: 1085 ret = 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 1086 break; 1087 case CPUNAME_REG: 1088 ret = 0x303030354133ULL; /* "3A5000" */ 1089 break; 1090 case MISC_FUNC_REG: 1091 if (!virt_is_veiointc_enabled(lvms)) { 1092 ret |= BIT_ULL(IOCSRM_EXTIOI_EN); 1093 break; 1094 } 1095 1096 features = address_space_ldl(&lvms->as_iocsr, 1097 EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, 1098 attrs, NULL); 1099 if (features & BIT(EXTIOI_ENABLE)) { 1100 ret |= BIT_ULL(IOCSRM_EXTIOI_EN); 1101 } 1102 if (features & BIT(EXTIOI_ENABLE_INT_ENCODE)) { 1103 ret |= BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE); 1104 } 1105 break; 1106 default: 1107 g_assert_not_reached(); 1108 } 1109 1110 *data = ret; 1111 return MEMTX_OK; 1112 } 1113 1114 static const MemoryRegionOps virt_iocsr_misc_ops = { 1115 .read_with_attrs = virt_iocsr_misc_read, 1116 .write_with_attrs = virt_iocsr_misc_write, 1117 .endianness = DEVICE_LITTLE_ENDIAN, 1118 .valid = { 1119 .min_access_size = 4, 1120 .max_access_size = 8, 1121 }, 1122 .impl = { 1123 .min_access_size = 8, 1124 .max_access_size = 8, 1125 }, 1126 }; 1127 1128 static void fw_cfg_add_memory(MachineState *ms) 1129 { 1130 hwaddr base, size, ram_size, gap; 1131 int nb_numa_nodes, nodes; 1132 NodeInfo *numa_info; 1133 1134 ram_size = ms->ram_size; 1135 base = VIRT_LOWMEM_BASE; 1136 gap = VIRT_LOWMEM_SIZE; 1137 nodes = nb_numa_nodes = ms->numa_state->num_nodes; 1138 numa_info = ms->numa_state->nodes; 1139 if (!nodes) { 1140 nodes = 1; 1141 } 1142 1143 /* add fw_cfg memory map of node0 */ 1144 if (nb_numa_nodes) { 1145 size = numa_info[0].node_mem; 1146 } else { 1147 size = ram_size; 1148 } 1149 1150 if (size >= gap) { 1151 memmap_add_entry(base, gap, 1); 1152 size -= gap; 1153 base = VIRT_HIGHMEM_BASE; 1154 } 1155 1156 if (size) { 1157 memmap_add_entry(base, size, 1); 1158 base += size; 1159 } 1160 1161 if (nodes < 2) { 1162 return; 1163 } 1164 1165 /* add fw_cfg memory map of other nodes */ 1166 if (numa_info[0].node_mem < gap && ram_size > gap) { 1167 /* 1168 * memory map for the maining nodes splited into two part 1169 * lowram: [base, +(gap - numa_info[0].node_mem)) 1170 * highram: [VIRT_HIGHMEM_BASE, +(ram_size - gap)) 1171 */ 1172 memmap_add_entry(base, gap - numa_info[0].node_mem, 1); 1173 size = ram_size - gap; 1174 base = VIRT_HIGHMEM_BASE; 1175 } else { 1176 size = ram_size - numa_info[0].node_mem; 1177 } 1178 1179 if (size) 1180 memmap_add_entry(base, size, 1); 1181 } 1182 1183 static void virt_init(MachineState *machine) 1184 { 1185 LoongArchCPU *lacpu; 1186 const char *cpu_model = machine->cpu_type; 1187 MemoryRegion *address_space_mem = get_system_memory(); 1188 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine); 1189 int i; 1190 hwaddr base, size, ram_size = machine->ram_size; 1191 const CPUArchIdList *possible_cpus; 1192 MachineClass *mc = MACHINE_GET_CLASS(machine); 1193 CPUState *cpu; 1194 1195 if (!cpu_model) { 1196 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 1197 } 1198 1199 /* Create IOCSR space */ 1200 memory_region_init_io(&lvms->system_iocsr, OBJECT(machine), NULL, 1201 machine, "iocsr", UINT64_MAX); 1202 address_space_init(&lvms->as_iocsr, &lvms->system_iocsr, "IOCSR"); 1203 memory_region_init_io(&lvms->iocsr_mem, OBJECT(machine), 1204 &virt_iocsr_misc_ops, 1205 machine, "iocsr_misc", 0x428); 1206 memory_region_add_subregion(&lvms->system_iocsr, 0, &lvms->iocsr_mem); 1207 1208 /* Init CPUs */ 1209 possible_cpus = mc->possible_cpu_arch_ids(machine); 1210 for (i = 0; i < possible_cpus->len; i++) { 1211 cpu = cpu_create(machine->cpu_type); 1212 cpu->cpu_index = i; 1213 machine->possible_cpus->cpus[i].cpu = cpu; 1214 lacpu = LOONGARCH_CPU(cpu); 1215 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; 1216 } 1217 fw_cfg_add_memory(machine); 1218 1219 /* Node0 memory */ 1220 size = ram_size; 1221 base = VIRT_LOWMEM_BASE; 1222 if (size > VIRT_LOWMEM_SIZE) { 1223 size = VIRT_LOWMEM_SIZE; 1224 } 1225 1226 memory_region_init_alias(&lvms->lowmem, NULL, "loongarch.lowram", 1227 machine->ram, base, size); 1228 memory_region_add_subregion(address_space_mem, base, &lvms->lowmem); 1229 base += size; 1230 if (ram_size - size) { 1231 base = VIRT_HIGHMEM_BASE; 1232 memory_region_init_alias(&lvms->highmem, NULL, "loongarch.highram", 1233 machine->ram, VIRT_LOWMEM_BASE + size, ram_size - size); 1234 memory_region_add_subregion(address_space_mem, base, &lvms->highmem); 1235 base += ram_size - size; 1236 } 1237 1238 /* initialize device memory address space */ 1239 if (machine->ram_size < machine->maxram_size) { 1240 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 1241 1242 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1243 error_report("unsupported amount of memory slots: %"PRIu64, 1244 machine->ram_slots); 1245 exit(EXIT_FAILURE); 1246 } 1247 1248 if (QEMU_ALIGN_UP(machine->maxram_size, 1249 TARGET_PAGE_SIZE) != machine->maxram_size) { 1250 error_report("maximum memory size must by aligned to multiple of " 1251 "%d bytes", TARGET_PAGE_SIZE); 1252 exit(EXIT_FAILURE); 1253 } 1254 machine_memory_devices_init(machine, base, device_mem_size); 1255 } 1256 1257 /* load the BIOS image. */ 1258 virt_firmware_init(lvms); 1259 1260 /* fw_cfg init */ 1261 lvms->fw_cfg = virt_fw_cfg_init(ram_size, machine); 1262 rom_set_fw(lvms->fw_cfg); 1263 if (lvms->fw_cfg != NULL) { 1264 fw_cfg_add_file(lvms->fw_cfg, "etc/memmap", 1265 memmap_table, 1266 sizeof(struct memmap_entry) * (memmap_entries)); 1267 } 1268 1269 /* Initialize the IO interrupt subsystem */ 1270 virt_irq_init(lvms); 1271 lvms->machine_done.notify = virt_done; 1272 qemu_add_machine_init_done_notifier(&lvms->machine_done); 1273 /* connect powerdown request */ 1274 lvms->powerdown_notifier.notify = virt_powerdown_req; 1275 qemu_register_powerdown_notifier(&lvms->powerdown_notifier); 1276 1277 lvms->bootinfo.ram_size = ram_size; 1278 loongarch_load_kernel(machine, &lvms->bootinfo); 1279 } 1280 1281 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1282 void *opaque, Error **errp) 1283 { 1284 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 1285 OnOffAuto acpi = lvms->acpi; 1286 1287 visit_type_OnOffAuto(v, name, &acpi, errp); 1288 } 1289 1290 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1291 void *opaque, Error **errp) 1292 { 1293 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 1294 1295 visit_type_OnOffAuto(v, name, &lvms->acpi, errp); 1296 } 1297 1298 static void virt_initfn(Object *obj) 1299 { 1300 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 1301 1302 if (tcg_enabled()) { 1303 lvms->veiointc = ON_OFF_AUTO_OFF; 1304 } 1305 lvms->acpi = ON_OFF_AUTO_AUTO; 1306 lvms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1307 lvms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1308 virt_flash_create(lvms); 1309 } 1310 1311 static bool memhp_type_supported(DeviceState *dev) 1312 { 1313 /* we only support pc dimm now */ 1314 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 1315 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1316 } 1317 1318 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1319 Error **errp) 1320 { 1321 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 1322 } 1323 1324 static void virt_device_pre_plug(HotplugHandler *hotplug_dev, 1325 DeviceState *dev, Error **errp) 1326 { 1327 if (memhp_type_supported(dev)) { 1328 virt_mem_pre_plug(hotplug_dev, dev, errp); 1329 } 1330 } 1331 1332 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 1333 DeviceState *dev, Error **errp) 1334 { 1335 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 1336 1337 /* the acpi ged is always exist */ 1338 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lvms->acpi_ged), dev, 1339 errp); 1340 } 1341 1342 static void virt_device_unplug_request(HotplugHandler *hotplug_dev, 1343 DeviceState *dev, Error **errp) 1344 { 1345 if (memhp_type_supported(dev)) { 1346 virt_mem_unplug_request(hotplug_dev, dev, errp); 1347 } 1348 } 1349 1350 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 1351 DeviceState *dev, Error **errp) 1352 { 1353 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 1354 1355 hotplug_handler_unplug(HOTPLUG_HANDLER(lvms->acpi_ged), dev, errp); 1356 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lvms)); 1357 qdev_unrealize(dev); 1358 } 1359 1360 static void virt_device_unplug(HotplugHandler *hotplug_dev, 1361 DeviceState *dev, Error **errp) 1362 { 1363 if (memhp_type_supported(dev)) { 1364 virt_mem_unplug(hotplug_dev, dev, errp); 1365 } 1366 } 1367 1368 static void virt_mem_plug(HotplugHandler *hotplug_dev, 1369 DeviceState *dev, Error **errp) 1370 { 1371 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 1372 1373 pc_dimm_plug(PC_DIMM(dev), MACHINE(lvms)); 1374 hotplug_handler_plug(HOTPLUG_HANDLER(lvms->acpi_ged), 1375 dev, &error_abort); 1376 } 1377 1378 static void virt_device_plug_cb(HotplugHandler *hotplug_dev, 1379 DeviceState *dev, Error **errp) 1380 { 1381 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 1382 MachineClass *mc = MACHINE_GET_CLASS(lvms); 1383 PlatformBusDevice *pbus; 1384 1385 if (device_is_dynamic_sysbus(mc, dev)) { 1386 if (lvms->platform_bus_dev) { 1387 pbus = PLATFORM_BUS_DEVICE(lvms->platform_bus_dev); 1388 platform_bus_link_device(pbus, SYS_BUS_DEVICE(dev)); 1389 } 1390 } else if (memhp_type_supported(dev)) { 1391 virt_mem_plug(hotplug_dev, dev, errp); 1392 } 1393 } 1394 1395 static HotplugHandler *virt_get_hotplug_handler(MachineState *machine, 1396 DeviceState *dev) 1397 { 1398 MachineClass *mc = MACHINE_GET_CLASS(machine); 1399 1400 if (device_is_dynamic_sysbus(mc, dev) || 1401 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1402 memhp_type_supported(dev)) { 1403 return HOTPLUG_HANDLER(machine); 1404 } 1405 return NULL; 1406 } 1407 1408 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1409 { 1410 int n; 1411 unsigned int max_cpus = ms->smp.max_cpus; 1412 1413 if (ms->possible_cpus) { 1414 assert(ms->possible_cpus->len == max_cpus); 1415 return ms->possible_cpus; 1416 } 1417 1418 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1419 sizeof(CPUArchId) * max_cpus); 1420 ms->possible_cpus->len = max_cpus; 1421 for (n = 0; n < ms->possible_cpus->len; n++) { 1422 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1423 ms->possible_cpus->cpus[n].arch_id = n; 1424 1425 ms->possible_cpus->cpus[n].props.has_socket_id = true; 1426 ms->possible_cpus->cpus[n].props.socket_id = 1427 n / (ms->smp.cores * ms->smp.threads); 1428 ms->possible_cpus->cpus[n].props.has_core_id = true; 1429 ms->possible_cpus->cpus[n].props.core_id = 1430 n / ms->smp.threads % ms->smp.cores; 1431 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1432 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 1433 } 1434 return ms->possible_cpus; 1435 } 1436 1437 static CpuInstanceProperties virt_cpu_index_to_props(MachineState *ms, 1438 unsigned cpu_index) 1439 { 1440 MachineClass *mc = MACHINE_GET_CLASS(ms); 1441 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1442 1443 assert(cpu_index < possible_cpus->len); 1444 return possible_cpus->cpus[cpu_index].props; 1445 } 1446 1447 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1448 { 1449 int64_t socket_id; 1450 1451 if (ms->numa_state->num_nodes) { 1452 socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 1453 return socket_id % ms->numa_state->num_nodes; 1454 } else { 1455 return 0; 1456 } 1457 } 1458 1459 static void virt_class_init(ObjectClass *oc, void *data) 1460 { 1461 MachineClass *mc = MACHINE_CLASS(oc); 1462 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1463 1464 mc->init = virt_init; 1465 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 1466 mc->default_ram_id = "loongarch.ram"; 1467 mc->desc = "QEMU LoongArch Virtual Machine"; 1468 mc->max_cpus = LOONGARCH_MAX_CPUS; 1469 mc->is_default = 1; 1470 mc->default_kernel_irqchip_split = false; 1471 mc->block_default_type = IF_VIRTIO; 1472 mc->default_boot_order = "c"; 1473 mc->no_cdrom = 1; 1474 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1475 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1476 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1477 mc->numa_mem_supported = true; 1478 mc->auto_enable_numa_with_memhp = true; 1479 mc->auto_enable_numa_with_memdev = true; 1480 mc->get_hotplug_handler = virt_get_hotplug_handler; 1481 mc->default_nic = "virtio-net-pci"; 1482 hc->plug = virt_device_plug_cb; 1483 hc->pre_plug = virt_device_pre_plug; 1484 hc->unplug_request = virt_device_unplug_request; 1485 hc->unplug = virt_device_unplug; 1486 1487 object_class_property_add(oc, "acpi", "OnOffAuto", 1488 virt_get_acpi, virt_set_acpi, 1489 NULL, NULL); 1490 object_class_property_set_description(oc, "acpi", 1491 "Enable ACPI"); 1492 object_class_property_add(oc, "v-eiointc", "OnOffAuto", 1493 virt_get_veiointc, virt_set_veiointc, 1494 NULL, NULL); 1495 object_class_property_set_description(oc, "v-eiointc", 1496 "Enable Virt Extend I/O Interrupt Controller."); 1497 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1498 #ifdef CONFIG_TPM 1499 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1500 #endif 1501 } 1502 1503 static const TypeInfo virt_machine_types[] = { 1504 { 1505 .name = TYPE_LOONGARCH_VIRT_MACHINE, 1506 .parent = TYPE_MACHINE, 1507 .instance_size = sizeof(LoongArchVirtMachineState), 1508 .class_init = virt_class_init, 1509 .instance_init = virt_initfn, 1510 .interfaces = (InterfaceInfo[]) { 1511 { TYPE_HOTPLUG_HANDLER }, 1512 { } 1513 }, 1514 } 1515 }; 1516 1517 DEFINE_TYPES(virt_machine_types) 1518