1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/sysemu.h" 14 #include "sysemu/qtest.h" 15 #include "sysemu/runstate.h" 16 #include "sysemu/reset.h" 17 #include "sysemu/rtc.h" 18 #include "hw/loongarch/virt.h" 19 #include "exec/address-spaces.h" 20 #include "hw/irq.h" 21 #include "net/net.h" 22 #include "hw/loader.h" 23 #include "elf.h" 24 #include "hw/intc/loongarch_ipi.h" 25 #include "hw/intc/loongarch_extioi.h" 26 #include "hw/intc/loongarch_pch_pic.h" 27 #include "hw/intc/loongarch_pch_msi.h" 28 #include "hw/pci-host/ls7a.h" 29 #include "hw/pci-host/gpex.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/loongarch/fw_cfg.h" 32 #include "target/loongarch/cpu.h" 33 #include "hw/firmware/smbios.h" 34 #include "hw/acpi/aml-build.h" 35 #include "qapi/qapi-visit-common.h" 36 #include "hw/acpi/generic_event_device.h" 37 #include "hw/mem/nvdimm.h" 38 #include "sysemu/device_tree.h" 39 #include <libfdt.h> 40 #include "hw/core/sysbus-fdt.h" 41 #include "hw/platform-bus.h" 42 #include "hw/display/ramfb.h" 43 #include "hw/mem/pc-dimm.h" 44 #include "sysemu/tpm.h" 45 #include "sysemu/block-backend.h" 46 #include "hw/block/flash.h" 47 #include "qemu/error-report.h" 48 49 static PFlashCFI01 *virt_flash_create1(LoongArchMachineState *lams, 50 const char *name, 51 const char *alias_prop_name) 52 { 53 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 54 55 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 56 qdev_prop_set_uint8(dev, "width", 4); 57 qdev_prop_set_uint8(dev, "device-width", 2); 58 qdev_prop_set_bit(dev, "big-endian", false); 59 qdev_prop_set_uint16(dev, "id0", 0x89); 60 qdev_prop_set_uint16(dev, "id1", 0x18); 61 qdev_prop_set_uint16(dev, "id2", 0x00); 62 qdev_prop_set_uint16(dev, "id3", 0x00); 63 qdev_prop_set_string(dev, "name", name); 64 object_property_add_child(OBJECT(lams), name, OBJECT(dev)); 65 object_property_add_alias(OBJECT(lams), alias_prop_name, 66 OBJECT(dev), "drive"); 67 return PFLASH_CFI01(dev); 68 } 69 70 static void virt_flash_create(LoongArchMachineState *lams) 71 { 72 lams->flash[0] = virt_flash_create1(lams, "virt.flash0", "pflash0"); 73 lams->flash[1] = virt_flash_create1(lams, "virt.flash1", "pflash1"); 74 } 75 76 static void virt_flash_map1(PFlashCFI01 *flash, 77 hwaddr base, hwaddr size, 78 MemoryRegion *sysmem) 79 { 80 DeviceState *dev = DEVICE(flash); 81 BlockBackend *blk; 82 hwaddr real_size = size; 83 84 blk = pflash_cfi01_get_blk(flash); 85 if (blk) { 86 real_size = blk_getlength(blk); 87 assert(real_size && real_size <= size); 88 } 89 90 assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE)); 91 assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 92 93 qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE); 94 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 95 memory_region_add_subregion(sysmem, base, 96 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 97 } 98 99 static void virt_flash_map(LoongArchMachineState *lams, 100 MemoryRegion *sysmem) 101 { 102 PFlashCFI01 *flash0 = lams->flash[0]; 103 PFlashCFI01 *flash1 = lams->flash[1]; 104 105 virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem); 106 virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem); 107 } 108 109 static void fdt_add_flash_node(LoongArchMachineState *lams) 110 { 111 MachineState *ms = MACHINE(lams); 112 char *nodename; 113 MemoryRegion *flash_mem; 114 115 hwaddr flash0_base; 116 hwaddr flash0_size; 117 118 hwaddr flash1_base; 119 hwaddr flash1_size; 120 121 flash_mem = pflash_cfi01_get_memory(lams->flash[0]); 122 flash0_base = flash_mem->addr; 123 flash0_size = memory_region_size(flash_mem); 124 125 flash_mem = pflash_cfi01_get_memory(lams->flash[1]); 126 flash1_base = flash_mem->addr; 127 flash1_size = memory_region_size(flash_mem); 128 129 nodename = g_strdup_printf("/flash@%" PRIx64, flash0_base); 130 qemu_fdt_add_subnode(ms->fdt, nodename); 131 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 132 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 133 2, flash0_base, 2, flash0_size, 134 2, flash1_base, 2, flash1_size); 135 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 136 g_free(nodename); 137 } 138 139 static void fdt_add_rtc_node(LoongArchMachineState *lams) 140 { 141 char *nodename; 142 hwaddr base = VIRT_RTC_REG_BASE; 143 hwaddr size = VIRT_RTC_LEN; 144 MachineState *ms = MACHINE(lams); 145 146 nodename = g_strdup_printf("/rtc@%" PRIx64, base); 147 qemu_fdt_add_subnode(ms->fdt, nodename); 148 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc"); 149 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 150 g_free(nodename); 151 } 152 153 static void fdt_add_uart_node(LoongArchMachineState *lams) 154 { 155 char *nodename; 156 hwaddr base = VIRT_UART_BASE; 157 hwaddr size = VIRT_UART_SIZE; 158 MachineState *ms = MACHINE(lams); 159 160 nodename = g_strdup_printf("/serial@%" PRIx64, base); 161 qemu_fdt_add_subnode(ms->fdt, nodename); 162 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); 163 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); 164 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); 165 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 166 g_free(nodename); 167 } 168 169 static void create_fdt(LoongArchMachineState *lams) 170 { 171 MachineState *ms = MACHINE(lams); 172 173 ms->fdt = create_device_tree(&lams->fdt_size); 174 if (!ms->fdt) { 175 error_report("create_device_tree() failed"); 176 exit(1); 177 } 178 179 /* Header */ 180 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 181 "linux,dummy-loongson3"); 182 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 183 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 184 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 185 } 186 187 static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) 188 { 189 int num; 190 const MachineState *ms = MACHINE(lams); 191 int smp_cpus = ms->smp.cpus; 192 193 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 194 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 195 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 196 197 /* cpu nodes */ 198 for (num = smp_cpus - 1; num >= 0; num--) { 199 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 200 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 201 CPUState *cs = CPU(cpu); 202 203 qemu_fdt_add_subnode(ms->fdt, nodename); 204 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 205 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 206 cpu->dtb_compatible); 207 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 208 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 209 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 210 } 211 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 212 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 213 qemu_fdt_alloc_phandle(ms->fdt)); 214 g_free(nodename); 215 } 216 217 /*cpu map */ 218 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 219 220 for (num = smp_cpus - 1; num >= 0; num--) { 221 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 222 char *map_path; 223 224 if (ms->smp.threads > 1) { 225 map_path = g_strdup_printf( 226 "/cpus/cpu-map/socket%d/core%d/thread%d", 227 num / (ms->smp.cores * ms->smp.threads), 228 (num / ms->smp.threads) % ms->smp.cores, 229 num % ms->smp.threads); 230 } else { 231 map_path = g_strdup_printf( 232 "/cpus/cpu-map/socket%d/core%d", 233 num / ms->smp.cores, 234 num % ms->smp.cores); 235 } 236 qemu_fdt_add_path(ms->fdt, map_path); 237 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 238 239 g_free(map_path); 240 g_free(cpu_path); 241 } 242 } 243 244 static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) 245 { 246 char *nodename; 247 hwaddr base = VIRT_FWCFG_BASE; 248 const MachineState *ms = MACHINE(lams); 249 250 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 251 qemu_fdt_add_subnode(ms->fdt, nodename); 252 qemu_fdt_setprop_string(ms->fdt, nodename, 253 "compatible", "qemu,fw-cfg-mmio"); 254 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 255 2, base, 2, 0x18); 256 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 257 g_free(nodename); 258 } 259 260 static void fdt_add_pcie_node(const LoongArchMachineState *lams) 261 { 262 char *nodename; 263 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 264 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 265 hwaddr base_pio = VIRT_PCI_IO_BASE; 266 hwaddr size_pio = VIRT_PCI_IO_SIZE; 267 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 268 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 269 hwaddr base = base_pcie; 270 271 const MachineState *ms = MACHINE(lams); 272 273 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 274 qemu_fdt_add_subnode(ms->fdt, nodename); 275 qemu_fdt_setprop_string(ms->fdt, nodename, 276 "compatible", "pci-host-ecam-generic"); 277 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 278 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 279 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 280 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 281 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 282 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 283 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 284 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 285 2, base_pcie, 2, size_pcie); 286 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 287 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 288 2, base_pio, 2, size_pio, 289 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 290 2, base_mmio, 2, size_mmio); 291 g_free(nodename); 292 } 293 294 static void fdt_add_irqchip_node(LoongArchMachineState *lams) 295 { 296 MachineState *ms = MACHINE(lams); 297 char *nodename; 298 uint32_t irqchip_phandle; 299 300 irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt); 301 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle); 302 303 nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE); 304 qemu_fdt_add_subnode(ms->fdt, nodename); 305 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 306 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 307 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 308 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 309 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 310 311 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 312 "loongarch,ls7a"); 313 314 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 315 2, VIRT_IOAPIC_REG_BASE, 316 2, PCH_PIC_ROUTE_ENTRY_OFFSET); 317 318 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle); 319 g_free(nodename); 320 } 321 322 static void fdt_add_memory_node(MachineState *ms, 323 uint64_t base, uint64_t size, int node_id) 324 { 325 char *nodename = g_strdup_printf("/memory@%" PRIx64, base); 326 327 qemu_fdt_add_subnode(ms->fdt, nodename); 328 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 329 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 330 331 if (ms->numa_state && ms->numa_state->num_nodes) { 332 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); 333 } 334 335 g_free(nodename); 336 } 337 338 static void virt_build_smbios(LoongArchMachineState *lams) 339 { 340 MachineState *ms = MACHINE(lams); 341 MachineClass *mc = MACHINE_GET_CLASS(lams); 342 uint8_t *smbios_tables, *smbios_anchor; 343 size_t smbios_tables_len, smbios_anchor_len; 344 const char *product = "QEMU Virtual Machine"; 345 346 if (!lams->fw_cfg) { 347 return; 348 } 349 350 smbios_set_defaults("QEMU", product, mc->name, true); 351 352 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 353 NULL, 0, 354 &smbios_tables, &smbios_tables_len, 355 &smbios_anchor, &smbios_anchor_len, &error_fatal); 356 357 if (smbios_anchor) { 358 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", 359 smbios_tables, smbios_tables_len); 360 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", 361 smbios_anchor, smbios_anchor_len); 362 } 363 } 364 365 static void virt_machine_done(Notifier *notifier, void *data) 366 { 367 LoongArchMachineState *lams = container_of(notifier, 368 LoongArchMachineState, machine_done); 369 virt_build_smbios(lams); 370 loongarch_acpi_setup(lams); 371 } 372 373 static void virt_powerdown_req(Notifier *notifier, void *opaque) 374 { 375 LoongArchMachineState *s = container_of(notifier, 376 LoongArchMachineState, powerdown_notifier); 377 378 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 379 } 380 381 struct memmap_entry { 382 uint64_t address; 383 uint64_t length; 384 uint32_t type; 385 uint32_t reserved; 386 }; 387 388 static struct memmap_entry *memmap_table; 389 static unsigned memmap_entries; 390 391 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 392 { 393 /* Ensure there are no duplicate entries. */ 394 for (unsigned i = 0; i < memmap_entries; i++) { 395 assert(memmap_table[i].address != address); 396 } 397 398 memmap_table = g_renew(struct memmap_entry, memmap_table, 399 memmap_entries + 1); 400 memmap_table[memmap_entries].address = cpu_to_le64(address); 401 memmap_table[memmap_entries].length = cpu_to_le64(length); 402 memmap_table[memmap_entries].type = cpu_to_le32(type); 403 memmap_table[memmap_entries].reserved = 0; 404 memmap_entries++; 405 } 406 407 static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams) 408 { 409 DeviceState *dev; 410 MachineState *ms = MACHINE(lams); 411 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 412 413 if (ms->ram_slots) { 414 event |= ACPI_GED_MEM_HOTPLUG_EVT; 415 } 416 dev = qdev_new(TYPE_ACPI_GED); 417 qdev_prop_set_uint32(dev, "ged-event", event); 418 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 419 420 /* ged event */ 421 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 422 /* memory hotplug */ 423 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 424 /* ged regs used for reset and power down */ 425 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 426 427 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 428 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 429 return dev; 430 } 431 432 static DeviceState *create_platform_bus(DeviceState *pch_pic) 433 { 434 DeviceState *dev; 435 SysBusDevice *sysbus; 436 int i, irq; 437 MemoryRegion *sysmem = get_system_memory(); 438 439 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 440 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 441 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 442 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 443 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 444 445 sysbus = SYS_BUS_DEVICE(dev); 446 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 447 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 448 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 449 } 450 451 memory_region_add_subregion(sysmem, 452 VIRT_PLATFORM_BUS_BASEADDRESS, 453 sysbus_mmio_get_region(sysbus, 0)); 454 return dev; 455 } 456 457 static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams) 458 { 459 MachineClass *mc = MACHINE_GET_CLASS(lams); 460 DeviceState *gpex_dev; 461 SysBusDevice *d; 462 PCIBus *pci_bus; 463 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 464 MemoryRegion *mmio_alias, *mmio_reg; 465 int i; 466 467 gpex_dev = qdev_new(TYPE_GPEX_HOST); 468 d = SYS_BUS_DEVICE(gpex_dev); 469 sysbus_realize_and_unref(d, &error_fatal); 470 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 471 lams->pci_bus = pci_bus; 472 473 /* Map only part size_ecam bytes of ECAM space */ 474 ecam_alias = g_new0(MemoryRegion, 1); 475 ecam_reg = sysbus_mmio_get_region(d, 0); 476 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 477 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 478 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 479 ecam_alias); 480 481 /* Map PCI mem space */ 482 mmio_alias = g_new0(MemoryRegion, 1); 483 mmio_reg = sysbus_mmio_get_region(d, 1); 484 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 485 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 486 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 487 mmio_alias); 488 489 /* Map PCI IO port space. */ 490 pio_alias = g_new0(MemoryRegion, 1); 491 pio_reg = sysbus_mmio_get_region(d, 2); 492 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 493 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 494 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 495 pio_alias); 496 497 for (i = 0; i < GPEX_NUM_IRQS; i++) { 498 sysbus_connect_irq(d, i, 499 qdev_get_gpio_in(pch_pic, 16 + i)); 500 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 501 } 502 503 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 504 qdev_get_gpio_in(pch_pic, 505 VIRT_UART_IRQ - VIRT_GSI_BASE), 506 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 507 fdt_add_uart_node(lams); 508 509 /* Network init */ 510 pci_init_nic_devices(pci_bus, mc->default_nic); 511 512 /* 513 * There are some invalid guest memory access. 514 * Create some unimplemented devices to emulate this. 515 */ 516 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 517 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 518 qdev_get_gpio_in(pch_pic, 519 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 520 fdt_add_rtc_node(lams); 521 522 /* acpi ged */ 523 lams->acpi_ged = create_acpi_ged(pch_pic, lams); 524 /* platform bus */ 525 lams->platform_bus_dev = create_platform_bus(pch_pic); 526 } 527 528 static void loongarch_irq_init(LoongArchMachineState *lams) 529 { 530 MachineState *ms = MACHINE(lams); 531 DeviceState *pch_pic, *pch_msi, *cpudev; 532 DeviceState *ipi, *extioi; 533 SysBusDevice *d; 534 LoongArchCPU *lacpu; 535 CPULoongArchState *env; 536 CPUState *cpu_state; 537 int cpu, pin, i, start, num; 538 539 /* 540 * The connection of interrupts: 541 * +-----+ +---------+ +-------+ 542 * | IPI |--> | CPUINTC | <-- | Timer | 543 * +-----+ +---------+ +-------+ 544 * ^ 545 * | 546 * +---------+ 547 * | EIOINTC | 548 * +---------+ 549 * ^ ^ 550 * | | 551 * +---------+ +---------+ 552 * | PCH-PIC | | PCH-MSI | 553 * +---------+ +---------+ 554 * ^ ^ ^ 555 * | | | 556 * +--------+ +---------+ +---------+ 557 * | UARTs | | Devices | | Devices | 558 * +--------+ +---------+ +---------+ 559 */ 560 561 /* Create IPI device */ 562 ipi = qdev_new(TYPE_LOONGARCH_IPI); 563 qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); 564 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 565 566 /* IPI iocsr memory region */ 567 memory_region_add_subregion(&lams->system_iocsr, SMP_IPI_MAILBOX, 568 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); 569 memory_region_add_subregion(&lams->system_iocsr, MAIL_SEND_ADDR, 570 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); 571 572 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 573 cpu_state = qemu_get_cpu(cpu); 574 cpudev = DEVICE(cpu_state); 575 lacpu = LOONGARCH_CPU(cpu_state); 576 env = &(lacpu->env); 577 env->address_space_iocsr = &lams->as_iocsr; 578 579 /* connect ipi irq to cpu irq */ 580 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); 581 env->ipistate = ipi; 582 } 583 584 /* Create EXTIOI device */ 585 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 586 qdev_prop_set_uint32(extioi, "num-cpu", ms->smp.cpus); 587 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 588 memory_region_add_subregion(&lams->system_iocsr, APIC_BASE, 589 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); 590 591 /* 592 * connect ext irq to the cpu irq 593 * cpu_pin[9:2] <= intc_pin[7:0] 594 */ 595 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 596 cpudev = DEVICE(qemu_get_cpu(cpu)); 597 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 598 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 599 qdev_get_gpio_in(cpudev, pin + 2)); 600 } 601 } 602 603 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 604 num = VIRT_PCH_PIC_IRQ_NUM; 605 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 606 d = SYS_BUS_DEVICE(pch_pic); 607 sysbus_realize_and_unref(d, &error_fatal); 608 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 609 sysbus_mmio_get_region(d, 0)); 610 memory_region_add_subregion(get_system_memory(), 611 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 612 sysbus_mmio_get_region(d, 1)); 613 memory_region_add_subregion(get_system_memory(), 614 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 615 sysbus_mmio_get_region(d, 2)); 616 617 /* Connect pch_pic irqs to extioi */ 618 for (i = 0; i < num; i++) { 619 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 620 } 621 622 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 623 start = num; 624 num = EXTIOI_IRQS - start; 625 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 626 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 627 d = SYS_BUS_DEVICE(pch_msi); 628 sysbus_realize_and_unref(d, &error_fatal); 629 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 630 for (i = 0; i < num; i++) { 631 /* Connect pch_msi irqs to extioi */ 632 qdev_connect_gpio_out(DEVICE(d), i, 633 qdev_get_gpio_in(extioi, i + start)); 634 } 635 636 loongarch_devices_init(pch_pic, lams); 637 } 638 639 static void loongarch_firmware_init(LoongArchMachineState *lams) 640 { 641 char *filename = MACHINE(lams)->firmware; 642 char *bios_name = NULL; 643 int bios_size, i; 644 BlockBackend *pflash_blk0; 645 MemoryRegion *mr; 646 647 lams->bios_loaded = false; 648 649 /* Map legacy -drive if=pflash to machine properties */ 650 for (i = 0; i < ARRAY_SIZE(lams->flash); i++) { 651 pflash_cfi01_legacy_drive(lams->flash[i], 652 drive_get(IF_PFLASH, 0, i)); 653 } 654 655 virt_flash_map(lams, get_system_memory()); 656 657 pflash_blk0 = pflash_cfi01_get_blk(lams->flash[0]); 658 659 if (pflash_blk0) { 660 if (filename) { 661 error_report("cannot use both '-bios' and '-drive if=pflash'" 662 "options at once"); 663 exit(1); 664 } 665 lams->bios_loaded = true; 666 return; 667 } 668 669 if (filename) { 670 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 671 if (!bios_name) { 672 error_report("Could not find ROM image '%s'", filename); 673 exit(1); 674 } 675 676 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lams->flash[0]), 0); 677 bios_size = load_image_mr(bios_name, mr); 678 if (bios_size < 0) { 679 error_report("Could not load ROM image '%s'", bios_name); 680 exit(1); 681 } 682 g_free(bios_name); 683 lams->bios_loaded = true; 684 } 685 } 686 687 688 static void loongarch_qemu_write(void *opaque, hwaddr addr, 689 uint64_t val, unsigned size) 690 { 691 } 692 693 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) 694 { 695 switch (addr) { 696 case VERSION_REG: 697 return 0x11ULL; 698 case FEATURE_REG: 699 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 700 1ULL << IOCSRF_CSRIPI; 701 case VENDOR_REG: 702 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 703 case CPUNAME_REG: 704 return 0x303030354133ULL; /* "3A5000" */ 705 case MISC_FUNC_REG: 706 return 1ULL << IOCSRM_EXTIOI_EN; 707 } 708 return 0ULL; 709 } 710 711 static const MemoryRegionOps loongarch_qemu_ops = { 712 .read = loongarch_qemu_read, 713 .write = loongarch_qemu_write, 714 .endianness = DEVICE_LITTLE_ENDIAN, 715 .valid = { 716 .min_access_size = 4, 717 .max_access_size = 8, 718 }, 719 .impl = { 720 .min_access_size = 8, 721 .max_access_size = 8, 722 }, 723 }; 724 725 static void loongarch_init(MachineState *machine) 726 { 727 LoongArchCPU *lacpu; 728 const char *cpu_model = machine->cpu_type; 729 ram_addr_t offset = 0; 730 ram_addr_t ram_size = machine->ram_size; 731 uint64_t highram_size = 0, phyAddr = 0; 732 MemoryRegion *address_space_mem = get_system_memory(); 733 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 734 int nb_numa_nodes = machine->numa_state->num_nodes; 735 NodeInfo *numa_info = machine->numa_state->nodes; 736 int i; 737 hwaddr fdt_base; 738 const CPUArchIdList *possible_cpus; 739 MachineClass *mc = MACHINE_GET_CLASS(machine); 740 CPUState *cpu; 741 char *ramName = NULL; 742 743 if (!cpu_model) { 744 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 745 } 746 747 if (ram_size < 1 * GiB) { 748 error_report("ram_size must be greater than 1G."); 749 exit(1); 750 } 751 create_fdt(lams); 752 753 /* Create IOCSR space */ 754 memory_region_init_io(&lams->system_iocsr, OBJECT(machine), NULL, 755 machine, "iocsr", UINT64_MAX); 756 address_space_init(&lams->as_iocsr, &lams->system_iocsr, "IOCSR"); 757 memory_region_init_io(&lams->iocsr_mem, OBJECT(machine), 758 &loongarch_qemu_ops, 759 machine, "iocsr_misc", 0x428); 760 memory_region_add_subregion(&lams->system_iocsr, 0, &lams->iocsr_mem); 761 762 /* Init CPUs */ 763 possible_cpus = mc->possible_cpu_arch_ids(machine); 764 for (i = 0; i < possible_cpus->len; i++) { 765 cpu = cpu_create(machine->cpu_type); 766 cpu->cpu_index = i; 767 machine->possible_cpus->cpus[i].cpu = cpu; 768 lacpu = LOONGARCH_CPU(cpu); 769 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; 770 } 771 fdt_add_cpu_nodes(lams); 772 773 /* Node0 memory */ 774 memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1); 775 fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0); 776 memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram", 777 machine->ram, offset, VIRT_LOWMEM_SIZE); 778 memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem); 779 780 offset += VIRT_LOWMEM_SIZE; 781 if (nb_numa_nodes > 0) { 782 assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE); 783 highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE; 784 } else { 785 highram_size = ram_size - VIRT_LOWMEM_SIZE; 786 } 787 phyAddr = VIRT_HIGHMEM_BASE; 788 memmap_add_entry(phyAddr, highram_size, 1); 789 fdt_add_memory_node(machine, phyAddr, highram_size, 0); 790 memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram", 791 machine->ram, offset, highram_size); 792 memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem); 793 794 /* Node1 - Nodemax memory */ 795 offset += highram_size; 796 phyAddr += highram_size; 797 798 for (i = 1; i < nb_numa_nodes; i++) { 799 MemoryRegion *nodemem = g_new(MemoryRegion, 1); 800 ramName = g_strdup_printf("loongarch.node%d.ram", i); 801 memory_region_init_alias(nodemem, NULL, ramName, machine->ram, 802 offset, numa_info[i].node_mem); 803 memory_region_add_subregion(address_space_mem, phyAddr, nodemem); 804 memmap_add_entry(phyAddr, numa_info[i].node_mem, 1); 805 fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i); 806 offset += numa_info[i].node_mem; 807 phyAddr += numa_info[i].node_mem; 808 } 809 810 /* initialize device memory address space */ 811 if (machine->ram_size < machine->maxram_size) { 812 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 813 hwaddr device_mem_base; 814 815 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 816 error_report("unsupported amount of memory slots: %"PRIu64, 817 machine->ram_slots); 818 exit(EXIT_FAILURE); 819 } 820 821 if (QEMU_ALIGN_UP(machine->maxram_size, 822 TARGET_PAGE_SIZE) != machine->maxram_size) { 823 error_report("maximum memory size must by aligned to multiple of " 824 "%d bytes", TARGET_PAGE_SIZE); 825 exit(EXIT_FAILURE); 826 } 827 /* device memory base is the top of high memory address. */ 828 device_mem_base = ROUND_UP(VIRT_HIGHMEM_BASE + highram_size, 1 * GiB); 829 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 830 } 831 832 /* load the BIOS image. */ 833 loongarch_firmware_init(lams); 834 835 /* fw_cfg init */ 836 lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine); 837 rom_set_fw(lams->fw_cfg); 838 if (lams->fw_cfg != NULL) { 839 fw_cfg_add_file(lams->fw_cfg, "etc/memmap", 840 memmap_table, 841 sizeof(struct memmap_entry) * (memmap_entries)); 842 } 843 fdt_add_fw_cfg_node(lams); 844 fdt_add_flash_node(lams); 845 846 /* Initialize the IO interrupt subsystem */ 847 loongarch_irq_init(lams); 848 fdt_add_irqchip_node(lams); 849 platform_bus_add_all_fdt_nodes(machine->fdt, "/intc", 850 VIRT_PLATFORM_BUS_BASEADDRESS, 851 VIRT_PLATFORM_BUS_SIZE, 852 VIRT_PLATFORM_BUS_IRQ); 853 lams->machine_done.notify = virt_machine_done; 854 qemu_add_machine_init_done_notifier(&lams->machine_done); 855 /* connect powerdown request */ 856 lams->powerdown_notifier.notify = virt_powerdown_req; 857 qemu_register_powerdown_notifier(&lams->powerdown_notifier); 858 859 fdt_add_pcie_node(lams); 860 /* 861 * Since lowmem region starts from 0 and Linux kernel legacy start address 862 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer 863 * access. FDT size limit with 1 MiB. 864 * Put the FDT into the memory map as a ROM image: this will ensure 865 * the FDT is copied again upon reset, even if addr points into RAM. 866 */ 867 fdt_base = 1 * MiB; 868 qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size); 869 rom_add_blob_fixed_as("fdt", machine->fdt, lams->fdt_size, fdt_base, 870 &address_space_memory); 871 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 872 rom_ptr_for_as(&address_space_memory, fdt_base, lams->fdt_size)); 873 874 lams->bootinfo.ram_size = ram_size; 875 loongarch_load_kernel(machine, &lams->bootinfo); 876 } 877 878 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) 879 { 880 if (lams->acpi == ON_OFF_AUTO_OFF) { 881 return false; 882 } 883 return true; 884 } 885 886 static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, 887 void *opaque, Error **errp) 888 { 889 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 890 OnOffAuto acpi = lams->acpi; 891 892 visit_type_OnOffAuto(v, name, &acpi, errp); 893 } 894 895 static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, 896 void *opaque, Error **errp) 897 { 898 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 899 900 visit_type_OnOffAuto(v, name, &lams->acpi, errp); 901 } 902 903 static void loongarch_machine_initfn(Object *obj) 904 { 905 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 906 907 lams->acpi = ON_OFF_AUTO_AUTO; 908 lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 909 lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 910 virt_flash_create(lams); 911 } 912 913 static bool memhp_type_supported(DeviceState *dev) 914 { 915 /* we only support pc dimm now */ 916 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 917 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 918 } 919 920 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 921 Error **errp) 922 { 923 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 924 } 925 926 static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev, 927 DeviceState *dev, Error **errp) 928 { 929 if (memhp_type_supported(dev)) { 930 virt_mem_pre_plug(hotplug_dev, dev, errp); 931 } 932 } 933 934 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 935 DeviceState *dev, Error **errp) 936 { 937 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 938 939 /* the acpi ged is always exist */ 940 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lams->acpi_ged), dev, 941 errp); 942 } 943 944 static void virt_machine_device_unplug_request(HotplugHandler *hotplug_dev, 945 DeviceState *dev, Error **errp) 946 { 947 if (memhp_type_supported(dev)) { 948 virt_mem_unplug_request(hotplug_dev, dev, errp); 949 } 950 } 951 952 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 953 DeviceState *dev, Error **errp) 954 { 955 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 956 957 hotplug_handler_unplug(HOTPLUG_HANDLER(lams->acpi_ged), dev, errp); 958 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lams)); 959 qdev_unrealize(dev); 960 } 961 962 static void virt_machine_device_unplug(HotplugHandler *hotplug_dev, 963 DeviceState *dev, Error **errp) 964 { 965 if (memhp_type_supported(dev)) { 966 virt_mem_unplug(hotplug_dev, dev, errp); 967 } 968 } 969 970 static void virt_mem_plug(HotplugHandler *hotplug_dev, 971 DeviceState *dev, Error **errp) 972 { 973 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 974 975 pc_dimm_plug(PC_DIMM(dev), MACHINE(lams)); 976 hotplug_handler_plug(HOTPLUG_HANDLER(lams->acpi_ged), 977 dev, &error_abort); 978 } 979 980 static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev, 981 DeviceState *dev, Error **errp) 982 { 983 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 984 MachineClass *mc = MACHINE_GET_CLASS(lams); 985 986 if (device_is_dynamic_sysbus(mc, dev)) { 987 if (lams->platform_bus_dev) { 988 platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev), 989 SYS_BUS_DEVICE(dev)); 990 } 991 } else if (memhp_type_supported(dev)) { 992 virt_mem_plug(hotplug_dev, dev, errp); 993 } 994 } 995 996 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 997 DeviceState *dev) 998 { 999 MachineClass *mc = MACHINE_GET_CLASS(machine); 1000 1001 if (device_is_dynamic_sysbus(mc, dev) || 1002 memhp_type_supported(dev)) { 1003 return HOTPLUG_HANDLER(machine); 1004 } 1005 return NULL; 1006 } 1007 1008 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1009 { 1010 int n; 1011 unsigned int max_cpus = ms->smp.max_cpus; 1012 1013 if (ms->possible_cpus) { 1014 assert(ms->possible_cpus->len == max_cpus); 1015 return ms->possible_cpus; 1016 } 1017 1018 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1019 sizeof(CPUArchId) * max_cpus); 1020 ms->possible_cpus->len = max_cpus; 1021 for (n = 0; n < ms->possible_cpus->len; n++) { 1022 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1023 ms->possible_cpus->cpus[n].arch_id = n; 1024 1025 ms->possible_cpus->cpus[n].props.has_socket_id = true; 1026 ms->possible_cpus->cpus[n].props.socket_id = 1027 n / (ms->smp.cores * ms->smp.threads); 1028 ms->possible_cpus->cpus[n].props.has_core_id = true; 1029 ms->possible_cpus->cpus[n].props.core_id = 1030 n / ms->smp.threads % ms->smp.cores; 1031 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1032 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 1033 } 1034 return ms->possible_cpus; 1035 } 1036 1037 static CpuInstanceProperties 1038 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1039 { 1040 MachineClass *mc = MACHINE_GET_CLASS(ms); 1041 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1042 1043 assert(cpu_index < possible_cpus->len); 1044 return possible_cpus->cpus[cpu_index].props; 1045 } 1046 1047 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1048 { 1049 int64_t nidx = 0; 1050 1051 if (ms->numa_state->num_nodes) { 1052 nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes); 1053 if (ms->numa_state->num_nodes <= nidx) { 1054 nidx = ms->numa_state->num_nodes - 1; 1055 } 1056 } 1057 return nidx; 1058 } 1059 1060 static void loongarch_class_init(ObjectClass *oc, void *data) 1061 { 1062 MachineClass *mc = MACHINE_CLASS(oc); 1063 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1064 1065 mc->desc = "Loongson-3A5000 LS7A1000 machine"; 1066 mc->init = loongarch_init; 1067 mc->default_ram_size = 1 * GiB; 1068 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 1069 mc->default_ram_id = "loongarch.ram"; 1070 mc->max_cpus = LOONGARCH_MAX_CPUS; 1071 mc->is_default = 1; 1072 mc->default_kernel_irqchip_split = false; 1073 mc->block_default_type = IF_VIRTIO; 1074 mc->default_boot_order = "c"; 1075 mc->no_cdrom = 1; 1076 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1077 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1078 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1079 mc->numa_mem_supported = true; 1080 mc->auto_enable_numa_with_memhp = true; 1081 mc->auto_enable_numa_with_memdev = true; 1082 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1083 mc->default_nic = "virtio-net-pci"; 1084 hc->plug = loongarch_machine_device_plug_cb; 1085 hc->pre_plug = virt_machine_device_pre_plug; 1086 hc->unplug_request = virt_machine_device_unplug_request; 1087 hc->unplug = virt_machine_device_unplug; 1088 1089 object_class_property_add(oc, "acpi", "OnOffAuto", 1090 loongarch_get_acpi, loongarch_set_acpi, 1091 NULL, NULL); 1092 object_class_property_set_description(oc, "acpi", 1093 "Enable ACPI"); 1094 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1095 #ifdef CONFIG_TPM 1096 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1097 #endif 1098 } 1099 1100 static const TypeInfo loongarch_machine_types[] = { 1101 { 1102 .name = TYPE_LOONGARCH_MACHINE, 1103 .parent = TYPE_MACHINE, 1104 .instance_size = sizeof(LoongArchMachineState), 1105 .class_init = loongarch_class_init, 1106 .instance_init = loongarch_machine_initfn, 1107 .interfaces = (InterfaceInfo[]) { 1108 { TYPE_HOTPLUG_HANDLER }, 1109 { } 1110 }, 1111 } 1112 }; 1113 1114 DEFINE_TYPES(loongarch_machine_types) 1115