1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/sysemu.h" 14 #include "sysemu/qtest.h" 15 #include "sysemu/runstate.h" 16 #include "sysemu/reset.h" 17 #include "sysemu/rtc.h" 18 #include "hw/loongarch/virt.h" 19 #include "exec/address-spaces.h" 20 #include "hw/irq.h" 21 #include "net/net.h" 22 #include "hw/loader.h" 23 #include "elf.h" 24 #include "hw/intc/loongarch_ipi.h" 25 #include "hw/intc/loongarch_extioi.h" 26 #include "hw/intc/loongarch_pch_pic.h" 27 #include "hw/intc/loongarch_pch_msi.h" 28 #include "hw/pci-host/ls7a.h" 29 #include "hw/pci-host/gpex.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/loongarch/fw_cfg.h" 32 #include "target/loongarch/cpu.h" 33 #include "hw/firmware/smbios.h" 34 #include "hw/acpi/aml-build.h" 35 #include "qapi/qapi-visit-common.h" 36 #include "hw/acpi/generic_event_device.h" 37 #include "hw/mem/nvdimm.h" 38 #include "sysemu/device_tree.h" 39 #include <libfdt.h> 40 #include "hw/core/sysbus-fdt.h" 41 #include "hw/platform-bus.h" 42 #include "hw/display/ramfb.h" 43 #include "hw/mem/pc-dimm.h" 44 #include "sysemu/tpm.h" 45 #include "sysemu/block-backend.h" 46 #include "hw/block/flash.h" 47 #include "qemu/error-report.h" 48 49 static PFlashCFI01 *virt_flash_create1(LoongArchMachineState *lams, 50 const char *name, 51 const char *alias_prop_name) 52 { 53 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 54 55 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 56 qdev_prop_set_uint8(dev, "width", 4); 57 qdev_prop_set_uint8(dev, "device-width", 2); 58 qdev_prop_set_bit(dev, "big-endian", false); 59 qdev_prop_set_uint16(dev, "id0", 0x89); 60 qdev_prop_set_uint16(dev, "id1", 0x18); 61 qdev_prop_set_uint16(dev, "id2", 0x00); 62 qdev_prop_set_uint16(dev, "id3", 0x00); 63 qdev_prop_set_string(dev, "name", name); 64 object_property_add_child(OBJECT(lams), name, OBJECT(dev)); 65 object_property_add_alias(OBJECT(lams), alias_prop_name, 66 OBJECT(dev), "drive"); 67 return PFLASH_CFI01(dev); 68 } 69 70 static void virt_flash_create(LoongArchMachineState *lams) 71 { 72 lams->flash[0] = virt_flash_create1(lams, "virt.flash0", "pflash0"); 73 lams->flash[1] = virt_flash_create1(lams, "virt.flash1", "pflash1"); 74 } 75 76 static void virt_flash_map1(PFlashCFI01 *flash, 77 hwaddr base, hwaddr size, 78 MemoryRegion *sysmem) 79 { 80 DeviceState *dev = DEVICE(flash); 81 BlockBackend *blk; 82 hwaddr real_size = size; 83 84 blk = pflash_cfi01_get_blk(flash); 85 if (blk) { 86 real_size = blk_getlength(blk); 87 assert(real_size && real_size <= size); 88 } 89 90 assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE)); 91 assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 92 93 qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE); 94 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 95 memory_region_add_subregion(sysmem, base, 96 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 97 } 98 99 static void virt_flash_map(LoongArchMachineState *lams, 100 MemoryRegion *sysmem) 101 { 102 PFlashCFI01 *flash0 = lams->flash[0]; 103 PFlashCFI01 *flash1 = lams->flash[1]; 104 105 virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem); 106 virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem); 107 } 108 109 static void fdt_add_flash_node(LoongArchMachineState *lams) 110 { 111 MachineState *ms = MACHINE(lams); 112 char *nodename; 113 MemoryRegion *flash_mem; 114 115 hwaddr flash0_base; 116 hwaddr flash0_size; 117 118 hwaddr flash1_base; 119 hwaddr flash1_size; 120 121 flash_mem = pflash_cfi01_get_memory(lams->flash[0]); 122 flash0_base = flash_mem->addr; 123 flash0_size = memory_region_size(flash_mem); 124 125 flash_mem = pflash_cfi01_get_memory(lams->flash[1]); 126 flash1_base = flash_mem->addr; 127 flash1_size = memory_region_size(flash_mem); 128 129 nodename = g_strdup_printf("/flash@%" PRIx64, flash0_base); 130 qemu_fdt_add_subnode(ms->fdt, nodename); 131 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 132 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 133 2, flash0_base, 2, flash0_size, 134 2, flash1_base, 2, flash1_size); 135 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 136 g_free(nodename); 137 } 138 139 static void fdt_add_rtc_node(LoongArchMachineState *lams) 140 { 141 char *nodename; 142 hwaddr base = VIRT_RTC_REG_BASE; 143 hwaddr size = VIRT_RTC_LEN; 144 MachineState *ms = MACHINE(lams); 145 146 nodename = g_strdup_printf("/rtc@%" PRIx64, base); 147 qemu_fdt_add_subnode(ms->fdt, nodename); 148 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc"); 149 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 150 g_free(nodename); 151 } 152 153 static void fdt_add_uart_node(LoongArchMachineState *lams) 154 { 155 char *nodename; 156 hwaddr base = VIRT_UART_BASE; 157 hwaddr size = VIRT_UART_SIZE; 158 MachineState *ms = MACHINE(lams); 159 160 nodename = g_strdup_printf("/serial@%" PRIx64, base); 161 qemu_fdt_add_subnode(ms->fdt, nodename); 162 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); 163 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); 164 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); 165 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 166 g_free(nodename); 167 } 168 169 static void create_fdt(LoongArchMachineState *lams) 170 { 171 MachineState *ms = MACHINE(lams); 172 173 ms->fdt = create_device_tree(&lams->fdt_size); 174 if (!ms->fdt) { 175 error_report("create_device_tree() failed"); 176 exit(1); 177 } 178 179 /* Header */ 180 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 181 "linux,dummy-loongson3"); 182 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 183 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 184 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 185 } 186 187 static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) 188 { 189 int num; 190 const MachineState *ms = MACHINE(lams); 191 int smp_cpus = ms->smp.cpus; 192 193 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 194 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 195 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 196 197 /* cpu nodes */ 198 for (num = smp_cpus - 1; num >= 0; num--) { 199 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 200 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 201 CPUState *cs = CPU(cpu); 202 203 qemu_fdt_add_subnode(ms->fdt, nodename); 204 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 205 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 206 cpu->dtb_compatible); 207 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 208 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 209 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 210 } 211 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 212 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 213 qemu_fdt_alloc_phandle(ms->fdt)); 214 g_free(nodename); 215 } 216 217 /*cpu map */ 218 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 219 220 for (num = smp_cpus - 1; num >= 0; num--) { 221 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 222 char *map_path; 223 224 if (ms->smp.threads > 1) { 225 map_path = g_strdup_printf( 226 "/cpus/cpu-map/socket%d/core%d/thread%d", 227 num / (ms->smp.cores * ms->smp.threads), 228 (num / ms->smp.threads) % ms->smp.cores, 229 num % ms->smp.threads); 230 } else { 231 map_path = g_strdup_printf( 232 "/cpus/cpu-map/socket%d/core%d", 233 num / ms->smp.cores, 234 num % ms->smp.cores); 235 } 236 qemu_fdt_add_path(ms->fdt, map_path); 237 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 238 239 g_free(map_path); 240 g_free(cpu_path); 241 } 242 } 243 244 static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) 245 { 246 char *nodename; 247 hwaddr base = VIRT_FWCFG_BASE; 248 const MachineState *ms = MACHINE(lams); 249 250 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 251 qemu_fdt_add_subnode(ms->fdt, nodename); 252 qemu_fdt_setprop_string(ms->fdt, nodename, 253 "compatible", "qemu,fw-cfg-mmio"); 254 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 255 2, base, 2, 0x18); 256 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 257 g_free(nodename); 258 } 259 260 static void fdt_add_pcie_node(const LoongArchMachineState *lams) 261 { 262 char *nodename; 263 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 264 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 265 hwaddr base_pio = VIRT_PCI_IO_BASE; 266 hwaddr size_pio = VIRT_PCI_IO_SIZE; 267 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 268 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 269 hwaddr base = base_pcie; 270 271 const MachineState *ms = MACHINE(lams); 272 273 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 274 qemu_fdt_add_subnode(ms->fdt, nodename); 275 qemu_fdt_setprop_string(ms->fdt, nodename, 276 "compatible", "pci-host-ecam-generic"); 277 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 278 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 279 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 280 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 281 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 282 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 283 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 284 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 285 2, base_pcie, 2, size_pcie); 286 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 287 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 288 2, base_pio, 2, size_pio, 289 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 290 2, base_mmio, 2, size_mmio); 291 g_free(nodename); 292 } 293 294 static void fdt_add_irqchip_node(LoongArchMachineState *lams) 295 { 296 MachineState *ms = MACHINE(lams); 297 char *nodename; 298 uint32_t irqchip_phandle; 299 300 irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt); 301 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle); 302 303 nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE); 304 qemu_fdt_add_subnode(ms->fdt, nodename); 305 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 306 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 307 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 308 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 309 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 310 311 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 312 "loongarch,ls7a"); 313 314 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 315 2, VIRT_IOAPIC_REG_BASE, 316 2, PCH_PIC_ROUTE_ENTRY_OFFSET); 317 318 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle); 319 g_free(nodename); 320 } 321 322 static void fdt_add_memory_node(MachineState *ms, 323 uint64_t base, uint64_t size, int node_id) 324 { 325 char *nodename = g_strdup_printf("/memory@%" PRIx64, base); 326 327 qemu_fdt_add_subnode(ms->fdt, nodename); 328 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, 0, size); 329 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 330 331 if (ms->numa_state && ms->numa_state->num_nodes) { 332 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); 333 } 334 335 g_free(nodename); 336 } 337 338 static void virt_build_smbios(LoongArchMachineState *lams) 339 { 340 MachineState *ms = MACHINE(lams); 341 MachineClass *mc = MACHINE_GET_CLASS(lams); 342 uint8_t *smbios_tables, *smbios_anchor; 343 size_t smbios_tables_len, smbios_anchor_len; 344 const char *product = "QEMU Virtual Machine"; 345 346 if (!lams->fw_cfg) { 347 return; 348 } 349 350 smbios_set_defaults("QEMU", product, mc->name, true); 351 352 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 353 NULL, 0, 354 &smbios_tables, &smbios_tables_len, 355 &smbios_anchor, &smbios_anchor_len, &error_fatal); 356 357 if (smbios_anchor) { 358 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", 359 smbios_tables, smbios_tables_len); 360 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", 361 smbios_anchor, smbios_anchor_len); 362 } 363 } 364 365 static void virt_machine_done(Notifier *notifier, void *data) 366 { 367 LoongArchMachineState *lams = container_of(notifier, 368 LoongArchMachineState, machine_done); 369 virt_build_smbios(lams); 370 loongarch_acpi_setup(lams); 371 } 372 373 static void virt_powerdown_req(Notifier *notifier, void *opaque) 374 { 375 LoongArchMachineState *s = container_of(notifier, 376 LoongArchMachineState, powerdown_notifier); 377 378 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 379 } 380 381 struct memmap_entry *memmap_table; 382 unsigned memmap_entries; 383 384 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 385 { 386 /* Ensure there are no duplicate entries. */ 387 for (unsigned i = 0; i < memmap_entries; i++) { 388 assert(memmap_table[i].address != address); 389 } 390 391 memmap_table = g_renew(struct memmap_entry, memmap_table, 392 memmap_entries + 1); 393 memmap_table[memmap_entries].address = cpu_to_le64(address); 394 memmap_table[memmap_entries].length = cpu_to_le64(length); 395 memmap_table[memmap_entries].type = cpu_to_le32(type); 396 memmap_table[memmap_entries].reserved = 0; 397 memmap_entries++; 398 } 399 400 static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams) 401 { 402 DeviceState *dev; 403 MachineState *ms = MACHINE(lams); 404 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 405 406 if (ms->ram_slots) { 407 event |= ACPI_GED_MEM_HOTPLUG_EVT; 408 } 409 dev = qdev_new(TYPE_ACPI_GED); 410 qdev_prop_set_uint32(dev, "ged-event", event); 411 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 412 413 /* ged event */ 414 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 415 /* memory hotplug */ 416 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 417 /* ged regs used for reset and power down */ 418 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 419 420 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 421 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 422 return dev; 423 } 424 425 static DeviceState *create_platform_bus(DeviceState *pch_pic) 426 { 427 DeviceState *dev; 428 SysBusDevice *sysbus; 429 int i, irq; 430 MemoryRegion *sysmem = get_system_memory(); 431 432 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 433 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 434 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 435 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 436 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 437 438 sysbus = SYS_BUS_DEVICE(dev); 439 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 440 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 441 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 442 } 443 444 memory_region_add_subregion(sysmem, 445 VIRT_PLATFORM_BUS_BASEADDRESS, 446 sysbus_mmio_get_region(sysbus, 0)); 447 return dev; 448 } 449 450 static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams) 451 { 452 MachineClass *mc = MACHINE_GET_CLASS(lams); 453 DeviceState *gpex_dev; 454 SysBusDevice *d; 455 PCIBus *pci_bus; 456 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 457 MemoryRegion *mmio_alias, *mmio_reg; 458 int i; 459 460 gpex_dev = qdev_new(TYPE_GPEX_HOST); 461 d = SYS_BUS_DEVICE(gpex_dev); 462 sysbus_realize_and_unref(d, &error_fatal); 463 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 464 lams->pci_bus = pci_bus; 465 466 /* Map only part size_ecam bytes of ECAM space */ 467 ecam_alias = g_new0(MemoryRegion, 1); 468 ecam_reg = sysbus_mmio_get_region(d, 0); 469 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 470 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 471 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 472 ecam_alias); 473 474 /* Map PCI mem space */ 475 mmio_alias = g_new0(MemoryRegion, 1); 476 mmio_reg = sysbus_mmio_get_region(d, 1); 477 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 478 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 479 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 480 mmio_alias); 481 482 /* Map PCI IO port space. */ 483 pio_alias = g_new0(MemoryRegion, 1); 484 pio_reg = sysbus_mmio_get_region(d, 2); 485 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 486 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 487 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 488 pio_alias); 489 490 for (i = 0; i < GPEX_NUM_IRQS; i++) { 491 sysbus_connect_irq(d, i, 492 qdev_get_gpio_in(pch_pic, 16 + i)); 493 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 494 } 495 496 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 497 qdev_get_gpio_in(pch_pic, 498 VIRT_UART_IRQ - VIRT_GSI_BASE), 499 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 500 fdt_add_uart_node(lams); 501 502 /* Network init */ 503 pci_init_nic_devices(pci_bus, mc->default_nic); 504 505 /* 506 * There are some invalid guest memory access. 507 * Create some unimplemented devices to emulate this. 508 */ 509 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 510 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 511 qdev_get_gpio_in(pch_pic, 512 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 513 fdt_add_rtc_node(lams); 514 515 /* acpi ged */ 516 lams->acpi_ged = create_acpi_ged(pch_pic, lams); 517 /* platform bus */ 518 lams->platform_bus_dev = create_platform_bus(pch_pic); 519 } 520 521 static void loongarch_irq_init(LoongArchMachineState *lams) 522 { 523 MachineState *ms = MACHINE(lams); 524 DeviceState *pch_pic, *pch_msi, *cpudev; 525 DeviceState *ipi, *extioi; 526 SysBusDevice *d; 527 LoongArchCPU *lacpu; 528 CPULoongArchState *env; 529 CPUState *cpu_state; 530 int cpu, pin, i, start, num; 531 532 /* 533 * The connection of interrupts: 534 * +-----+ +---------+ +-------+ 535 * | IPI |--> | CPUINTC | <-- | Timer | 536 * +-----+ +---------+ +-------+ 537 * ^ 538 * | 539 * +---------+ 540 * | EIOINTC | 541 * +---------+ 542 * ^ ^ 543 * | | 544 * +---------+ +---------+ 545 * | PCH-PIC | | PCH-MSI | 546 * +---------+ +---------+ 547 * ^ ^ ^ 548 * | | | 549 * +--------+ +---------+ +---------+ 550 * | UARTs | | Devices | | Devices | 551 * +--------+ +---------+ +---------+ 552 */ 553 554 /* Create IPI device */ 555 ipi = qdev_new(TYPE_LOONGARCH_IPI); 556 qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); 557 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 558 559 /* IPI iocsr memory region */ 560 memory_region_add_subregion(&lams->system_iocsr, SMP_IPI_MAILBOX, 561 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); 562 memory_region_add_subregion(&lams->system_iocsr, MAIL_SEND_ADDR, 563 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); 564 565 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 566 cpu_state = qemu_get_cpu(cpu); 567 cpudev = DEVICE(cpu_state); 568 lacpu = LOONGARCH_CPU(cpu_state); 569 env = &(lacpu->env); 570 env->address_space_iocsr = &lams->as_iocsr; 571 572 /* connect ipi irq to cpu irq */ 573 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); 574 env->ipistate = ipi; 575 } 576 577 /* Create EXTIOI device */ 578 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 579 qdev_prop_set_uint32(extioi, "num-cpu", ms->smp.cpus); 580 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 581 memory_region_add_subregion(&lams->system_iocsr, APIC_BASE, 582 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); 583 584 /* 585 * connect ext irq to the cpu irq 586 * cpu_pin[9:2] <= intc_pin[7:0] 587 */ 588 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 589 cpudev = DEVICE(qemu_get_cpu(cpu)); 590 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 591 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 592 qdev_get_gpio_in(cpudev, pin + 2)); 593 } 594 } 595 596 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 597 num = VIRT_PCH_PIC_IRQ_NUM; 598 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 599 d = SYS_BUS_DEVICE(pch_pic); 600 sysbus_realize_and_unref(d, &error_fatal); 601 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 602 sysbus_mmio_get_region(d, 0)); 603 memory_region_add_subregion(get_system_memory(), 604 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 605 sysbus_mmio_get_region(d, 1)); 606 memory_region_add_subregion(get_system_memory(), 607 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 608 sysbus_mmio_get_region(d, 2)); 609 610 /* Connect pch_pic irqs to extioi */ 611 for (i = 0; i < num; i++) { 612 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 613 } 614 615 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 616 start = num; 617 num = EXTIOI_IRQS - start; 618 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 619 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 620 d = SYS_BUS_DEVICE(pch_msi); 621 sysbus_realize_and_unref(d, &error_fatal); 622 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 623 for (i = 0; i < num; i++) { 624 /* Connect pch_msi irqs to extioi */ 625 qdev_connect_gpio_out(DEVICE(d), i, 626 qdev_get_gpio_in(extioi, i + start)); 627 } 628 629 loongarch_devices_init(pch_pic, lams); 630 } 631 632 static void loongarch_firmware_init(LoongArchMachineState *lams) 633 { 634 char *filename = MACHINE(lams)->firmware; 635 char *bios_name = NULL; 636 int bios_size, i; 637 BlockBackend *pflash_blk0; 638 MemoryRegion *mr; 639 640 lams->bios_loaded = false; 641 642 /* Map legacy -drive if=pflash to machine properties */ 643 for (i = 0; i < ARRAY_SIZE(lams->flash); i++) { 644 pflash_cfi01_legacy_drive(lams->flash[i], 645 drive_get(IF_PFLASH, 0, i)); 646 } 647 648 virt_flash_map(lams, get_system_memory()); 649 650 pflash_blk0 = pflash_cfi01_get_blk(lams->flash[0]); 651 652 if (pflash_blk0) { 653 if (filename) { 654 error_report("cannot use both '-bios' and '-drive if=pflash'" 655 "options at once"); 656 exit(1); 657 } 658 lams->bios_loaded = true; 659 return; 660 } 661 662 if (filename) { 663 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 664 if (!bios_name) { 665 error_report("Could not find ROM image '%s'", filename); 666 exit(1); 667 } 668 669 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lams->flash[0]), 0); 670 bios_size = load_image_mr(bios_name, mr); 671 if (bios_size < 0) { 672 error_report("Could not load ROM image '%s'", bios_name); 673 exit(1); 674 } 675 g_free(bios_name); 676 lams->bios_loaded = true; 677 } 678 } 679 680 681 static void loongarch_qemu_write(void *opaque, hwaddr addr, 682 uint64_t val, unsigned size) 683 { 684 } 685 686 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) 687 { 688 switch (addr) { 689 case VERSION_REG: 690 return 0x11ULL; 691 case FEATURE_REG: 692 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 693 1ULL << IOCSRF_CSRIPI; 694 case VENDOR_REG: 695 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 696 case CPUNAME_REG: 697 return 0x303030354133ULL; /* "3A5000" */ 698 case MISC_FUNC_REG: 699 return 1ULL << IOCSRM_EXTIOI_EN; 700 } 701 return 0ULL; 702 } 703 704 static const MemoryRegionOps loongarch_qemu_ops = { 705 .read = loongarch_qemu_read, 706 .write = loongarch_qemu_write, 707 .endianness = DEVICE_LITTLE_ENDIAN, 708 .valid = { 709 .min_access_size = 4, 710 .max_access_size = 8, 711 }, 712 .impl = { 713 .min_access_size = 8, 714 .max_access_size = 8, 715 }, 716 }; 717 718 static void loongarch_init(MachineState *machine) 719 { 720 LoongArchCPU *lacpu; 721 const char *cpu_model = machine->cpu_type; 722 ram_addr_t offset = 0; 723 ram_addr_t ram_size = machine->ram_size; 724 uint64_t highram_size = 0, phyAddr = 0; 725 MemoryRegion *address_space_mem = get_system_memory(); 726 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 727 int nb_numa_nodes = machine->numa_state->num_nodes; 728 NodeInfo *numa_info = machine->numa_state->nodes; 729 int i; 730 const CPUArchIdList *possible_cpus; 731 MachineClass *mc = MACHINE_GET_CLASS(machine); 732 CPUState *cpu; 733 char *ramName = NULL; 734 735 if (!cpu_model) { 736 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 737 } 738 739 if (ram_size < 1 * GiB) { 740 error_report("ram_size must be greater than 1G."); 741 exit(1); 742 } 743 create_fdt(lams); 744 745 /* Create IOCSR space */ 746 memory_region_init_io(&lams->system_iocsr, OBJECT(machine), NULL, 747 machine, "iocsr", UINT64_MAX); 748 address_space_init(&lams->as_iocsr, &lams->system_iocsr, "IOCSR"); 749 memory_region_init_io(&lams->iocsr_mem, OBJECT(machine), 750 &loongarch_qemu_ops, 751 machine, "iocsr_misc", 0x428); 752 memory_region_add_subregion(&lams->system_iocsr, 0, &lams->iocsr_mem); 753 754 /* Init CPUs */ 755 possible_cpus = mc->possible_cpu_arch_ids(machine); 756 for (i = 0; i < possible_cpus->len; i++) { 757 cpu = cpu_create(machine->cpu_type); 758 cpu->cpu_index = i; 759 machine->possible_cpus->cpus[i].cpu = cpu; 760 lacpu = LOONGARCH_CPU(cpu); 761 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; 762 } 763 fdt_add_cpu_nodes(lams); 764 765 /* Node0 memory */ 766 memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1); 767 fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0); 768 memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram", 769 machine->ram, offset, VIRT_LOWMEM_SIZE); 770 memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem); 771 772 offset += VIRT_LOWMEM_SIZE; 773 if (nb_numa_nodes > 0) { 774 assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE); 775 highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE; 776 } else { 777 highram_size = ram_size - VIRT_LOWMEM_SIZE; 778 } 779 phyAddr = VIRT_HIGHMEM_BASE; 780 memmap_add_entry(phyAddr, highram_size, 1); 781 fdt_add_memory_node(machine, phyAddr, highram_size, 0); 782 memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram", 783 machine->ram, offset, highram_size); 784 memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem); 785 786 /* Node1 - Nodemax memory */ 787 offset += highram_size; 788 phyAddr += highram_size; 789 790 for (i = 1; i < nb_numa_nodes; i++) { 791 MemoryRegion *nodemem = g_new(MemoryRegion, 1); 792 ramName = g_strdup_printf("loongarch.node%d.ram", i); 793 memory_region_init_alias(nodemem, NULL, ramName, machine->ram, 794 offset, numa_info[i].node_mem); 795 memory_region_add_subregion(address_space_mem, phyAddr, nodemem); 796 memmap_add_entry(phyAddr, numa_info[i].node_mem, 1); 797 fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i); 798 offset += numa_info[i].node_mem; 799 phyAddr += numa_info[i].node_mem; 800 } 801 802 /* initialize device memory address space */ 803 if (machine->ram_size < machine->maxram_size) { 804 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 805 hwaddr device_mem_base; 806 807 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 808 error_report("unsupported amount of memory slots: %"PRIu64, 809 machine->ram_slots); 810 exit(EXIT_FAILURE); 811 } 812 813 if (QEMU_ALIGN_UP(machine->maxram_size, 814 TARGET_PAGE_SIZE) != machine->maxram_size) { 815 error_report("maximum memory size must by aligned to multiple of " 816 "%d bytes", TARGET_PAGE_SIZE); 817 exit(EXIT_FAILURE); 818 } 819 /* device memory base is the top of high memory address. */ 820 device_mem_base = ROUND_UP(VIRT_HIGHMEM_BASE + highram_size, 1 * GiB); 821 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 822 } 823 824 /* load the BIOS image. */ 825 loongarch_firmware_init(lams); 826 827 /* fw_cfg init */ 828 lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine); 829 rom_set_fw(lams->fw_cfg); 830 if (lams->fw_cfg != NULL) { 831 fw_cfg_add_file(lams->fw_cfg, "etc/memmap", 832 memmap_table, 833 sizeof(struct memmap_entry) * (memmap_entries)); 834 } 835 fdt_add_fw_cfg_node(lams); 836 fdt_add_flash_node(lams); 837 838 /* Initialize the IO interrupt subsystem */ 839 loongarch_irq_init(lams); 840 fdt_add_irqchip_node(lams); 841 platform_bus_add_all_fdt_nodes(machine->fdt, "/intc", 842 VIRT_PLATFORM_BUS_BASEADDRESS, 843 VIRT_PLATFORM_BUS_SIZE, 844 VIRT_PLATFORM_BUS_IRQ); 845 lams->machine_done.notify = virt_machine_done; 846 qemu_add_machine_init_done_notifier(&lams->machine_done); 847 /* connect powerdown request */ 848 lams->powerdown_notifier.notify = virt_powerdown_req; 849 qemu_register_powerdown_notifier(&lams->powerdown_notifier); 850 851 fdt_add_pcie_node(lams); 852 /* 853 * Since lowmem region starts from 0 and Linux kernel legacy start address 854 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer 855 * access. FDT size limit with 1 MiB. 856 * Put the FDT into the memory map as a ROM image: this will ensure 857 * the FDT is copied again upon reset, even if addr points into RAM. 858 */ 859 qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size); 860 rom_add_blob_fixed_as("fdt", machine->fdt, lams->fdt_size, FDT_BASE, 861 &address_space_memory); 862 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 863 rom_ptr_for_as(&address_space_memory, FDT_BASE, lams->fdt_size)); 864 865 lams->bootinfo.ram_size = ram_size; 866 loongarch_load_kernel(machine, &lams->bootinfo); 867 } 868 869 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) 870 { 871 if (lams->acpi == ON_OFF_AUTO_OFF) { 872 return false; 873 } 874 return true; 875 } 876 877 static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, 878 void *opaque, Error **errp) 879 { 880 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 881 OnOffAuto acpi = lams->acpi; 882 883 visit_type_OnOffAuto(v, name, &acpi, errp); 884 } 885 886 static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, 887 void *opaque, Error **errp) 888 { 889 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 890 891 visit_type_OnOffAuto(v, name, &lams->acpi, errp); 892 } 893 894 static void loongarch_machine_initfn(Object *obj) 895 { 896 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 897 898 lams->acpi = ON_OFF_AUTO_AUTO; 899 lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 900 lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 901 virt_flash_create(lams); 902 } 903 904 static bool memhp_type_supported(DeviceState *dev) 905 { 906 /* we only support pc dimm now */ 907 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 908 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 909 } 910 911 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 912 Error **errp) 913 { 914 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 915 } 916 917 static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev, 918 DeviceState *dev, Error **errp) 919 { 920 if (memhp_type_supported(dev)) { 921 virt_mem_pre_plug(hotplug_dev, dev, errp); 922 } 923 } 924 925 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 926 DeviceState *dev, Error **errp) 927 { 928 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 929 930 /* the acpi ged is always exist */ 931 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lams->acpi_ged), dev, 932 errp); 933 } 934 935 static void virt_machine_device_unplug_request(HotplugHandler *hotplug_dev, 936 DeviceState *dev, Error **errp) 937 { 938 if (memhp_type_supported(dev)) { 939 virt_mem_unplug_request(hotplug_dev, dev, errp); 940 } 941 } 942 943 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 944 DeviceState *dev, Error **errp) 945 { 946 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 947 948 hotplug_handler_unplug(HOTPLUG_HANDLER(lams->acpi_ged), dev, errp); 949 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lams)); 950 qdev_unrealize(dev); 951 } 952 953 static void virt_machine_device_unplug(HotplugHandler *hotplug_dev, 954 DeviceState *dev, Error **errp) 955 { 956 if (memhp_type_supported(dev)) { 957 virt_mem_unplug(hotplug_dev, dev, errp); 958 } 959 } 960 961 static void virt_mem_plug(HotplugHandler *hotplug_dev, 962 DeviceState *dev, Error **errp) 963 { 964 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 965 966 pc_dimm_plug(PC_DIMM(dev), MACHINE(lams)); 967 hotplug_handler_plug(HOTPLUG_HANDLER(lams->acpi_ged), 968 dev, &error_abort); 969 } 970 971 static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev, 972 DeviceState *dev, Error **errp) 973 { 974 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 975 MachineClass *mc = MACHINE_GET_CLASS(lams); 976 977 if (device_is_dynamic_sysbus(mc, dev)) { 978 if (lams->platform_bus_dev) { 979 platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev), 980 SYS_BUS_DEVICE(dev)); 981 } 982 } else if (memhp_type_supported(dev)) { 983 virt_mem_plug(hotplug_dev, dev, errp); 984 } 985 } 986 987 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 988 DeviceState *dev) 989 { 990 MachineClass *mc = MACHINE_GET_CLASS(machine); 991 992 if (device_is_dynamic_sysbus(mc, dev) || 993 memhp_type_supported(dev)) { 994 return HOTPLUG_HANDLER(machine); 995 } 996 return NULL; 997 } 998 999 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1000 { 1001 int n; 1002 unsigned int max_cpus = ms->smp.max_cpus; 1003 1004 if (ms->possible_cpus) { 1005 assert(ms->possible_cpus->len == max_cpus); 1006 return ms->possible_cpus; 1007 } 1008 1009 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1010 sizeof(CPUArchId) * max_cpus); 1011 ms->possible_cpus->len = max_cpus; 1012 for (n = 0; n < ms->possible_cpus->len; n++) { 1013 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1014 ms->possible_cpus->cpus[n].arch_id = n; 1015 1016 ms->possible_cpus->cpus[n].props.has_socket_id = true; 1017 ms->possible_cpus->cpus[n].props.socket_id = 1018 n / (ms->smp.cores * ms->smp.threads); 1019 ms->possible_cpus->cpus[n].props.has_core_id = true; 1020 ms->possible_cpus->cpus[n].props.core_id = 1021 n / ms->smp.threads % ms->smp.cores; 1022 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1023 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 1024 } 1025 return ms->possible_cpus; 1026 } 1027 1028 static CpuInstanceProperties 1029 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1030 { 1031 MachineClass *mc = MACHINE_GET_CLASS(ms); 1032 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1033 1034 assert(cpu_index < possible_cpus->len); 1035 return possible_cpus->cpus[cpu_index].props; 1036 } 1037 1038 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1039 { 1040 int64_t nidx = 0; 1041 1042 if (ms->numa_state->num_nodes) { 1043 nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes); 1044 if (ms->numa_state->num_nodes <= nidx) { 1045 nidx = ms->numa_state->num_nodes - 1; 1046 } 1047 } 1048 return nidx; 1049 } 1050 1051 static void loongarch_class_init(ObjectClass *oc, void *data) 1052 { 1053 MachineClass *mc = MACHINE_CLASS(oc); 1054 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1055 1056 mc->desc = "Loongson-3A5000 LS7A1000 machine"; 1057 mc->init = loongarch_init; 1058 mc->default_ram_size = 1 * GiB; 1059 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 1060 mc->default_ram_id = "loongarch.ram"; 1061 mc->max_cpus = LOONGARCH_MAX_CPUS; 1062 mc->is_default = 1; 1063 mc->default_kernel_irqchip_split = false; 1064 mc->block_default_type = IF_VIRTIO; 1065 mc->default_boot_order = "c"; 1066 mc->no_cdrom = 1; 1067 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1068 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1069 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1070 mc->numa_mem_supported = true; 1071 mc->auto_enable_numa_with_memhp = true; 1072 mc->auto_enable_numa_with_memdev = true; 1073 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1074 mc->default_nic = "virtio-net-pci"; 1075 hc->plug = loongarch_machine_device_plug_cb; 1076 hc->pre_plug = virt_machine_device_pre_plug; 1077 hc->unplug_request = virt_machine_device_unplug_request; 1078 hc->unplug = virt_machine_device_unplug; 1079 1080 object_class_property_add(oc, "acpi", "OnOffAuto", 1081 loongarch_get_acpi, loongarch_set_acpi, 1082 NULL, NULL); 1083 object_class_property_set_description(oc, "acpi", 1084 "Enable ACPI"); 1085 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1086 #ifdef CONFIG_TPM 1087 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1088 #endif 1089 } 1090 1091 static const TypeInfo loongarch_machine_types[] = { 1092 { 1093 .name = TYPE_LOONGARCH_MACHINE, 1094 .parent = TYPE_MACHINE, 1095 .instance_size = sizeof(LoongArchMachineState), 1096 .class_init = loongarch_class_init, 1097 .instance_init = loongarch_machine_initfn, 1098 .interfaces = (InterfaceInfo[]) { 1099 { TYPE_HOTPLUG_HANDLER }, 1100 { } 1101 }, 1102 } 1103 }; 1104 1105 DEFINE_TYPES(loongarch_machine_types) 1106