1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/kvm.h" 14 #include "sysemu/sysemu.h" 15 #include "sysemu/qtest.h" 16 #include "sysemu/runstate.h" 17 #include "sysemu/reset.h" 18 #include "sysemu/rtc.h" 19 #include "hw/loongarch/virt.h" 20 #include "exec/address-spaces.h" 21 #include "hw/irq.h" 22 #include "net/net.h" 23 #include "hw/loader.h" 24 #include "elf.h" 25 #include "hw/intc/loongson_ipi.h" 26 #include "hw/intc/loongarch_extioi.h" 27 #include "hw/intc/loongarch_pch_pic.h" 28 #include "hw/intc/loongarch_pch_msi.h" 29 #include "hw/pci-host/ls7a.h" 30 #include "hw/pci-host/gpex.h" 31 #include "hw/misc/unimp.h" 32 #include "hw/loongarch/fw_cfg.h" 33 #include "target/loongarch/cpu.h" 34 #include "hw/firmware/smbios.h" 35 #include "hw/acpi/aml-build.h" 36 #include "qapi/qapi-visit-common.h" 37 #include "hw/acpi/generic_event_device.h" 38 #include "hw/mem/nvdimm.h" 39 #include "sysemu/device_tree.h" 40 #include <libfdt.h> 41 #include "hw/core/sysbus-fdt.h" 42 #include "hw/platform-bus.h" 43 #include "hw/display/ramfb.h" 44 #include "hw/mem/pc-dimm.h" 45 #include "sysemu/tpm.h" 46 #include "sysemu/block-backend.h" 47 #include "hw/block/flash.h" 48 #include "qemu/error-report.h" 49 50 static PFlashCFI01 *virt_flash_create1(LoongArchVirtMachineState *lvms, 51 const char *name, 52 const char *alias_prop_name) 53 { 54 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 55 56 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 57 qdev_prop_set_uint8(dev, "width", 4); 58 qdev_prop_set_uint8(dev, "device-width", 2); 59 qdev_prop_set_bit(dev, "big-endian", false); 60 qdev_prop_set_uint16(dev, "id0", 0x89); 61 qdev_prop_set_uint16(dev, "id1", 0x18); 62 qdev_prop_set_uint16(dev, "id2", 0x00); 63 qdev_prop_set_uint16(dev, "id3", 0x00); 64 qdev_prop_set_string(dev, "name", name); 65 object_property_add_child(OBJECT(lvms), name, OBJECT(dev)); 66 object_property_add_alias(OBJECT(lvms), alias_prop_name, 67 OBJECT(dev), "drive"); 68 return PFLASH_CFI01(dev); 69 } 70 71 static void virt_flash_create(LoongArchVirtMachineState *lvms) 72 { 73 lvms->flash[0] = virt_flash_create1(lvms, "virt.flash0", "pflash0"); 74 lvms->flash[1] = virt_flash_create1(lvms, "virt.flash1", "pflash1"); 75 } 76 77 static void virt_flash_map1(PFlashCFI01 *flash, 78 hwaddr base, hwaddr size, 79 MemoryRegion *sysmem) 80 { 81 DeviceState *dev = DEVICE(flash); 82 BlockBackend *blk; 83 hwaddr real_size = size; 84 85 blk = pflash_cfi01_get_blk(flash); 86 if (blk) { 87 real_size = blk_getlength(blk); 88 assert(real_size && real_size <= size); 89 } 90 91 assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE)); 92 assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 93 94 qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE); 95 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 96 memory_region_add_subregion(sysmem, base, 97 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 98 } 99 100 static void virt_flash_map(LoongArchVirtMachineState *lvms, 101 MemoryRegion *sysmem) 102 { 103 PFlashCFI01 *flash0 = lvms->flash[0]; 104 PFlashCFI01 *flash1 = lvms->flash[1]; 105 106 virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem); 107 virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem); 108 } 109 110 static void fdt_add_cpuic_node(LoongArchVirtMachineState *lvms, 111 uint32_t *cpuintc_phandle) 112 { 113 MachineState *ms = MACHINE(lvms); 114 char *nodename; 115 116 *cpuintc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 117 nodename = g_strdup_printf("/cpuic"); 118 qemu_fdt_add_subnode(ms->fdt, nodename); 119 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *cpuintc_phandle); 120 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 121 "loongson,cpu-interrupt-controller"); 122 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 123 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 124 g_free(nodename); 125 } 126 127 static void fdt_add_eiointc_node(LoongArchVirtMachineState *lvms, 128 uint32_t *cpuintc_phandle, 129 uint32_t *eiointc_phandle) 130 { 131 MachineState *ms = MACHINE(lvms); 132 char *nodename; 133 hwaddr extioi_base = APIC_BASE; 134 hwaddr extioi_size = EXTIOI_SIZE; 135 136 *eiointc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 137 nodename = g_strdup_printf("/eiointc@%" PRIx64, extioi_base); 138 qemu_fdt_add_subnode(ms->fdt, nodename); 139 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *eiointc_phandle); 140 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 141 "loongson,ls2k2000-eiointc"); 142 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 143 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 144 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 145 *cpuintc_phandle); 146 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", 3); 147 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, 148 extioi_base, 0x0, extioi_size); 149 g_free(nodename); 150 } 151 152 static void fdt_add_pch_pic_node(LoongArchVirtMachineState *lvms, 153 uint32_t *eiointc_phandle, 154 uint32_t *pch_pic_phandle) 155 { 156 MachineState *ms = MACHINE(lvms); 157 char *nodename; 158 hwaddr pch_pic_base = VIRT_PCH_REG_BASE; 159 hwaddr pch_pic_size = VIRT_PCH_REG_SIZE; 160 161 *pch_pic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 162 nodename = g_strdup_printf("/platic@%" PRIx64, pch_pic_base); 163 qemu_fdt_add_subnode(ms->fdt, nodename); 164 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_pic_phandle); 165 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 166 "loongson,pch-pic-1.0"); 167 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, 168 pch_pic_base, 0, pch_pic_size); 169 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 170 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 2); 171 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 172 *eiointc_phandle); 173 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,pic-base-vec", 0); 174 g_free(nodename); 175 } 176 177 static void fdt_add_pch_msi_node(LoongArchVirtMachineState *lvms, 178 uint32_t *eiointc_phandle, 179 uint32_t *pch_msi_phandle) 180 { 181 MachineState *ms = MACHINE(lvms); 182 char *nodename; 183 hwaddr pch_msi_base = VIRT_PCH_MSI_ADDR_LOW; 184 hwaddr pch_msi_size = VIRT_PCH_MSI_SIZE; 185 186 *pch_msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 187 nodename = g_strdup_printf("/msi@%" PRIx64, pch_msi_base); 188 qemu_fdt_add_subnode(ms->fdt, nodename); 189 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_msi_phandle); 190 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 191 "loongson,pch-msi-1.0"); 192 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 193 0, pch_msi_base, 194 0, pch_msi_size); 195 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 196 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 197 *eiointc_phandle); 198 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-base-vec", 199 VIRT_PCH_PIC_IRQ_NUM); 200 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-num-vecs", 201 EXTIOI_IRQS - VIRT_PCH_PIC_IRQ_NUM); 202 g_free(nodename); 203 } 204 205 static void fdt_add_flash_node(LoongArchVirtMachineState *lvms) 206 { 207 MachineState *ms = MACHINE(lvms); 208 char *nodename; 209 MemoryRegion *flash_mem; 210 211 hwaddr flash0_base; 212 hwaddr flash0_size; 213 214 hwaddr flash1_base; 215 hwaddr flash1_size; 216 217 flash_mem = pflash_cfi01_get_memory(lvms->flash[0]); 218 flash0_base = flash_mem->addr; 219 flash0_size = memory_region_size(flash_mem); 220 221 flash_mem = pflash_cfi01_get_memory(lvms->flash[1]); 222 flash1_base = flash_mem->addr; 223 flash1_size = memory_region_size(flash_mem); 224 225 nodename = g_strdup_printf("/flash@%" PRIx64, flash0_base); 226 qemu_fdt_add_subnode(ms->fdt, nodename); 227 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 228 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 229 2, flash0_base, 2, flash0_size, 230 2, flash1_base, 2, flash1_size); 231 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 232 g_free(nodename); 233 } 234 235 static void fdt_add_rtc_node(LoongArchVirtMachineState *lvms, 236 uint32_t *pch_pic_phandle) 237 { 238 char *nodename; 239 hwaddr base = VIRT_RTC_REG_BASE; 240 hwaddr size = VIRT_RTC_LEN; 241 MachineState *ms = MACHINE(lvms); 242 243 nodename = g_strdup_printf("/rtc@%" PRIx64, base); 244 qemu_fdt_add_subnode(ms->fdt, nodename); 245 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 246 "loongson,ls7a-rtc"); 247 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 248 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 249 VIRT_RTC_IRQ - VIRT_GSI_BASE , 0x4); 250 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 251 *pch_pic_phandle); 252 g_free(nodename); 253 } 254 255 static void fdt_add_uart_node(LoongArchVirtMachineState *lvms, 256 uint32_t *pch_pic_phandle) 257 { 258 char *nodename; 259 hwaddr base = VIRT_UART_BASE; 260 hwaddr size = VIRT_UART_SIZE; 261 MachineState *ms = MACHINE(lvms); 262 263 nodename = g_strdup_printf("/serial@%" PRIx64, base); 264 qemu_fdt_add_subnode(ms->fdt, nodename); 265 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); 266 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); 267 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); 268 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 269 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 270 VIRT_UART_IRQ - VIRT_GSI_BASE, 0x4); 271 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 272 *pch_pic_phandle); 273 g_free(nodename); 274 } 275 276 static void create_fdt(LoongArchVirtMachineState *lvms) 277 { 278 MachineState *ms = MACHINE(lvms); 279 280 ms->fdt = create_device_tree(&lvms->fdt_size); 281 if (!ms->fdt) { 282 error_report("create_device_tree() failed"); 283 exit(1); 284 } 285 286 /* Header */ 287 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 288 "linux,dummy-loongson3"); 289 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 290 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 291 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 292 } 293 294 static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms) 295 { 296 int num; 297 const MachineState *ms = MACHINE(lvms); 298 int smp_cpus = ms->smp.cpus; 299 300 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 301 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 302 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 303 304 /* cpu nodes */ 305 for (num = smp_cpus - 1; num >= 0; num--) { 306 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 307 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 308 CPUState *cs = CPU(cpu); 309 310 qemu_fdt_add_subnode(ms->fdt, nodename); 311 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 312 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 313 cpu->dtb_compatible); 314 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 315 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 316 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 317 } 318 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 319 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 320 qemu_fdt_alloc_phandle(ms->fdt)); 321 g_free(nodename); 322 } 323 324 /*cpu map */ 325 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 326 327 for (num = smp_cpus - 1; num >= 0; num--) { 328 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 329 char *map_path; 330 331 if (ms->smp.threads > 1) { 332 map_path = g_strdup_printf( 333 "/cpus/cpu-map/socket%d/core%d/thread%d", 334 num / (ms->smp.cores * ms->smp.threads), 335 (num / ms->smp.threads) % ms->smp.cores, 336 num % ms->smp.threads); 337 } else { 338 map_path = g_strdup_printf( 339 "/cpus/cpu-map/socket%d/core%d", 340 num / ms->smp.cores, 341 num % ms->smp.cores); 342 } 343 qemu_fdt_add_path(ms->fdt, map_path); 344 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 345 346 g_free(map_path); 347 g_free(cpu_path); 348 } 349 } 350 351 static void fdt_add_fw_cfg_node(const LoongArchVirtMachineState *lvms) 352 { 353 char *nodename; 354 hwaddr base = VIRT_FWCFG_BASE; 355 const MachineState *ms = MACHINE(lvms); 356 357 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 358 qemu_fdt_add_subnode(ms->fdt, nodename); 359 qemu_fdt_setprop_string(ms->fdt, nodename, 360 "compatible", "qemu,fw-cfg-mmio"); 361 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 362 2, base, 2, 0x18); 363 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 364 g_free(nodename); 365 } 366 367 static void fdt_add_pcie_irq_map_node(const LoongArchVirtMachineState *lvms, 368 char *nodename, 369 uint32_t *pch_pic_phandle) 370 { 371 int pin, dev; 372 uint32_t irq_map_stride = 0; 373 uint32_t full_irq_map[GPEX_NUM_IRQS *GPEX_NUM_IRQS * 10] = {}; 374 uint32_t *irq_map = full_irq_map; 375 const MachineState *ms = MACHINE(lvms); 376 377 /* This code creates a standard swizzle of interrupts such that 378 * each device's first interrupt is based on it's PCI_SLOT number. 379 * (See pci_swizzle_map_irq_fn()) 380 * 381 * We only need one entry per interrupt in the table (not one per 382 * possible slot) seeing the interrupt-map-mask will allow the table 383 * to wrap to any number of devices. 384 */ 385 386 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 387 int devfn = dev * 0x8; 388 389 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 390 int irq_nr = 16 + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 391 int i = 0; 392 393 /* Fill PCI address cells */ 394 irq_map[i] = cpu_to_be32(devfn << 8); 395 i += 3; 396 397 /* Fill PCI Interrupt cells */ 398 irq_map[i] = cpu_to_be32(pin + 1); 399 i += 1; 400 401 /* Fill interrupt controller phandle and cells */ 402 irq_map[i++] = cpu_to_be32(*pch_pic_phandle); 403 irq_map[i++] = cpu_to_be32(irq_nr); 404 405 if (!irq_map_stride) { 406 irq_map_stride = i; 407 } 408 irq_map += irq_map_stride; 409 } 410 } 411 412 413 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", full_irq_map, 414 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 415 irq_map_stride * sizeof(uint32_t)); 416 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 417 0x1800, 0, 0, 0x7); 418 } 419 420 static void fdt_add_pcie_node(const LoongArchVirtMachineState *lvms, 421 uint32_t *pch_pic_phandle, 422 uint32_t *pch_msi_phandle) 423 { 424 char *nodename; 425 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 426 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 427 hwaddr base_pio = VIRT_PCI_IO_BASE; 428 hwaddr size_pio = VIRT_PCI_IO_SIZE; 429 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 430 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 431 hwaddr base = base_pcie; 432 433 const MachineState *ms = MACHINE(lvms); 434 435 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 436 qemu_fdt_add_subnode(ms->fdt, nodename); 437 qemu_fdt_setprop_string(ms->fdt, nodename, 438 "compatible", "pci-host-ecam-generic"); 439 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 440 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 441 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 442 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 443 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 444 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 445 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 446 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 447 2, base_pcie, 2, size_pcie); 448 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 449 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 450 2, base_pio, 2, size_pio, 451 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 452 2, base_mmio, 2, size_mmio); 453 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 454 0, *pch_msi_phandle, 0, 0x10000); 455 456 fdt_add_pcie_irq_map_node(lvms, nodename, pch_pic_phandle); 457 458 g_free(nodename); 459 } 460 461 static void fdt_add_memory_node(MachineState *ms, 462 uint64_t base, uint64_t size, int node_id) 463 { 464 char *nodename = g_strdup_printf("/memory@%" PRIx64, base); 465 466 qemu_fdt_add_subnode(ms->fdt, nodename); 467 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, 0, size); 468 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 469 470 if (ms->numa_state && ms->numa_state->num_nodes) { 471 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); 472 } 473 474 g_free(nodename); 475 } 476 477 static void virt_build_smbios(LoongArchVirtMachineState *lvms) 478 { 479 MachineState *ms = MACHINE(lvms); 480 MachineClass *mc = MACHINE_GET_CLASS(lvms); 481 uint8_t *smbios_tables, *smbios_anchor; 482 size_t smbios_tables_len, smbios_anchor_len; 483 const char *product = "QEMU Virtual Machine"; 484 485 if (!lvms->fw_cfg) { 486 return; 487 } 488 489 smbios_set_defaults("QEMU", product, mc->name, true); 490 491 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 492 NULL, 0, 493 &smbios_tables, &smbios_tables_len, 494 &smbios_anchor, &smbios_anchor_len, &error_fatal); 495 496 if (smbios_anchor) { 497 fw_cfg_add_file(lvms->fw_cfg, "etc/smbios/smbios-tables", 498 smbios_tables, smbios_tables_len); 499 fw_cfg_add_file(lvms->fw_cfg, "etc/smbios/smbios-anchor", 500 smbios_anchor, smbios_anchor_len); 501 } 502 } 503 504 static void virt_done(Notifier *notifier, void *data) 505 { 506 LoongArchVirtMachineState *lvms = container_of(notifier, 507 LoongArchVirtMachineState, machine_done); 508 virt_build_smbios(lvms); 509 loongarch_acpi_setup(lvms); 510 } 511 512 static void virt_powerdown_req(Notifier *notifier, void *opaque) 513 { 514 LoongArchVirtMachineState *s; 515 516 s = container_of(notifier, LoongArchVirtMachineState, powerdown_notifier); 517 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 518 } 519 520 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 521 { 522 /* Ensure there are no duplicate entries. */ 523 for (unsigned i = 0; i < memmap_entries; i++) { 524 assert(memmap_table[i].address != address); 525 } 526 527 memmap_table = g_renew(struct memmap_entry, memmap_table, 528 memmap_entries + 1); 529 memmap_table[memmap_entries].address = cpu_to_le64(address); 530 memmap_table[memmap_entries].length = cpu_to_le64(length); 531 memmap_table[memmap_entries].type = cpu_to_le32(type); 532 memmap_table[memmap_entries].reserved = 0; 533 memmap_entries++; 534 } 535 536 static DeviceState *create_acpi_ged(DeviceState *pch_pic, 537 LoongArchVirtMachineState *lvms) 538 { 539 DeviceState *dev; 540 MachineState *ms = MACHINE(lvms); 541 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 542 543 if (ms->ram_slots) { 544 event |= ACPI_GED_MEM_HOTPLUG_EVT; 545 } 546 dev = qdev_new(TYPE_ACPI_GED); 547 qdev_prop_set_uint32(dev, "ged-event", event); 548 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 549 550 /* ged event */ 551 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 552 /* memory hotplug */ 553 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 554 /* ged regs used for reset and power down */ 555 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 556 557 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 558 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 559 return dev; 560 } 561 562 static DeviceState *create_platform_bus(DeviceState *pch_pic) 563 { 564 DeviceState *dev; 565 SysBusDevice *sysbus; 566 int i, irq; 567 MemoryRegion *sysmem = get_system_memory(); 568 569 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 570 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 571 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 572 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 573 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 574 575 sysbus = SYS_BUS_DEVICE(dev); 576 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 577 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 578 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 579 } 580 581 memory_region_add_subregion(sysmem, 582 VIRT_PLATFORM_BUS_BASEADDRESS, 583 sysbus_mmio_get_region(sysbus, 0)); 584 return dev; 585 } 586 587 static void virt_devices_init(DeviceState *pch_pic, 588 LoongArchVirtMachineState *lvms, 589 uint32_t *pch_pic_phandle, 590 uint32_t *pch_msi_phandle) 591 { 592 MachineClass *mc = MACHINE_GET_CLASS(lvms); 593 DeviceState *gpex_dev; 594 SysBusDevice *d; 595 PCIBus *pci_bus; 596 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 597 MemoryRegion *mmio_alias, *mmio_reg; 598 int i; 599 600 gpex_dev = qdev_new(TYPE_GPEX_HOST); 601 d = SYS_BUS_DEVICE(gpex_dev); 602 sysbus_realize_and_unref(d, &error_fatal); 603 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 604 lvms->pci_bus = pci_bus; 605 606 /* Map only part size_ecam bytes of ECAM space */ 607 ecam_alias = g_new0(MemoryRegion, 1); 608 ecam_reg = sysbus_mmio_get_region(d, 0); 609 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 610 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 611 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 612 ecam_alias); 613 614 /* Map PCI mem space */ 615 mmio_alias = g_new0(MemoryRegion, 1); 616 mmio_reg = sysbus_mmio_get_region(d, 1); 617 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 618 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 619 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 620 mmio_alias); 621 622 /* Map PCI IO port space. */ 623 pio_alias = g_new0(MemoryRegion, 1); 624 pio_reg = sysbus_mmio_get_region(d, 2); 625 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 626 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 627 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 628 pio_alias); 629 630 for (i = 0; i < GPEX_NUM_IRQS; i++) { 631 sysbus_connect_irq(d, i, 632 qdev_get_gpio_in(pch_pic, 16 + i)); 633 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 634 } 635 636 /* Add pcie node */ 637 fdt_add_pcie_node(lvms, pch_pic_phandle, pch_msi_phandle); 638 639 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 640 qdev_get_gpio_in(pch_pic, 641 VIRT_UART_IRQ - VIRT_GSI_BASE), 642 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 643 fdt_add_uart_node(lvms, pch_pic_phandle); 644 645 /* Network init */ 646 pci_init_nic_devices(pci_bus, mc->default_nic); 647 648 /* 649 * There are some invalid guest memory access. 650 * Create some unimplemented devices to emulate this. 651 */ 652 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 653 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 654 qdev_get_gpio_in(pch_pic, 655 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 656 fdt_add_rtc_node(lvms, pch_pic_phandle); 657 658 /* acpi ged */ 659 lvms->acpi_ged = create_acpi_ged(pch_pic, lvms); 660 /* platform bus */ 661 lvms->platform_bus_dev = create_platform_bus(pch_pic); 662 } 663 664 static void virt_irq_init(LoongArchVirtMachineState *lvms) 665 { 666 MachineState *ms = MACHINE(lvms); 667 DeviceState *pch_pic, *pch_msi, *cpudev; 668 DeviceState *ipi, *extioi; 669 SysBusDevice *d; 670 LoongArchCPU *lacpu; 671 CPULoongArchState *env; 672 CPUState *cpu_state; 673 int cpu, pin, i, start, num; 674 uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle; 675 676 /* 677 * The connection of interrupts: 678 * +-----+ +---------+ +-------+ 679 * | IPI |--> | CPUINTC | <-- | Timer | 680 * +-----+ +---------+ +-------+ 681 * ^ 682 * | 683 * +---------+ 684 * | EIOINTC | 685 * +---------+ 686 * ^ ^ 687 * | | 688 * +---------+ +---------+ 689 * | PCH-PIC | | PCH-MSI | 690 * +---------+ +---------+ 691 * ^ ^ ^ 692 * | | | 693 * +--------+ +---------+ +---------+ 694 * | UARTs | | Devices | | Devices | 695 * +--------+ +---------+ +---------+ 696 */ 697 698 /* Create IPI device */ 699 ipi = qdev_new(TYPE_LOONGSON_IPI); 700 qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); 701 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 702 703 /* IPI iocsr memory region */ 704 memory_region_add_subregion(&lvms->system_iocsr, SMP_IPI_MAILBOX, 705 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); 706 memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR, 707 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); 708 709 /* Add cpu interrupt-controller */ 710 fdt_add_cpuic_node(lvms, &cpuintc_phandle); 711 712 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 713 cpu_state = qemu_get_cpu(cpu); 714 cpudev = DEVICE(cpu_state); 715 lacpu = LOONGARCH_CPU(cpu_state); 716 env = &(lacpu->env); 717 env->address_space_iocsr = &lvms->as_iocsr; 718 719 /* connect ipi irq to cpu irq */ 720 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); 721 env->ipistate = ipi; 722 } 723 724 /* Create EXTIOI device */ 725 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 726 qdev_prop_set_uint32(extioi, "num-cpu", ms->smp.cpus); 727 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 728 memory_region_add_subregion(&lvms->system_iocsr, APIC_BASE, 729 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); 730 731 /* 732 * connect ext irq to the cpu irq 733 * cpu_pin[9:2] <= intc_pin[7:0] 734 */ 735 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 736 cpudev = DEVICE(qemu_get_cpu(cpu)); 737 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 738 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 739 qdev_get_gpio_in(cpudev, pin + 2)); 740 } 741 } 742 743 /* Add Extend I/O Interrupt Controller node */ 744 fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle); 745 746 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 747 num = VIRT_PCH_PIC_IRQ_NUM; 748 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 749 d = SYS_BUS_DEVICE(pch_pic); 750 sysbus_realize_and_unref(d, &error_fatal); 751 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 752 sysbus_mmio_get_region(d, 0)); 753 memory_region_add_subregion(get_system_memory(), 754 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 755 sysbus_mmio_get_region(d, 1)); 756 memory_region_add_subregion(get_system_memory(), 757 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 758 sysbus_mmio_get_region(d, 2)); 759 760 /* Connect pch_pic irqs to extioi */ 761 for (i = 0; i < num; i++) { 762 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 763 } 764 765 /* Add PCH PIC node */ 766 fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle); 767 768 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 769 start = num; 770 num = EXTIOI_IRQS - start; 771 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 772 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 773 d = SYS_BUS_DEVICE(pch_msi); 774 sysbus_realize_and_unref(d, &error_fatal); 775 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 776 for (i = 0; i < num; i++) { 777 /* Connect pch_msi irqs to extioi */ 778 qdev_connect_gpio_out(DEVICE(d), i, 779 qdev_get_gpio_in(extioi, i + start)); 780 } 781 782 /* Add PCH MSI node */ 783 fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle); 784 785 virt_devices_init(pch_pic, lvms, &pch_pic_phandle, &pch_msi_phandle); 786 } 787 788 static void virt_firmware_init(LoongArchVirtMachineState *lvms) 789 { 790 char *filename = MACHINE(lvms)->firmware; 791 char *bios_name = NULL; 792 int bios_size, i; 793 BlockBackend *pflash_blk0; 794 MemoryRegion *mr; 795 796 lvms->bios_loaded = false; 797 798 /* Map legacy -drive if=pflash to machine properties */ 799 for (i = 0; i < ARRAY_SIZE(lvms->flash); i++) { 800 pflash_cfi01_legacy_drive(lvms->flash[i], 801 drive_get(IF_PFLASH, 0, i)); 802 } 803 804 virt_flash_map(lvms, get_system_memory()); 805 806 pflash_blk0 = pflash_cfi01_get_blk(lvms->flash[0]); 807 808 if (pflash_blk0) { 809 if (filename) { 810 error_report("cannot use both '-bios' and '-drive if=pflash'" 811 "options at once"); 812 exit(1); 813 } 814 lvms->bios_loaded = true; 815 return; 816 } 817 818 if (filename) { 819 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 820 if (!bios_name) { 821 error_report("Could not find ROM image '%s'", filename); 822 exit(1); 823 } 824 825 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lvms->flash[0]), 0); 826 bios_size = load_image_mr(bios_name, mr); 827 if (bios_size < 0) { 828 error_report("Could not load ROM image '%s'", bios_name); 829 exit(1); 830 } 831 g_free(bios_name); 832 lvms->bios_loaded = true; 833 } 834 } 835 836 837 static void virt_iocsr_misc_write(void *opaque, hwaddr addr, 838 uint64_t val, unsigned size) 839 { 840 } 841 842 static uint64_t virt_iocsr_misc_read(void *opaque, hwaddr addr, unsigned size) 843 { 844 uint64_t ret; 845 846 switch (addr) { 847 case VERSION_REG: 848 return 0x11ULL; 849 case FEATURE_REG: 850 ret = BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); 851 if (kvm_enabled()) { 852 ret |= BIT(IOCSRF_VM); 853 } 854 return ret; 855 case VENDOR_REG: 856 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 857 case CPUNAME_REG: 858 return 0x303030354133ULL; /* "3A5000" */ 859 case MISC_FUNC_REG: 860 return BIT_ULL(IOCSRM_EXTIOI_EN); 861 } 862 return 0ULL; 863 } 864 865 static const MemoryRegionOps virt_iocsr_misc_ops = { 866 .read = virt_iocsr_misc_read, 867 .write = virt_iocsr_misc_write, 868 .endianness = DEVICE_LITTLE_ENDIAN, 869 .valid = { 870 .min_access_size = 4, 871 .max_access_size = 8, 872 }, 873 .impl = { 874 .min_access_size = 8, 875 .max_access_size = 8, 876 }, 877 }; 878 879 static void virt_init(MachineState *machine) 880 { 881 LoongArchCPU *lacpu; 882 const char *cpu_model = machine->cpu_type; 883 ram_addr_t offset = 0; 884 ram_addr_t ram_size = machine->ram_size; 885 uint64_t highram_size = 0, phyAddr = 0; 886 MemoryRegion *address_space_mem = get_system_memory(); 887 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine); 888 int nb_numa_nodes = machine->numa_state->num_nodes; 889 NodeInfo *numa_info = machine->numa_state->nodes; 890 int i; 891 const CPUArchIdList *possible_cpus; 892 MachineClass *mc = MACHINE_GET_CLASS(machine); 893 CPUState *cpu; 894 895 if (!cpu_model) { 896 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 897 } 898 899 if (ram_size < 1 * GiB) { 900 error_report("ram_size must be greater than 1G."); 901 exit(1); 902 } 903 create_fdt(lvms); 904 905 /* Create IOCSR space */ 906 memory_region_init_io(&lvms->system_iocsr, OBJECT(machine), NULL, 907 machine, "iocsr", UINT64_MAX); 908 address_space_init(&lvms->as_iocsr, &lvms->system_iocsr, "IOCSR"); 909 memory_region_init_io(&lvms->iocsr_mem, OBJECT(machine), 910 &virt_iocsr_misc_ops, 911 machine, "iocsr_misc", 0x428); 912 memory_region_add_subregion(&lvms->system_iocsr, 0, &lvms->iocsr_mem); 913 914 /* Init CPUs */ 915 possible_cpus = mc->possible_cpu_arch_ids(machine); 916 for (i = 0; i < possible_cpus->len; i++) { 917 cpu = cpu_create(machine->cpu_type); 918 cpu->cpu_index = i; 919 machine->possible_cpus->cpus[i].cpu = cpu; 920 lacpu = LOONGARCH_CPU(cpu); 921 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; 922 } 923 fdt_add_cpu_nodes(lvms); 924 925 /* Node0 memory */ 926 memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1); 927 fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0); 928 memory_region_init_alias(&lvms->lowmem, NULL, "loongarch.node0.lowram", 929 machine->ram, offset, VIRT_LOWMEM_SIZE); 930 memory_region_add_subregion(address_space_mem, phyAddr, &lvms->lowmem); 931 932 offset += VIRT_LOWMEM_SIZE; 933 if (nb_numa_nodes > 0) { 934 assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE); 935 highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE; 936 } else { 937 highram_size = ram_size - VIRT_LOWMEM_SIZE; 938 } 939 phyAddr = VIRT_HIGHMEM_BASE; 940 memmap_add_entry(phyAddr, highram_size, 1); 941 fdt_add_memory_node(machine, phyAddr, highram_size, 0); 942 memory_region_init_alias(&lvms->highmem, NULL, "loongarch.node0.highram", 943 machine->ram, offset, highram_size); 944 memory_region_add_subregion(address_space_mem, phyAddr, &lvms->highmem); 945 946 /* Node1 - Nodemax memory */ 947 offset += highram_size; 948 phyAddr += highram_size; 949 950 for (i = 1; i < nb_numa_nodes; i++) { 951 MemoryRegion *nodemem = g_new(MemoryRegion, 1); 952 g_autofree char *ramName = g_strdup_printf("loongarch.node%d.ram", i); 953 memory_region_init_alias(nodemem, NULL, ramName, machine->ram, 954 offset, numa_info[i].node_mem); 955 memory_region_add_subregion(address_space_mem, phyAddr, nodemem); 956 memmap_add_entry(phyAddr, numa_info[i].node_mem, 1); 957 fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i); 958 offset += numa_info[i].node_mem; 959 phyAddr += numa_info[i].node_mem; 960 } 961 962 /* initialize device memory address space */ 963 if (machine->ram_size < machine->maxram_size) { 964 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 965 hwaddr device_mem_base; 966 967 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 968 error_report("unsupported amount of memory slots: %"PRIu64, 969 machine->ram_slots); 970 exit(EXIT_FAILURE); 971 } 972 973 if (QEMU_ALIGN_UP(machine->maxram_size, 974 TARGET_PAGE_SIZE) != machine->maxram_size) { 975 error_report("maximum memory size must by aligned to multiple of " 976 "%d bytes", TARGET_PAGE_SIZE); 977 exit(EXIT_FAILURE); 978 } 979 /* device memory base is the top of high memory address. */ 980 device_mem_base = ROUND_UP(VIRT_HIGHMEM_BASE + highram_size, 1 * GiB); 981 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 982 } 983 984 /* load the BIOS image. */ 985 virt_firmware_init(lvms); 986 987 /* fw_cfg init */ 988 lvms->fw_cfg = virt_fw_cfg_init(ram_size, machine); 989 rom_set_fw(lvms->fw_cfg); 990 if (lvms->fw_cfg != NULL) { 991 fw_cfg_add_file(lvms->fw_cfg, "etc/memmap", 992 memmap_table, 993 sizeof(struct memmap_entry) * (memmap_entries)); 994 } 995 fdt_add_fw_cfg_node(lvms); 996 fdt_add_flash_node(lvms); 997 998 /* Initialize the IO interrupt subsystem */ 999 virt_irq_init(lvms); 1000 platform_bus_add_all_fdt_nodes(machine->fdt, "/platic", 1001 VIRT_PLATFORM_BUS_BASEADDRESS, 1002 VIRT_PLATFORM_BUS_SIZE, 1003 VIRT_PLATFORM_BUS_IRQ); 1004 lvms->machine_done.notify = virt_done; 1005 qemu_add_machine_init_done_notifier(&lvms->machine_done); 1006 /* connect powerdown request */ 1007 lvms->powerdown_notifier.notify = virt_powerdown_req; 1008 qemu_register_powerdown_notifier(&lvms->powerdown_notifier); 1009 1010 /* 1011 * Since lowmem region starts from 0 and Linux kernel legacy start address 1012 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer 1013 * access. FDT size limit with 1 MiB. 1014 * Put the FDT into the memory map as a ROM image: this will ensure 1015 * the FDT is copied again upon reset, even if addr points into RAM. 1016 */ 1017 qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size); 1018 rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE, 1019 &address_space_memory); 1020 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 1021 rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size)); 1022 1023 lvms->bootinfo.ram_size = ram_size; 1024 loongarch_load_kernel(machine, &lvms->bootinfo); 1025 } 1026 1027 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1028 void *opaque, Error **errp) 1029 { 1030 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 1031 OnOffAuto acpi = lvms->acpi; 1032 1033 visit_type_OnOffAuto(v, name, &acpi, errp); 1034 } 1035 1036 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1037 void *opaque, Error **errp) 1038 { 1039 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 1040 1041 visit_type_OnOffAuto(v, name, &lvms->acpi, errp); 1042 } 1043 1044 static void virt_initfn(Object *obj) 1045 { 1046 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 1047 1048 lvms->acpi = ON_OFF_AUTO_AUTO; 1049 lvms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1050 lvms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1051 virt_flash_create(lvms); 1052 } 1053 1054 static bool memhp_type_supported(DeviceState *dev) 1055 { 1056 /* we only support pc dimm now */ 1057 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 1058 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1059 } 1060 1061 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1062 Error **errp) 1063 { 1064 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 1065 } 1066 1067 static void virt_device_pre_plug(HotplugHandler *hotplug_dev, 1068 DeviceState *dev, Error **errp) 1069 { 1070 if (memhp_type_supported(dev)) { 1071 virt_mem_pre_plug(hotplug_dev, dev, errp); 1072 } 1073 } 1074 1075 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 1076 DeviceState *dev, Error **errp) 1077 { 1078 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 1079 1080 /* the acpi ged is always exist */ 1081 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lvms->acpi_ged), dev, 1082 errp); 1083 } 1084 1085 static void virt_device_unplug_request(HotplugHandler *hotplug_dev, 1086 DeviceState *dev, Error **errp) 1087 { 1088 if (memhp_type_supported(dev)) { 1089 virt_mem_unplug_request(hotplug_dev, dev, errp); 1090 } 1091 } 1092 1093 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 1094 DeviceState *dev, Error **errp) 1095 { 1096 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 1097 1098 hotplug_handler_unplug(HOTPLUG_HANDLER(lvms->acpi_ged), dev, errp); 1099 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lvms)); 1100 qdev_unrealize(dev); 1101 } 1102 1103 static void virt_device_unplug(HotplugHandler *hotplug_dev, 1104 DeviceState *dev, Error **errp) 1105 { 1106 if (memhp_type_supported(dev)) { 1107 virt_mem_unplug(hotplug_dev, dev, errp); 1108 } 1109 } 1110 1111 static void virt_mem_plug(HotplugHandler *hotplug_dev, 1112 DeviceState *dev, Error **errp) 1113 { 1114 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 1115 1116 pc_dimm_plug(PC_DIMM(dev), MACHINE(lvms)); 1117 hotplug_handler_plug(HOTPLUG_HANDLER(lvms->acpi_ged), 1118 dev, &error_abort); 1119 } 1120 1121 static void virt_device_plug_cb(HotplugHandler *hotplug_dev, 1122 DeviceState *dev, Error **errp) 1123 { 1124 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 1125 MachineClass *mc = MACHINE_GET_CLASS(lvms); 1126 PlatformBusDevice *pbus; 1127 1128 if (device_is_dynamic_sysbus(mc, dev)) { 1129 if (lvms->platform_bus_dev) { 1130 pbus = PLATFORM_BUS_DEVICE(lvms->platform_bus_dev); 1131 platform_bus_link_device(pbus, SYS_BUS_DEVICE(dev)); 1132 } 1133 } else if (memhp_type_supported(dev)) { 1134 virt_mem_plug(hotplug_dev, dev, errp); 1135 } 1136 } 1137 1138 static HotplugHandler *virt_get_hotplug_handler(MachineState *machine, 1139 DeviceState *dev) 1140 { 1141 MachineClass *mc = MACHINE_GET_CLASS(machine); 1142 1143 if (device_is_dynamic_sysbus(mc, dev) || 1144 memhp_type_supported(dev)) { 1145 return HOTPLUG_HANDLER(machine); 1146 } 1147 return NULL; 1148 } 1149 1150 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1151 { 1152 int n; 1153 unsigned int max_cpus = ms->smp.max_cpus; 1154 1155 if (ms->possible_cpus) { 1156 assert(ms->possible_cpus->len == max_cpus); 1157 return ms->possible_cpus; 1158 } 1159 1160 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1161 sizeof(CPUArchId) * max_cpus); 1162 ms->possible_cpus->len = max_cpus; 1163 for (n = 0; n < ms->possible_cpus->len; n++) { 1164 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1165 ms->possible_cpus->cpus[n].arch_id = n; 1166 1167 ms->possible_cpus->cpus[n].props.has_socket_id = true; 1168 ms->possible_cpus->cpus[n].props.socket_id = 1169 n / (ms->smp.cores * ms->smp.threads); 1170 ms->possible_cpus->cpus[n].props.has_core_id = true; 1171 ms->possible_cpus->cpus[n].props.core_id = 1172 n / ms->smp.threads % ms->smp.cores; 1173 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1174 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 1175 } 1176 return ms->possible_cpus; 1177 } 1178 1179 static CpuInstanceProperties virt_cpu_index_to_props(MachineState *ms, 1180 unsigned cpu_index) 1181 { 1182 MachineClass *mc = MACHINE_GET_CLASS(ms); 1183 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1184 1185 assert(cpu_index < possible_cpus->len); 1186 return possible_cpus->cpus[cpu_index].props; 1187 } 1188 1189 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1190 { 1191 int64_t socket_id; 1192 1193 if (ms->numa_state->num_nodes) { 1194 socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 1195 return socket_id % ms->numa_state->num_nodes; 1196 } else { 1197 return 0; 1198 } 1199 } 1200 1201 static void virt_class_init(ObjectClass *oc, void *data) 1202 { 1203 MachineClass *mc = MACHINE_CLASS(oc); 1204 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1205 1206 mc->init = virt_init; 1207 mc->default_ram_size = 1 * GiB; 1208 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 1209 mc->default_ram_id = "loongarch.ram"; 1210 mc->max_cpus = LOONGARCH_MAX_CPUS; 1211 mc->is_default = 1; 1212 mc->default_kernel_irqchip_split = false; 1213 mc->block_default_type = IF_VIRTIO; 1214 mc->default_boot_order = "c"; 1215 mc->no_cdrom = 1; 1216 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1217 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1218 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1219 mc->numa_mem_supported = true; 1220 mc->auto_enable_numa_with_memhp = true; 1221 mc->auto_enable_numa_with_memdev = true; 1222 mc->get_hotplug_handler = virt_get_hotplug_handler; 1223 mc->default_nic = "virtio-net-pci"; 1224 hc->plug = virt_device_plug_cb; 1225 hc->pre_plug = virt_device_pre_plug; 1226 hc->unplug_request = virt_device_unplug_request; 1227 hc->unplug = virt_device_unplug; 1228 1229 object_class_property_add(oc, "acpi", "OnOffAuto", 1230 virt_get_acpi, virt_set_acpi, 1231 NULL, NULL); 1232 object_class_property_set_description(oc, "acpi", 1233 "Enable ACPI"); 1234 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1235 #ifdef CONFIG_TPM 1236 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1237 #endif 1238 } 1239 1240 static const TypeInfo virt_machine_types[] = { 1241 { 1242 .name = TYPE_LOONGARCH_VIRT_MACHINE, 1243 .parent = TYPE_MACHINE, 1244 .instance_size = sizeof(LoongArchVirtMachineState), 1245 .class_init = virt_class_init, 1246 .instance_init = virt_initfn, 1247 .interfaces = (InterfaceInfo[]) { 1248 { TYPE_HOTPLUG_HANDLER }, 1249 { } 1250 }, 1251 } 1252 }; 1253 1254 DEFINE_TYPES(virt_machine_types) 1255