1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/sysemu.h" 14 #include "sysemu/qtest.h" 15 #include "sysemu/runstate.h" 16 #include "sysemu/reset.h" 17 #include "sysemu/rtc.h" 18 #include "hw/loongarch/virt.h" 19 #include "exec/address-spaces.h" 20 #include "hw/irq.h" 21 #include "net/net.h" 22 #include "hw/loader.h" 23 #include "elf.h" 24 #include "hw/intc/loongarch_ipi.h" 25 #include "hw/intc/loongarch_extioi.h" 26 #include "hw/intc/loongarch_pch_pic.h" 27 #include "hw/intc/loongarch_pch_msi.h" 28 #include "hw/pci-host/ls7a.h" 29 #include "hw/pci-host/gpex.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/loongarch/fw_cfg.h" 32 #include "target/loongarch/cpu.h" 33 #include "hw/firmware/smbios.h" 34 #include "hw/acpi/aml-build.h" 35 #include "qapi/qapi-visit-common.h" 36 #include "hw/acpi/generic_event_device.h" 37 #include "hw/mem/nvdimm.h" 38 #include "sysemu/device_tree.h" 39 #include <libfdt.h> 40 #include "hw/core/sysbus-fdt.h" 41 #include "hw/platform-bus.h" 42 #include "hw/display/ramfb.h" 43 #include "hw/mem/pc-dimm.h" 44 #include "sysemu/tpm.h" 45 #include "sysemu/block-backend.h" 46 #include "hw/block/flash.h" 47 #include "qemu/error-report.h" 48 49 static PFlashCFI01 *virt_flash_create1(LoongArchMachineState *lams, 50 const char *name, 51 const char *alias_prop_name) 52 { 53 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 54 55 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 56 qdev_prop_set_uint8(dev, "width", 4); 57 qdev_prop_set_uint8(dev, "device-width", 2); 58 qdev_prop_set_bit(dev, "big-endian", false); 59 qdev_prop_set_uint16(dev, "id0", 0x89); 60 qdev_prop_set_uint16(dev, "id1", 0x18); 61 qdev_prop_set_uint16(dev, "id2", 0x00); 62 qdev_prop_set_uint16(dev, "id3", 0x00); 63 qdev_prop_set_string(dev, "name", name); 64 object_property_add_child(OBJECT(lams), name, OBJECT(dev)); 65 object_property_add_alias(OBJECT(lams), alias_prop_name, 66 OBJECT(dev), "drive"); 67 return PFLASH_CFI01(dev); 68 } 69 70 static void virt_flash_create(LoongArchMachineState *lams) 71 { 72 lams->flash[0] = virt_flash_create1(lams, "virt.flash0", "pflash0"); 73 lams->flash[1] = virt_flash_create1(lams, "virt.flash1", "pflash1"); 74 } 75 76 static void virt_flash_map1(PFlashCFI01 *flash, 77 hwaddr base, hwaddr size, 78 MemoryRegion *sysmem) 79 { 80 DeviceState *dev = DEVICE(flash); 81 BlockBackend *blk; 82 hwaddr real_size = size; 83 84 blk = pflash_cfi01_get_blk(flash); 85 if (blk) { 86 real_size = blk_getlength(blk); 87 assert(real_size && real_size <= size); 88 } 89 90 assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE)); 91 assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 92 93 qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE); 94 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 95 memory_region_add_subregion(sysmem, base, 96 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 97 } 98 99 static void virt_flash_map(LoongArchMachineState *lams, 100 MemoryRegion *sysmem) 101 { 102 PFlashCFI01 *flash0 = lams->flash[0]; 103 PFlashCFI01 *flash1 = lams->flash[1]; 104 105 virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem); 106 virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem); 107 } 108 109 static void fdt_add_cpuic_node(LoongArchMachineState *lams, 110 uint32_t *cpuintc_phandle) 111 { 112 MachineState *ms = MACHINE(lams); 113 char *nodename; 114 115 *cpuintc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 116 nodename = g_strdup_printf("/cpuic"); 117 qemu_fdt_add_subnode(ms->fdt, nodename); 118 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *cpuintc_phandle); 119 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 120 "loongson,cpu-interrupt-controller"); 121 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 122 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 123 g_free(nodename); 124 } 125 126 static void fdt_add_flash_node(LoongArchMachineState *lams) 127 { 128 MachineState *ms = MACHINE(lams); 129 char *nodename; 130 MemoryRegion *flash_mem; 131 132 hwaddr flash0_base; 133 hwaddr flash0_size; 134 135 hwaddr flash1_base; 136 hwaddr flash1_size; 137 138 flash_mem = pflash_cfi01_get_memory(lams->flash[0]); 139 flash0_base = flash_mem->addr; 140 flash0_size = memory_region_size(flash_mem); 141 142 flash_mem = pflash_cfi01_get_memory(lams->flash[1]); 143 flash1_base = flash_mem->addr; 144 flash1_size = memory_region_size(flash_mem); 145 146 nodename = g_strdup_printf("/flash@%" PRIx64, flash0_base); 147 qemu_fdt_add_subnode(ms->fdt, nodename); 148 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 149 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 150 2, flash0_base, 2, flash0_size, 151 2, flash1_base, 2, flash1_size); 152 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 153 g_free(nodename); 154 } 155 156 static void fdt_add_rtc_node(LoongArchMachineState *lams) 157 { 158 char *nodename; 159 hwaddr base = VIRT_RTC_REG_BASE; 160 hwaddr size = VIRT_RTC_LEN; 161 MachineState *ms = MACHINE(lams); 162 163 nodename = g_strdup_printf("/rtc@%" PRIx64, base); 164 qemu_fdt_add_subnode(ms->fdt, nodename); 165 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc"); 166 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 167 g_free(nodename); 168 } 169 170 static void fdt_add_uart_node(LoongArchMachineState *lams) 171 { 172 char *nodename; 173 hwaddr base = VIRT_UART_BASE; 174 hwaddr size = VIRT_UART_SIZE; 175 MachineState *ms = MACHINE(lams); 176 177 nodename = g_strdup_printf("/serial@%" PRIx64, base); 178 qemu_fdt_add_subnode(ms->fdt, nodename); 179 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); 180 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); 181 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); 182 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 183 g_free(nodename); 184 } 185 186 static void create_fdt(LoongArchMachineState *lams) 187 { 188 MachineState *ms = MACHINE(lams); 189 190 ms->fdt = create_device_tree(&lams->fdt_size); 191 if (!ms->fdt) { 192 error_report("create_device_tree() failed"); 193 exit(1); 194 } 195 196 /* Header */ 197 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 198 "linux,dummy-loongson3"); 199 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 200 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 201 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 202 } 203 204 static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) 205 { 206 int num; 207 const MachineState *ms = MACHINE(lams); 208 int smp_cpus = ms->smp.cpus; 209 210 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 211 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 212 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 213 214 /* cpu nodes */ 215 for (num = smp_cpus - 1; num >= 0; num--) { 216 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 217 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 218 CPUState *cs = CPU(cpu); 219 220 qemu_fdt_add_subnode(ms->fdt, nodename); 221 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 222 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 223 cpu->dtb_compatible); 224 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 225 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 226 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 227 } 228 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 229 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 230 qemu_fdt_alloc_phandle(ms->fdt)); 231 g_free(nodename); 232 } 233 234 /*cpu map */ 235 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 236 237 for (num = smp_cpus - 1; num >= 0; num--) { 238 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 239 char *map_path; 240 241 if (ms->smp.threads > 1) { 242 map_path = g_strdup_printf( 243 "/cpus/cpu-map/socket%d/core%d/thread%d", 244 num / (ms->smp.cores * ms->smp.threads), 245 (num / ms->smp.threads) % ms->smp.cores, 246 num % ms->smp.threads); 247 } else { 248 map_path = g_strdup_printf( 249 "/cpus/cpu-map/socket%d/core%d", 250 num / ms->smp.cores, 251 num % ms->smp.cores); 252 } 253 qemu_fdt_add_path(ms->fdt, map_path); 254 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 255 256 g_free(map_path); 257 g_free(cpu_path); 258 } 259 } 260 261 static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) 262 { 263 char *nodename; 264 hwaddr base = VIRT_FWCFG_BASE; 265 const MachineState *ms = MACHINE(lams); 266 267 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 268 qemu_fdt_add_subnode(ms->fdt, nodename); 269 qemu_fdt_setprop_string(ms->fdt, nodename, 270 "compatible", "qemu,fw-cfg-mmio"); 271 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 272 2, base, 2, 0x18); 273 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 274 g_free(nodename); 275 } 276 277 static void fdt_add_pcie_node(const LoongArchMachineState *lams) 278 { 279 char *nodename; 280 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 281 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 282 hwaddr base_pio = VIRT_PCI_IO_BASE; 283 hwaddr size_pio = VIRT_PCI_IO_SIZE; 284 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 285 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 286 hwaddr base = base_pcie; 287 288 const MachineState *ms = MACHINE(lams); 289 290 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 291 qemu_fdt_add_subnode(ms->fdt, nodename); 292 qemu_fdt_setprop_string(ms->fdt, nodename, 293 "compatible", "pci-host-ecam-generic"); 294 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 295 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 296 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 297 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 298 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 299 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 300 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 301 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 302 2, base_pcie, 2, size_pcie); 303 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 304 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 305 2, base_pio, 2, size_pio, 306 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 307 2, base_mmio, 2, size_mmio); 308 g_free(nodename); 309 } 310 311 static void fdt_add_irqchip_node(LoongArchMachineState *lams) 312 { 313 MachineState *ms = MACHINE(lams); 314 char *nodename; 315 uint32_t irqchip_phandle; 316 317 irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt); 318 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle); 319 320 nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE); 321 qemu_fdt_add_subnode(ms->fdt, nodename); 322 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 323 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 324 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 325 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 326 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 327 328 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 329 "loongarch,ls7a"); 330 331 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 332 2, VIRT_IOAPIC_REG_BASE, 333 2, PCH_PIC_ROUTE_ENTRY_OFFSET); 334 335 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle); 336 g_free(nodename); 337 } 338 339 static void fdt_add_memory_node(MachineState *ms, 340 uint64_t base, uint64_t size, int node_id) 341 { 342 char *nodename = g_strdup_printf("/memory@%" PRIx64, base); 343 344 qemu_fdt_add_subnode(ms->fdt, nodename); 345 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, 0, size); 346 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 347 348 if (ms->numa_state && ms->numa_state->num_nodes) { 349 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); 350 } 351 352 g_free(nodename); 353 } 354 355 static void virt_build_smbios(LoongArchMachineState *lams) 356 { 357 MachineState *ms = MACHINE(lams); 358 MachineClass *mc = MACHINE_GET_CLASS(lams); 359 uint8_t *smbios_tables, *smbios_anchor; 360 size_t smbios_tables_len, smbios_anchor_len; 361 const char *product = "QEMU Virtual Machine"; 362 363 if (!lams->fw_cfg) { 364 return; 365 } 366 367 smbios_set_defaults("QEMU", product, mc->name, true); 368 369 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 370 NULL, 0, 371 &smbios_tables, &smbios_tables_len, 372 &smbios_anchor, &smbios_anchor_len, &error_fatal); 373 374 if (smbios_anchor) { 375 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", 376 smbios_tables, smbios_tables_len); 377 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", 378 smbios_anchor, smbios_anchor_len); 379 } 380 } 381 382 static void virt_machine_done(Notifier *notifier, void *data) 383 { 384 LoongArchMachineState *lams = container_of(notifier, 385 LoongArchMachineState, machine_done); 386 virt_build_smbios(lams); 387 loongarch_acpi_setup(lams); 388 } 389 390 static void virt_powerdown_req(Notifier *notifier, void *opaque) 391 { 392 LoongArchMachineState *s = container_of(notifier, 393 LoongArchMachineState, powerdown_notifier); 394 395 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 396 } 397 398 struct memmap_entry *memmap_table; 399 unsigned memmap_entries; 400 401 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 402 { 403 /* Ensure there are no duplicate entries. */ 404 for (unsigned i = 0; i < memmap_entries; i++) { 405 assert(memmap_table[i].address != address); 406 } 407 408 memmap_table = g_renew(struct memmap_entry, memmap_table, 409 memmap_entries + 1); 410 memmap_table[memmap_entries].address = cpu_to_le64(address); 411 memmap_table[memmap_entries].length = cpu_to_le64(length); 412 memmap_table[memmap_entries].type = cpu_to_le32(type); 413 memmap_table[memmap_entries].reserved = 0; 414 memmap_entries++; 415 } 416 417 static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams) 418 { 419 DeviceState *dev; 420 MachineState *ms = MACHINE(lams); 421 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 422 423 if (ms->ram_slots) { 424 event |= ACPI_GED_MEM_HOTPLUG_EVT; 425 } 426 dev = qdev_new(TYPE_ACPI_GED); 427 qdev_prop_set_uint32(dev, "ged-event", event); 428 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 429 430 /* ged event */ 431 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 432 /* memory hotplug */ 433 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 434 /* ged regs used for reset and power down */ 435 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 436 437 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 438 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 439 return dev; 440 } 441 442 static DeviceState *create_platform_bus(DeviceState *pch_pic) 443 { 444 DeviceState *dev; 445 SysBusDevice *sysbus; 446 int i, irq; 447 MemoryRegion *sysmem = get_system_memory(); 448 449 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 450 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 451 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 452 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 453 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 454 455 sysbus = SYS_BUS_DEVICE(dev); 456 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 457 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 458 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 459 } 460 461 memory_region_add_subregion(sysmem, 462 VIRT_PLATFORM_BUS_BASEADDRESS, 463 sysbus_mmio_get_region(sysbus, 0)); 464 return dev; 465 } 466 467 static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams) 468 { 469 MachineClass *mc = MACHINE_GET_CLASS(lams); 470 DeviceState *gpex_dev; 471 SysBusDevice *d; 472 PCIBus *pci_bus; 473 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 474 MemoryRegion *mmio_alias, *mmio_reg; 475 int i; 476 477 gpex_dev = qdev_new(TYPE_GPEX_HOST); 478 d = SYS_BUS_DEVICE(gpex_dev); 479 sysbus_realize_and_unref(d, &error_fatal); 480 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 481 lams->pci_bus = pci_bus; 482 483 /* Map only part size_ecam bytes of ECAM space */ 484 ecam_alias = g_new0(MemoryRegion, 1); 485 ecam_reg = sysbus_mmio_get_region(d, 0); 486 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 487 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 488 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 489 ecam_alias); 490 491 /* Map PCI mem space */ 492 mmio_alias = g_new0(MemoryRegion, 1); 493 mmio_reg = sysbus_mmio_get_region(d, 1); 494 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 495 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 496 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 497 mmio_alias); 498 499 /* Map PCI IO port space. */ 500 pio_alias = g_new0(MemoryRegion, 1); 501 pio_reg = sysbus_mmio_get_region(d, 2); 502 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 503 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 504 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 505 pio_alias); 506 507 for (i = 0; i < GPEX_NUM_IRQS; i++) { 508 sysbus_connect_irq(d, i, 509 qdev_get_gpio_in(pch_pic, 16 + i)); 510 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 511 } 512 513 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 514 qdev_get_gpio_in(pch_pic, 515 VIRT_UART_IRQ - VIRT_GSI_BASE), 516 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 517 fdt_add_uart_node(lams); 518 519 /* Network init */ 520 pci_init_nic_devices(pci_bus, mc->default_nic); 521 522 /* 523 * There are some invalid guest memory access. 524 * Create some unimplemented devices to emulate this. 525 */ 526 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 527 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 528 qdev_get_gpio_in(pch_pic, 529 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 530 fdt_add_rtc_node(lams); 531 532 /* acpi ged */ 533 lams->acpi_ged = create_acpi_ged(pch_pic, lams); 534 /* platform bus */ 535 lams->platform_bus_dev = create_platform_bus(pch_pic); 536 } 537 538 static void loongarch_irq_init(LoongArchMachineState *lams) 539 { 540 MachineState *ms = MACHINE(lams); 541 DeviceState *pch_pic, *pch_msi, *cpudev; 542 DeviceState *ipi, *extioi; 543 SysBusDevice *d; 544 LoongArchCPU *lacpu; 545 CPULoongArchState *env; 546 CPUState *cpu_state; 547 int cpu, pin, i, start, num; 548 uint32_t cpuintc_phandle; 549 550 /* 551 * The connection of interrupts: 552 * +-----+ +---------+ +-------+ 553 * | IPI |--> | CPUINTC | <-- | Timer | 554 * +-----+ +---------+ +-------+ 555 * ^ 556 * | 557 * +---------+ 558 * | EIOINTC | 559 * +---------+ 560 * ^ ^ 561 * | | 562 * +---------+ +---------+ 563 * | PCH-PIC | | PCH-MSI | 564 * +---------+ +---------+ 565 * ^ ^ ^ 566 * | | | 567 * +--------+ +---------+ +---------+ 568 * | UARTs | | Devices | | Devices | 569 * +--------+ +---------+ +---------+ 570 */ 571 572 /* Create IPI device */ 573 ipi = qdev_new(TYPE_LOONGARCH_IPI); 574 qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); 575 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 576 577 /* IPI iocsr memory region */ 578 memory_region_add_subregion(&lams->system_iocsr, SMP_IPI_MAILBOX, 579 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); 580 memory_region_add_subregion(&lams->system_iocsr, MAIL_SEND_ADDR, 581 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); 582 583 /* Add cpu interrupt-controller */ 584 fdt_add_cpuic_node(lams, &cpuintc_phandle); 585 586 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 587 cpu_state = qemu_get_cpu(cpu); 588 cpudev = DEVICE(cpu_state); 589 lacpu = LOONGARCH_CPU(cpu_state); 590 env = &(lacpu->env); 591 env->address_space_iocsr = &lams->as_iocsr; 592 593 /* connect ipi irq to cpu irq */ 594 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); 595 env->ipistate = ipi; 596 } 597 598 /* Create EXTIOI device */ 599 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 600 qdev_prop_set_uint32(extioi, "num-cpu", ms->smp.cpus); 601 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 602 memory_region_add_subregion(&lams->system_iocsr, APIC_BASE, 603 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); 604 605 /* 606 * connect ext irq to the cpu irq 607 * cpu_pin[9:2] <= intc_pin[7:0] 608 */ 609 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 610 cpudev = DEVICE(qemu_get_cpu(cpu)); 611 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 612 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 613 qdev_get_gpio_in(cpudev, pin + 2)); 614 } 615 } 616 617 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 618 num = VIRT_PCH_PIC_IRQ_NUM; 619 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 620 d = SYS_BUS_DEVICE(pch_pic); 621 sysbus_realize_and_unref(d, &error_fatal); 622 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 623 sysbus_mmio_get_region(d, 0)); 624 memory_region_add_subregion(get_system_memory(), 625 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 626 sysbus_mmio_get_region(d, 1)); 627 memory_region_add_subregion(get_system_memory(), 628 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 629 sysbus_mmio_get_region(d, 2)); 630 631 /* Connect pch_pic irqs to extioi */ 632 for (i = 0; i < num; i++) { 633 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 634 } 635 636 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 637 start = num; 638 num = EXTIOI_IRQS - start; 639 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 640 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 641 d = SYS_BUS_DEVICE(pch_msi); 642 sysbus_realize_and_unref(d, &error_fatal); 643 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 644 for (i = 0; i < num; i++) { 645 /* Connect pch_msi irqs to extioi */ 646 qdev_connect_gpio_out(DEVICE(d), i, 647 qdev_get_gpio_in(extioi, i + start)); 648 } 649 650 loongarch_devices_init(pch_pic, lams); 651 } 652 653 static void loongarch_firmware_init(LoongArchMachineState *lams) 654 { 655 char *filename = MACHINE(lams)->firmware; 656 char *bios_name = NULL; 657 int bios_size, i; 658 BlockBackend *pflash_blk0; 659 MemoryRegion *mr; 660 661 lams->bios_loaded = false; 662 663 /* Map legacy -drive if=pflash to machine properties */ 664 for (i = 0; i < ARRAY_SIZE(lams->flash); i++) { 665 pflash_cfi01_legacy_drive(lams->flash[i], 666 drive_get(IF_PFLASH, 0, i)); 667 } 668 669 virt_flash_map(lams, get_system_memory()); 670 671 pflash_blk0 = pflash_cfi01_get_blk(lams->flash[0]); 672 673 if (pflash_blk0) { 674 if (filename) { 675 error_report("cannot use both '-bios' and '-drive if=pflash'" 676 "options at once"); 677 exit(1); 678 } 679 lams->bios_loaded = true; 680 return; 681 } 682 683 if (filename) { 684 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 685 if (!bios_name) { 686 error_report("Could not find ROM image '%s'", filename); 687 exit(1); 688 } 689 690 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lams->flash[0]), 0); 691 bios_size = load_image_mr(bios_name, mr); 692 if (bios_size < 0) { 693 error_report("Could not load ROM image '%s'", bios_name); 694 exit(1); 695 } 696 g_free(bios_name); 697 lams->bios_loaded = true; 698 } 699 } 700 701 702 static void loongarch_qemu_write(void *opaque, hwaddr addr, 703 uint64_t val, unsigned size) 704 { 705 } 706 707 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) 708 { 709 switch (addr) { 710 case VERSION_REG: 711 return 0x11ULL; 712 case FEATURE_REG: 713 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 714 1ULL << IOCSRF_CSRIPI; 715 case VENDOR_REG: 716 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 717 case CPUNAME_REG: 718 return 0x303030354133ULL; /* "3A5000" */ 719 case MISC_FUNC_REG: 720 return 1ULL << IOCSRM_EXTIOI_EN; 721 } 722 return 0ULL; 723 } 724 725 static const MemoryRegionOps loongarch_qemu_ops = { 726 .read = loongarch_qemu_read, 727 .write = loongarch_qemu_write, 728 .endianness = DEVICE_LITTLE_ENDIAN, 729 .valid = { 730 .min_access_size = 4, 731 .max_access_size = 8, 732 }, 733 .impl = { 734 .min_access_size = 8, 735 .max_access_size = 8, 736 }, 737 }; 738 739 static void loongarch_init(MachineState *machine) 740 { 741 LoongArchCPU *lacpu; 742 const char *cpu_model = machine->cpu_type; 743 ram_addr_t offset = 0; 744 ram_addr_t ram_size = machine->ram_size; 745 uint64_t highram_size = 0, phyAddr = 0; 746 MemoryRegion *address_space_mem = get_system_memory(); 747 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 748 int nb_numa_nodes = machine->numa_state->num_nodes; 749 NodeInfo *numa_info = machine->numa_state->nodes; 750 int i; 751 const CPUArchIdList *possible_cpus; 752 MachineClass *mc = MACHINE_GET_CLASS(machine); 753 CPUState *cpu; 754 char *ramName = NULL; 755 756 if (!cpu_model) { 757 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 758 } 759 760 if (ram_size < 1 * GiB) { 761 error_report("ram_size must be greater than 1G."); 762 exit(1); 763 } 764 create_fdt(lams); 765 766 /* Create IOCSR space */ 767 memory_region_init_io(&lams->system_iocsr, OBJECT(machine), NULL, 768 machine, "iocsr", UINT64_MAX); 769 address_space_init(&lams->as_iocsr, &lams->system_iocsr, "IOCSR"); 770 memory_region_init_io(&lams->iocsr_mem, OBJECT(machine), 771 &loongarch_qemu_ops, 772 machine, "iocsr_misc", 0x428); 773 memory_region_add_subregion(&lams->system_iocsr, 0, &lams->iocsr_mem); 774 775 /* Init CPUs */ 776 possible_cpus = mc->possible_cpu_arch_ids(machine); 777 for (i = 0; i < possible_cpus->len; i++) { 778 cpu = cpu_create(machine->cpu_type); 779 cpu->cpu_index = i; 780 machine->possible_cpus->cpus[i].cpu = cpu; 781 lacpu = LOONGARCH_CPU(cpu); 782 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; 783 } 784 fdt_add_cpu_nodes(lams); 785 786 /* Node0 memory */ 787 memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1); 788 fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0); 789 memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram", 790 machine->ram, offset, VIRT_LOWMEM_SIZE); 791 memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem); 792 793 offset += VIRT_LOWMEM_SIZE; 794 if (nb_numa_nodes > 0) { 795 assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE); 796 highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE; 797 } else { 798 highram_size = ram_size - VIRT_LOWMEM_SIZE; 799 } 800 phyAddr = VIRT_HIGHMEM_BASE; 801 memmap_add_entry(phyAddr, highram_size, 1); 802 fdt_add_memory_node(machine, phyAddr, highram_size, 0); 803 memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram", 804 machine->ram, offset, highram_size); 805 memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem); 806 807 /* Node1 - Nodemax memory */ 808 offset += highram_size; 809 phyAddr += highram_size; 810 811 for (i = 1; i < nb_numa_nodes; i++) { 812 MemoryRegion *nodemem = g_new(MemoryRegion, 1); 813 ramName = g_strdup_printf("loongarch.node%d.ram", i); 814 memory_region_init_alias(nodemem, NULL, ramName, machine->ram, 815 offset, numa_info[i].node_mem); 816 memory_region_add_subregion(address_space_mem, phyAddr, nodemem); 817 memmap_add_entry(phyAddr, numa_info[i].node_mem, 1); 818 fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i); 819 offset += numa_info[i].node_mem; 820 phyAddr += numa_info[i].node_mem; 821 } 822 823 /* initialize device memory address space */ 824 if (machine->ram_size < machine->maxram_size) { 825 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 826 hwaddr device_mem_base; 827 828 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 829 error_report("unsupported amount of memory slots: %"PRIu64, 830 machine->ram_slots); 831 exit(EXIT_FAILURE); 832 } 833 834 if (QEMU_ALIGN_UP(machine->maxram_size, 835 TARGET_PAGE_SIZE) != machine->maxram_size) { 836 error_report("maximum memory size must by aligned to multiple of " 837 "%d bytes", TARGET_PAGE_SIZE); 838 exit(EXIT_FAILURE); 839 } 840 /* device memory base is the top of high memory address. */ 841 device_mem_base = ROUND_UP(VIRT_HIGHMEM_BASE + highram_size, 1 * GiB); 842 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 843 } 844 845 /* load the BIOS image. */ 846 loongarch_firmware_init(lams); 847 848 /* fw_cfg init */ 849 lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine); 850 rom_set_fw(lams->fw_cfg); 851 if (lams->fw_cfg != NULL) { 852 fw_cfg_add_file(lams->fw_cfg, "etc/memmap", 853 memmap_table, 854 sizeof(struct memmap_entry) * (memmap_entries)); 855 } 856 fdt_add_fw_cfg_node(lams); 857 fdt_add_flash_node(lams); 858 859 /* Initialize the IO interrupt subsystem */ 860 loongarch_irq_init(lams); 861 fdt_add_irqchip_node(lams); 862 platform_bus_add_all_fdt_nodes(machine->fdt, "/intc", 863 VIRT_PLATFORM_BUS_BASEADDRESS, 864 VIRT_PLATFORM_BUS_SIZE, 865 VIRT_PLATFORM_BUS_IRQ); 866 lams->machine_done.notify = virt_machine_done; 867 qemu_add_machine_init_done_notifier(&lams->machine_done); 868 /* connect powerdown request */ 869 lams->powerdown_notifier.notify = virt_powerdown_req; 870 qemu_register_powerdown_notifier(&lams->powerdown_notifier); 871 872 fdt_add_pcie_node(lams); 873 /* 874 * Since lowmem region starts from 0 and Linux kernel legacy start address 875 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer 876 * access. FDT size limit with 1 MiB. 877 * Put the FDT into the memory map as a ROM image: this will ensure 878 * the FDT is copied again upon reset, even if addr points into RAM. 879 */ 880 qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size); 881 rom_add_blob_fixed_as("fdt", machine->fdt, lams->fdt_size, FDT_BASE, 882 &address_space_memory); 883 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 884 rom_ptr_for_as(&address_space_memory, FDT_BASE, lams->fdt_size)); 885 886 lams->bootinfo.ram_size = ram_size; 887 loongarch_load_kernel(machine, &lams->bootinfo); 888 } 889 890 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) 891 { 892 if (lams->acpi == ON_OFF_AUTO_OFF) { 893 return false; 894 } 895 return true; 896 } 897 898 static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, 899 void *opaque, Error **errp) 900 { 901 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 902 OnOffAuto acpi = lams->acpi; 903 904 visit_type_OnOffAuto(v, name, &acpi, errp); 905 } 906 907 static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, 908 void *opaque, Error **errp) 909 { 910 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 911 912 visit_type_OnOffAuto(v, name, &lams->acpi, errp); 913 } 914 915 static void loongarch_machine_initfn(Object *obj) 916 { 917 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 918 919 lams->acpi = ON_OFF_AUTO_AUTO; 920 lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 921 lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 922 virt_flash_create(lams); 923 } 924 925 static bool memhp_type_supported(DeviceState *dev) 926 { 927 /* we only support pc dimm now */ 928 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 929 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 930 } 931 932 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 933 Error **errp) 934 { 935 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 936 } 937 938 static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev, 939 DeviceState *dev, Error **errp) 940 { 941 if (memhp_type_supported(dev)) { 942 virt_mem_pre_plug(hotplug_dev, dev, errp); 943 } 944 } 945 946 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 947 DeviceState *dev, Error **errp) 948 { 949 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 950 951 /* the acpi ged is always exist */ 952 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lams->acpi_ged), dev, 953 errp); 954 } 955 956 static void virt_machine_device_unplug_request(HotplugHandler *hotplug_dev, 957 DeviceState *dev, Error **errp) 958 { 959 if (memhp_type_supported(dev)) { 960 virt_mem_unplug_request(hotplug_dev, dev, errp); 961 } 962 } 963 964 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 965 DeviceState *dev, Error **errp) 966 { 967 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 968 969 hotplug_handler_unplug(HOTPLUG_HANDLER(lams->acpi_ged), dev, errp); 970 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lams)); 971 qdev_unrealize(dev); 972 } 973 974 static void virt_machine_device_unplug(HotplugHandler *hotplug_dev, 975 DeviceState *dev, Error **errp) 976 { 977 if (memhp_type_supported(dev)) { 978 virt_mem_unplug(hotplug_dev, dev, errp); 979 } 980 } 981 982 static void virt_mem_plug(HotplugHandler *hotplug_dev, 983 DeviceState *dev, Error **errp) 984 { 985 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 986 987 pc_dimm_plug(PC_DIMM(dev), MACHINE(lams)); 988 hotplug_handler_plug(HOTPLUG_HANDLER(lams->acpi_ged), 989 dev, &error_abort); 990 } 991 992 static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev, 993 DeviceState *dev, Error **errp) 994 { 995 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 996 MachineClass *mc = MACHINE_GET_CLASS(lams); 997 998 if (device_is_dynamic_sysbus(mc, dev)) { 999 if (lams->platform_bus_dev) { 1000 platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev), 1001 SYS_BUS_DEVICE(dev)); 1002 } 1003 } else if (memhp_type_supported(dev)) { 1004 virt_mem_plug(hotplug_dev, dev, errp); 1005 } 1006 } 1007 1008 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1009 DeviceState *dev) 1010 { 1011 MachineClass *mc = MACHINE_GET_CLASS(machine); 1012 1013 if (device_is_dynamic_sysbus(mc, dev) || 1014 memhp_type_supported(dev)) { 1015 return HOTPLUG_HANDLER(machine); 1016 } 1017 return NULL; 1018 } 1019 1020 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1021 { 1022 int n; 1023 unsigned int max_cpus = ms->smp.max_cpus; 1024 1025 if (ms->possible_cpus) { 1026 assert(ms->possible_cpus->len == max_cpus); 1027 return ms->possible_cpus; 1028 } 1029 1030 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1031 sizeof(CPUArchId) * max_cpus); 1032 ms->possible_cpus->len = max_cpus; 1033 for (n = 0; n < ms->possible_cpus->len; n++) { 1034 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1035 ms->possible_cpus->cpus[n].arch_id = n; 1036 1037 ms->possible_cpus->cpus[n].props.has_socket_id = true; 1038 ms->possible_cpus->cpus[n].props.socket_id = 1039 n / (ms->smp.cores * ms->smp.threads); 1040 ms->possible_cpus->cpus[n].props.has_core_id = true; 1041 ms->possible_cpus->cpus[n].props.core_id = 1042 n / ms->smp.threads % ms->smp.cores; 1043 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1044 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 1045 } 1046 return ms->possible_cpus; 1047 } 1048 1049 static CpuInstanceProperties 1050 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1051 { 1052 MachineClass *mc = MACHINE_GET_CLASS(ms); 1053 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1054 1055 assert(cpu_index < possible_cpus->len); 1056 return possible_cpus->cpus[cpu_index].props; 1057 } 1058 1059 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1060 { 1061 int64_t nidx = 0; 1062 1063 if (ms->numa_state->num_nodes) { 1064 nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes); 1065 if (ms->numa_state->num_nodes <= nidx) { 1066 nidx = ms->numa_state->num_nodes - 1; 1067 } 1068 } 1069 return nidx; 1070 } 1071 1072 static void loongarch_class_init(ObjectClass *oc, void *data) 1073 { 1074 MachineClass *mc = MACHINE_CLASS(oc); 1075 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1076 1077 mc->desc = "Loongson-3A5000 LS7A1000 machine"; 1078 mc->init = loongarch_init; 1079 mc->default_ram_size = 1 * GiB; 1080 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 1081 mc->default_ram_id = "loongarch.ram"; 1082 mc->max_cpus = LOONGARCH_MAX_CPUS; 1083 mc->is_default = 1; 1084 mc->default_kernel_irqchip_split = false; 1085 mc->block_default_type = IF_VIRTIO; 1086 mc->default_boot_order = "c"; 1087 mc->no_cdrom = 1; 1088 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1089 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1090 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1091 mc->numa_mem_supported = true; 1092 mc->auto_enable_numa_with_memhp = true; 1093 mc->auto_enable_numa_with_memdev = true; 1094 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1095 mc->default_nic = "virtio-net-pci"; 1096 hc->plug = loongarch_machine_device_plug_cb; 1097 hc->pre_plug = virt_machine_device_pre_plug; 1098 hc->unplug_request = virt_machine_device_unplug_request; 1099 hc->unplug = virt_machine_device_unplug; 1100 1101 object_class_property_add(oc, "acpi", "OnOffAuto", 1102 loongarch_get_acpi, loongarch_set_acpi, 1103 NULL, NULL); 1104 object_class_property_set_description(oc, "acpi", 1105 "Enable ACPI"); 1106 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1107 #ifdef CONFIG_TPM 1108 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1109 #endif 1110 } 1111 1112 static const TypeInfo loongarch_machine_types[] = { 1113 { 1114 .name = TYPE_LOONGARCH_MACHINE, 1115 .parent = TYPE_MACHINE, 1116 .instance_size = sizeof(LoongArchMachineState), 1117 .class_init = loongarch_class_init, 1118 .instance_init = loongarch_machine_initfn, 1119 .interfaces = (InterfaceInfo[]) { 1120 { TYPE_HOTPLUG_HANDLER }, 1121 { } 1122 }, 1123 } 1124 }; 1125 1126 DEFINE_TYPES(loongarch_machine_types) 1127