1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/sysemu.h" 14 #include "sysemu/qtest.h" 15 #include "sysemu/runstate.h" 16 #include "sysemu/reset.h" 17 #include "sysemu/rtc.h" 18 #include "hw/loongarch/virt.h" 19 #include "exec/address-spaces.h" 20 #include "hw/irq.h" 21 #include "net/net.h" 22 #include "hw/loader.h" 23 #include "elf.h" 24 #include "hw/intc/loongarch_ipi.h" 25 #include "hw/intc/loongarch_extioi.h" 26 #include "hw/intc/loongarch_pch_pic.h" 27 #include "hw/intc/loongarch_pch_msi.h" 28 #include "hw/pci-host/ls7a.h" 29 #include "hw/pci-host/gpex.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/loongarch/fw_cfg.h" 32 #include "target/loongarch/cpu.h" 33 #include "hw/firmware/smbios.h" 34 #include "hw/acpi/aml-build.h" 35 #include "qapi/qapi-visit-common.h" 36 #include "hw/acpi/generic_event_device.h" 37 #include "hw/mem/nvdimm.h" 38 #include "sysemu/device_tree.h" 39 #include <libfdt.h> 40 #include "hw/core/sysbus-fdt.h" 41 #include "hw/platform-bus.h" 42 #include "hw/display/ramfb.h" 43 #include "hw/mem/pc-dimm.h" 44 #include "sysemu/tpm.h" 45 #include "sysemu/block-backend.h" 46 #include "hw/block/flash.h" 47 #include "qemu/error-report.h" 48 49 static PFlashCFI01 *virt_flash_create1(LoongArchMachineState *lams, 50 const char *name, 51 const char *alias_prop_name) 52 { 53 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 54 55 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 56 qdev_prop_set_uint8(dev, "width", 4); 57 qdev_prop_set_uint8(dev, "device-width", 2); 58 qdev_prop_set_bit(dev, "big-endian", false); 59 qdev_prop_set_uint16(dev, "id0", 0x89); 60 qdev_prop_set_uint16(dev, "id1", 0x18); 61 qdev_prop_set_uint16(dev, "id2", 0x00); 62 qdev_prop_set_uint16(dev, "id3", 0x00); 63 qdev_prop_set_string(dev, "name", name); 64 object_property_add_child(OBJECT(lams), name, OBJECT(dev)); 65 object_property_add_alias(OBJECT(lams), alias_prop_name, 66 OBJECT(dev), "drive"); 67 return PFLASH_CFI01(dev); 68 } 69 70 static void virt_flash_create(LoongArchMachineState *lams) 71 { 72 lams->flash[0] = virt_flash_create1(lams, "virt.flash0", "pflash0"); 73 lams->flash[1] = virt_flash_create1(lams, "virt.flash1", "pflash1"); 74 } 75 76 static void virt_flash_map1(PFlashCFI01 *flash, 77 hwaddr base, hwaddr size, 78 MemoryRegion *sysmem) 79 { 80 DeviceState *dev = DEVICE(flash); 81 BlockBackend *blk; 82 hwaddr real_size = size; 83 84 blk = pflash_cfi01_get_blk(flash); 85 if (blk) { 86 real_size = blk_getlength(blk); 87 assert(real_size && real_size <= size); 88 } 89 90 assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE)); 91 assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 92 93 qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE); 94 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 95 memory_region_add_subregion(sysmem, base, 96 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 97 } 98 99 static void virt_flash_map(LoongArchMachineState *lams, 100 MemoryRegion *sysmem) 101 { 102 PFlashCFI01 *flash0 = lams->flash[0]; 103 PFlashCFI01 *flash1 = lams->flash[1]; 104 105 virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem); 106 virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem); 107 } 108 109 static void fdt_add_cpuic_node(LoongArchMachineState *lams, 110 uint32_t *cpuintc_phandle) 111 { 112 MachineState *ms = MACHINE(lams); 113 char *nodename; 114 115 *cpuintc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 116 nodename = g_strdup_printf("/cpuic"); 117 qemu_fdt_add_subnode(ms->fdt, nodename); 118 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *cpuintc_phandle); 119 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 120 "loongson,cpu-interrupt-controller"); 121 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 122 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 123 g_free(nodename); 124 } 125 126 static void fdt_add_eiointc_node(LoongArchMachineState *lams, 127 uint32_t *cpuintc_phandle, 128 uint32_t *eiointc_phandle) 129 { 130 MachineState *ms = MACHINE(lams); 131 char *nodename; 132 hwaddr extioi_base = APIC_BASE; 133 hwaddr extioi_size = EXTIOI_SIZE; 134 135 *eiointc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 136 nodename = g_strdup_printf("/eiointc@%" PRIx64, extioi_base); 137 qemu_fdt_add_subnode(ms->fdt, nodename); 138 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *eiointc_phandle); 139 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 140 "loongson,ls2k2000-eiointc"); 141 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 142 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 143 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 144 *cpuintc_phandle); 145 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", 3); 146 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, 147 extioi_base, 0x0, extioi_size); 148 g_free(nodename); 149 } 150 151 static void fdt_add_flash_node(LoongArchMachineState *lams) 152 { 153 MachineState *ms = MACHINE(lams); 154 char *nodename; 155 MemoryRegion *flash_mem; 156 157 hwaddr flash0_base; 158 hwaddr flash0_size; 159 160 hwaddr flash1_base; 161 hwaddr flash1_size; 162 163 flash_mem = pflash_cfi01_get_memory(lams->flash[0]); 164 flash0_base = flash_mem->addr; 165 flash0_size = memory_region_size(flash_mem); 166 167 flash_mem = pflash_cfi01_get_memory(lams->flash[1]); 168 flash1_base = flash_mem->addr; 169 flash1_size = memory_region_size(flash_mem); 170 171 nodename = g_strdup_printf("/flash@%" PRIx64, flash0_base); 172 qemu_fdt_add_subnode(ms->fdt, nodename); 173 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 174 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 175 2, flash0_base, 2, flash0_size, 176 2, flash1_base, 2, flash1_size); 177 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 178 g_free(nodename); 179 } 180 181 static void fdt_add_rtc_node(LoongArchMachineState *lams) 182 { 183 char *nodename; 184 hwaddr base = VIRT_RTC_REG_BASE; 185 hwaddr size = VIRT_RTC_LEN; 186 MachineState *ms = MACHINE(lams); 187 188 nodename = g_strdup_printf("/rtc@%" PRIx64, base); 189 qemu_fdt_add_subnode(ms->fdt, nodename); 190 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc"); 191 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 192 g_free(nodename); 193 } 194 195 static void fdt_add_uart_node(LoongArchMachineState *lams) 196 { 197 char *nodename; 198 hwaddr base = VIRT_UART_BASE; 199 hwaddr size = VIRT_UART_SIZE; 200 MachineState *ms = MACHINE(lams); 201 202 nodename = g_strdup_printf("/serial@%" PRIx64, base); 203 qemu_fdt_add_subnode(ms->fdt, nodename); 204 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); 205 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); 206 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); 207 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 208 g_free(nodename); 209 } 210 211 static void create_fdt(LoongArchMachineState *lams) 212 { 213 MachineState *ms = MACHINE(lams); 214 215 ms->fdt = create_device_tree(&lams->fdt_size); 216 if (!ms->fdt) { 217 error_report("create_device_tree() failed"); 218 exit(1); 219 } 220 221 /* Header */ 222 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 223 "linux,dummy-loongson3"); 224 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 225 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 226 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 227 } 228 229 static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) 230 { 231 int num; 232 const MachineState *ms = MACHINE(lams); 233 int smp_cpus = ms->smp.cpus; 234 235 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 236 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 237 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 238 239 /* cpu nodes */ 240 for (num = smp_cpus - 1; num >= 0; num--) { 241 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 242 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 243 CPUState *cs = CPU(cpu); 244 245 qemu_fdt_add_subnode(ms->fdt, nodename); 246 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 247 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 248 cpu->dtb_compatible); 249 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 250 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 251 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 252 } 253 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 254 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 255 qemu_fdt_alloc_phandle(ms->fdt)); 256 g_free(nodename); 257 } 258 259 /*cpu map */ 260 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 261 262 for (num = smp_cpus - 1; num >= 0; num--) { 263 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 264 char *map_path; 265 266 if (ms->smp.threads > 1) { 267 map_path = g_strdup_printf( 268 "/cpus/cpu-map/socket%d/core%d/thread%d", 269 num / (ms->smp.cores * ms->smp.threads), 270 (num / ms->smp.threads) % ms->smp.cores, 271 num % ms->smp.threads); 272 } else { 273 map_path = g_strdup_printf( 274 "/cpus/cpu-map/socket%d/core%d", 275 num / ms->smp.cores, 276 num % ms->smp.cores); 277 } 278 qemu_fdt_add_path(ms->fdt, map_path); 279 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 280 281 g_free(map_path); 282 g_free(cpu_path); 283 } 284 } 285 286 static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) 287 { 288 char *nodename; 289 hwaddr base = VIRT_FWCFG_BASE; 290 const MachineState *ms = MACHINE(lams); 291 292 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 293 qemu_fdt_add_subnode(ms->fdt, nodename); 294 qemu_fdt_setprop_string(ms->fdt, nodename, 295 "compatible", "qemu,fw-cfg-mmio"); 296 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 297 2, base, 2, 0x18); 298 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 299 g_free(nodename); 300 } 301 302 static void fdt_add_pcie_node(const LoongArchMachineState *lams) 303 { 304 char *nodename; 305 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 306 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 307 hwaddr base_pio = VIRT_PCI_IO_BASE; 308 hwaddr size_pio = VIRT_PCI_IO_SIZE; 309 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 310 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 311 hwaddr base = base_pcie; 312 313 const MachineState *ms = MACHINE(lams); 314 315 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 316 qemu_fdt_add_subnode(ms->fdt, nodename); 317 qemu_fdt_setprop_string(ms->fdt, nodename, 318 "compatible", "pci-host-ecam-generic"); 319 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 320 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 321 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 322 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 323 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 324 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 325 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 326 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 327 2, base_pcie, 2, size_pcie); 328 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 329 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 330 2, base_pio, 2, size_pio, 331 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 332 2, base_mmio, 2, size_mmio); 333 g_free(nodename); 334 } 335 336 static void fdt_add_irqchip_node(LoongArchMachineState *lams) 337 { 338 MachineState *ms = MACHINE(lams); 339 char *nodename; 340 uint32_t irqchip_phandle; 341 342 irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt); 343 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle); 344 345 nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE); 346 qemu_fdt_add_subnode(ms->fdt, nodename); 347 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 348 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 349 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 350 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 351 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 352 353 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 354 "loongarch,ls7a"); 355 356 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 357 2, VIRT_IOAPIC_REG_BASE, 358 2, PCH_PIC_ROUTE_ENTRY_OFFSET); 359 360 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle); 361 g_free(nodename); 362 } 363 364 static void fdt_add_memory_node(MachineState *ms, 365 uint64_t base, uint64_t size, int node_id) 366 { 367 char *nodename = g_strdup_printf("/memory@%" PRIx64, base); 368 369 qemu_fdt_add_subnode(ms->fdt, nodename); 370 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, 0, size); 371 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 372 373 if (ms->numa_state && ms->numa_state->num_nodes) { 374 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); 375 } 376 377 g_free(nodename); 378 } 379 380 static void virt_build_smbios(LoongArchMachineState *lams) 381 { 382 MachineState *ms = MACHINE(lams); 383 MachineClass *mc = MACHINE_GET_CLASS(lams); 384 uint8_t *smbios_tables, *smbios_anchor; 385 size_t smbios_tables_len, smbios_anchor_len; 386 const char *product = "QEMU Virtual Machine"; 387 388 if (!lams->fw_cfg) { 389 return; 390 } 391 392 smbios_set_defaults("QEMU", product, mc->name, true); 393 394 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 395 NULL, 0, 396 &smbios_tables, &smbios_tables_len, 397 &smbios_anchor, &smbios_anchor_len, &error_fatal); 398 399 if (smbios_anchor) { 400 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", 401 smbios_tables, smbios_tables_len); 402 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", 403 smbios_anchor, smbios_anchor_len); 404 } 405 } 406 407 static void virt_machine_done(Notifier *notifier, void *data) 408 { 409 LoongArchMachineState *lams = container_of(notifier, 410 LoongArchMachineState, machine_done); 411 virt_build_smbios(lams); 412 loongarch_acpi_setup(lams); 413 } 414 415 static void virt_powerdown_req(Notifier *notifier, void *opaque) 416 { 417 LoongArchMachineState *s = container_of(notifier, 418 LoongArchMachineState, powerdown_notifier); 419 420 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 421 } 422 423 struct memmap_entry *memmap_table; 424 unsigned memmap_entries; 425 426 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 427 { 428 /* Ensure there are no duplicate entries. */ 429 for (unsigned i = 0; i < memmap_entries; i++) { 430 assert(memmap_table[i].address != address); 431 } 432 433 memmap_table = g_renew(struct memmap_entry, memmap_table, 434 memmap_entries + 1); 435 memmap_table[memmap_entries].address = cpu_to_le64(address); 436 memmap_table[memmap_entries].length = cpu_to_le64(length); 437 memmap_table[memmap_entries].type = cpu_to_le32(type); 438 memmap_table[memmap_entries].reserved = 0; 439 memmap_entries++; 440 } 441 442 static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams) 443 { 444 DeviceState *dev; 445 MachineState *ms = MACHINE(lams); 446 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 447 448 if (ms->ram_slots) { 449 event |= ACPI_GED_MEM_HOTPLUG_EVT; 450 } 451 dev = qdev_new(TYPE_ACPI_GED); 452 qdev_prop_set_uint32(dev, "ged-event", event); 453 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 454 455 /* ged event */ 456 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 457 /* memory hotplug */ 458 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 459 /* ged regs used for reset and power down */ 460 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 461 462 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 463 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 464 return dev; 465 } 466 467 static DeviceState *create_platform_bus(DeviceState *pch_pic) 468 { 469 DeviceState *dev; 470 SysBusDevice *sysbus; 471 int i, irq; 472 MemoryRegion *sysmem = get_system_memory(); 473 474 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 475 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 476 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 477 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 478 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 479 480 sysbus = SYS_BUS_DEVICE(dev); 481 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 482 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 483 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 484 } 485 486 memory_region_add_subregion(sysmem, 487 VIRT_PLATFORM_BUS_BASEADDRESS, 488 sysbus_mmio_get_region(sysbus, 0)); 489 return dev; 490 } 491 492 static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams) 493 { 494 MachineClass *mc = MACHINE_GET_CLASS(lams); 495 DeviceState *gpex_dev; 496 SysBusDevice *d; 497 PCIBus *pci_bus; 498 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 499 MemoryRegion *mmio_alias, *mmio_reg; 500 int i; 501 502 gpex_dev = qdev_new(TYPE_GPEX_HOST); 503 d = SYS_BUS_DEVICE(gpex_dev); 504 sysbus_realize_and_unref(d, &error_fatal); 505 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 506 lams->pci_bus = pci_bus; 507 508 /* Map only part size_ecam bytes of ECAM space */ 509 ecam_alias = g_new0(MemoryRegion, 1); 510 ecam_reg = sysbus_mmio_get_region(d, 0); 511 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 512 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 513 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 514 ecam_alias); 515 516 /* Map PCI mem space */ 517 mmio_alias = g_new0(MemoryRegion, 1); 518 mmio_reg = sysbus_mmio_get_region(d, 1); 519 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 520 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 521 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 522 mmio_alias); 523 524 /* Map PCI IO port space. */ 525 pio_alias = g_new0(MemoryRegion, 1); 526 pio_reg = sysbus_mmio_get_region(d, 2); 527 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 528 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 529 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 530 pio_alias); 531 532 for (i = 0; i < GPEX_NUM_IRQS; i++) { 533 sysbus_connect_irq(d, i, 534 qdev_get_gpio_in(pch_pic, 16 + i)); 535 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 536 } 537 538 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 539 qdev_get_gpio_in(pch_pic, 540 VIRT_UART_IRQ - VIRT_GSI_BASE), 541 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 542 fdt_add_uart_node(lams); 543 544 /* Network init */ 545 pci_init_nic_devices(pci_bus, mc->default_nic); 546 547 /* 548 * There are some invalid guest memory access. 549 * Create some unimplemented devices to emulate this. 550 */ 551 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 552 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 553 qdev_get_gpio_in(pch_pic, 554 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 555 fdt_add_rtc_node(lams); 556 557 /* acpi ged */ 558 lams->acpi_ged = create_acpi_ged(pch_pic, lams); 559 /* platform bus */ 560 lams->platform_bus_dev = create_platform_bus(pch_pic); 561 } 562 563 static void loongarch_irq_init(LoongArchMachineState *lams) 564 { 565 MachineState *ms = MACHINE(lams); 566 DeviceState *pch_pic, *pch_msi, *cpudev; 567 DeviceState *ipi, *extioi; 568 SysBusDevice *d; 569 LoongArchCPU *lacpu; 570 CPULoongArchState *env; 571 CPUState *cpu_state; 572 int cpu, pin, i, start, num; 573 uint32_t cpuintc_phandle, eiointc_phandle; 574 575 /* 576 * The connection of interrupts: 577 * +-----+ +---------+ +-------+ 578 * | IPI |--> | CPUINTC | <-- | Timer | 579 * +-----+ +---------+ +-------+ 580 * ^ 581 * | 582 * +---------+ 583 * | EIOINTC | 584 * +---------+ 585 * ^ ^ 586 * | | 587 * +---------+ +---------+ 588 * | PCH-PIC | | PCH-MSI | 589 * +---------+ +---------+ 590 * ^ ^ ^ 591 * | | | 592 * +--------+ +---------+ +---------+ 593 * | UARTs | | Devices | | Devices | 594 * +--------+ +---------+ +---------+ 595 */ 596 597 /* Create IPI device */ 598 ipi = qdev_new(TYPE_LOONGARCH_IPI); 599 qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); 600 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 601 602 /* IPI iocsr memory region */ 603 memory_region_add_subregion(&lams->system_iocsr, SMP_IPI_MAILBOX, 604 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); 605 memory_region_add_subregion(&lams->system_iocsr, MAIL_SEND_ADDR, 606 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); 607 608 /* Add cpu interrupt-controller */ 609 fdt_add_cpuic_node(lams, &cpuintc_phandle); 610 611 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 612 cpu_state = qemu_get_cpu(cpu); 613 cpudev = DEVICE(cpu_state); 614 lacpu = LOONGARCH_CPU(cpu_state); 615 env = &(lacpu->env); 616 env->address_space_iocsr = &lams->as_iocsr; 617 618 /* connect ipi irq to cpu irq */ 619 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); 620 env->ipistate = ipi; 621 } 622 623 /* Create EXTIOI device */ 624 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 625 qdev_prop_set_uint32(extioi, "num-cpu", ms->smp.cpus); 626 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 627 memory_region_add_subregion(&lams->system_iocsr, APIC_BASE, 628 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); 629 630 /* 631 * connect ext irq to the cpu irq 632 * cpu_pin[9:2] <= intc_pin[7:0] 633 */ 634 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 635 cpudev = DEVICE(qemu_get_cpu(cpu)); 636 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 637 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 638 qdev_get_gpio_in(cpudev, pin + 2)); 639 } 640 } 641 642 /* Add Extend I/O Interrupt Controller node */ 643 fdt_add_eiointc_node(lams, &cpuintc_phandle, &eiointc_phandle); 644 645 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 646 num = VIRT_PCH_PIC_IRQ_NUM; 647 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 648 d = SYS_BUS_DEVICE(pch_pic); 649 sysbus_realize_and_unref(d, &error_fatal); 650 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 651 sysbus_mmio_get_region(d, 0)); 652 memory_region_add_subregion(get_system_memory(), 653 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 654 sysbus_mmio_get_region(d, 1)); 655 memory_region_add_subregion(get_system_memory(), 656 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 657 sysbus_mmio_get_region(d, 2)); 658 659 /* Connect pch_pic irqs to extioi */ 660 for (i = 0; i < num; i++) { 661 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 662 } 663 664 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 665 start = num; 666 num = EXTIOI_IRQS - start; 667 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 668 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 669 d = SYS_BUS_DEVICE(pch_msi); 670 sysbus_realize_and_unref(d, &error_fatal); 671 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 672 for (i = 0; i < num; i++) { 673 /* Connect pch_msi irqs to extioi */ 674 qdev_connect_gpio_out(DEVICE(d), i, 675 qdev_get_gpio_in(extioi, i + start)); 676 } 677 678 loongarch_devices_init(pch_pic, lams); 679 } 680 681 static void loongarch_firmware_init(LoongArchMachineState *lams) 682 { 683 char *filename = MACHINE(lams)->firmware; 684 char *bios_name = NULL; 685 int bios_size, i; 686 BlockBackend *pflash_blk0; 687 MemoryRegion *mr; 688 689 lams->bios_loaded = false; 690 691 /* Map legacy -drive if=pflash to machine properties */ 692 for (i = 0; i < ARRAY_SIZE(lams->flash); i++) { 693 pflash_cfi01_legacy_drive(lams->flash[i], 694 drive_get(IF_PFLASH, 0, i)); 695 } 696 697 virt_flash_map(lams, get_system_memory()); 698 699 pflash_blk0 = pflash_cfi01_get_blk(lams->flash[0]); 700 701 if (pflash_blk0) { 702 if (filename) { 703 error_report("cannot use both '-bios' and '-drive if=pflash'" 704 "options at once"); 705 exit(1); 706 } 707 lams->bios_loaded = true; 708 return; 709 } 710 711 if (filename) { 712 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 713 if (!bios_name) { 714 error_report("Could not find ROM image '%s'", filename); 715 exit(1); 716 } 717 718 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lams->flash[0]), 0); 719 bios_size = load_image_mr(bios_name, mr); 720 if (bios_size < 0) { 721 error_report("Could not load ROM image '%s'", bios_name); 722 exit(1); 723 } 724 g_free(bios_name); 725 lams->bios_loaded = true; 726 } 727 } 728 729 730 static void loongarch_qemu_write(void *opaque, hwaddr addr, 731 uint64_t val, unsigned size) 732 { 733 } 734 735 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) 736 { 737 switch (addr) { 738 case VERSION_REG: 739 return 0x11ULL; 740 case FEATURE_REG: 741 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 742 1ULL << IOCSRF_CSRIPI; 743 case VENDOR_REG: 744 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 745 case CPUNAME_REG: 746 return 0x303030354133ULL; /* "3A5000" */ 747 case MISC_FUNC_REG: 748 return 1ULL << IOCSRM_EXTIOI_EN; 749 } 750 return 0ULL; 751 } 752 753 static const MemoryRegionOps loongarch_qemu_ops = { 754 .read = loongarch_qemu_read, 755 .write = loongarch_qemu_write, 756 .endianness = DEVICE_LITTLE_ENDIAN, 757 .valid = { 758 .min_access_size = 4, 759 .max_access_size = 8, 760 }, 761 .impl = { 762 .min_access_size = 8, 763 .max_access_size = 8, 764 }, 765 }; 766 767 static void loongarch_init(MachineState *machine) 768 { 769 LoongArchCPU *lacpu; 770 const char *cpu_model = machine->cpu_type; 771 ram_addr_t offset = 0; 772 ram_addr_t ram_size = machine->ram_size; 773 uint64_t highram_size = 0, phyAddr = 0; 774 MemoryRegion *address_space_mem = get_system_memory(); 775 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 776 int nb_numa_nodes = machine->numa_state->num_nodes; 777 NodeInfo *numa_info = machine->numa_state->nodes; 778 int i; 779 const CPUArchIdList *possible_cpus; 780 MachineClass *mc = MACHINE_GET_CLASS(machine); 781 CPUState *cpu; 782 char *ramName = NULL; 783 784 if (!cpu_model) { 785 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 786 } 787 788 if (ram_size < 1 * GiB) { 789 error_report("ram_size must be greater than 1G."); 790 exit(1); 791 } 792 create_fdt(lams); 793 794 /* Create IOCSR space */ 795 memory_region_init_io(&lams->system_iocsr, OBJECT(machine), NULL, 796 machine, "iocsr", UINT64_MAX); 797 address_space_init(&lams->as_iocsr, &lams->system_iocsr, "IOCSR"); 798 memory_region_init_io(&lams->iocsr_mem, OBJECT(machine), 799 &loongarch_qemu_ops, 800 machine, "iocsr_misc", 0x428); 801 memory_region_add_subregion(&lams->system_iocsr, 0, &lams->iocsr_mem); 802 803 /* Init CPUs */ 804 possible_cpus = mc->possible_cpu_arch_ids(machine); 805 for (i = 0; i < possible_cpus->len; i++) { 806 cpu = cpu_create(machine->cpu_type); 807 cpu->cpu_index = i; 808 machine->possible_cpus->cpus[i].cpu = cpu; 809 lacpu = LOONGARCH_CPU(cpu); 810 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; 811 } 812 fdt_add_cpu_nodes(lams); 813 814 /* Node0 memory */ 815 memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1); 816 fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0); 817 memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram", 818 machine->ram, offset, VIRT_LOWMEM_SIZE); 819 memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem); 820 821 offset += VIRT_LOWMEM_SIZE; 822 if (nb_numa_nodes > 0) { 823 assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE); 824 highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE; 825 } else { 826 highram_size = ram_size - VIRT_LOWMEM_SIZE; 827 } 828 phyAddr = VIRT_HIGHMEM_BASE; 829 memmap_add_entry(phyAddr, highram_size, 1); 830 fdt_add_memory_node(machine, phyAddr, highram_size, 0); 831 memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram", 832 machine->ram, offset, highram_size); 833 memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem); 834 835 /* Node1 - Nodemax memory */ 836 offset += highram_size; 837 phyAddr += highram_size; 838 839 for (i = 1; i < nb_numa_nodes; i++) { 840 MemoryRegion *nodemem = g_new(MemoryRegion, 1); 841 ramName = g_strdup_printf("loongarch.node%d.ram", i); 842 memory_region_init_alias(nodemem, NULL, ramName, machine->ram, 843 offset, numa_info[i].node_mem); 844 memory_region_add_subregion(address_space_mem, phyAddr, nodemem); 845 memmap_add_entry(phyAddr, numa_info[i].node_mem, 1); 846 fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i); 847 offset += numa_info[i].node_mem; 848 phyAddr += numa_info[i].node_mem; 849 } 850 851 /* initialize device memory address space */ 852 if (machine->ram_size < machine->maxram_size) { 853 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 854 hwaddr device_mem_base; 855 856 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 857 error_report("unsupported amount of memory slots: %"PRIu64, 858 machine->ram_slots); 859 exit(EXIT_FAILURE); 860 } 861 862 if (QEMU_ALIGN_UP(machine->maxram_size, 863 TARGET_PAGE_SIZE) != machine->maxram_size) { 864 error_report("maximum memory size must by aligned to multiple of " 865 "%d bytes", TARGET_PAGE_SIZE); 866 exit(EXIT_FAILURE); 867 } 868 /* device memory base is the top of high memory address. */ 869 device_mem_base = ROUND_UP(VIRT_HIGHMEM_BASE + highram_size, 1 * GiB); 870 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 871 } 872 873 /* load the BIOS image. */ 874 loongarch_firmware_init(lams); 875 876 /* fw_cfg init */ 877 lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine); 878 rom_set_fw(lams->fw_cfg); 879 if (lams->fw_cfg != NULL) { 880 fw_cfg_add_file(lams->fw_cfg, "etc/memmap", 881 memmap_table, 882 sizeof(struct memmap_entry) * (memmap_entries)); 883 } 884 fdt_add_fw_cfg_node(lams); 885 fdt_add_flash_node(lams); 886 887 /* Initialize the IO interrupt subsystem */ 888 loongarch_irq_init(lams); 889 fdt_add_irqchip_node(lams); 890 platform_bus_add_all_fdt_nodes(machine->fdt, "/intc", 891 VIRT_PLATFORM_BUS_BASEADDRESS, 892 VIRT_PLATFORM_BUS_SIZE, 893 VIRT_PLATFORM_BUS_IRQ); 894 lams->machine_done.notify = virt_machine_done; 895 qemu_add_machine_init_done_notifier(&lams->machine_done); 896 /* connect powerdown request */ 897 lams->powerdown_notifier.notify = virt_powerdown_req; 898 qemu_register_powerdown_notifier(&lams->powerdown_notifier); 899 900 fdt_add_pcie_node(lams); 901 /* 902 * Since lowmem region starts from 0 and Linux kernel legacy start address 903 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer 904 * access. FDT size limit with 1 MiB. 905 * Put the FDT into the memory map as a ROM image: this will ensure 906 * the FDT is copied again upon reset, even if addr points into RAM. 907 */ 908 qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size); 909 rom_add_blob_fixed_as("fdt", machine->fdt, lams->fdt_size, FDT_BASE, 910 &address_space_memory); 911 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 912 rom_ptr_for_as(&address_space_memory, FDT_BASE, lams->fdt_size)); 913 914 lams->bootinfo.ram_size = ram_size; 915 loongarch_load_kernel(machine, &lams->bootinfo); 916 } 917 918 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) 919 { 920 if (lams->acpi == ON_OFF_AUTO_OFF) { 921 return false; 922 } 923 return true; 924 } 925 926 static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, 927 void *opaque, Error **errp) 928 { 929 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 930 OnOffAuto acpi = lams->acpi; 931 932 visit_type_OnOffAuto(v, name, &acpi, errp); 933 } 934 935 static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, 936 void *opaque, Error **errp) 937 { 938 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 939 940 visit_type_OnOffAuto(v, name, &lams->acpi, errp); 941 } 942 943 static void loongarch_machine_initfn(Object *obj) 944 { 945 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 946 947 lams->acpi = ON_OFF_AUTO_AUTO; 948 lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 949 lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 950 virt_flash_create(lams); 951 } 952 953 static bool memhp_type_supported(DeviceState *dev) 954 { 955 /* we only support pc dimm now */ 956 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 957 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 958 } 959 960 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 961 Error **errp) 962 { 963 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 964 } 965 966 static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev, 967 DeviceState *dev, Error **errp) 968 { 969 if (memhp_type_supported(dev)) { 970 virt_mem_pre_plug(hotplug_dev, dev, errp); 971 } 972 } 973 974 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 975 DeviceState *dev, Error **errp) 976 { 977 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 978 979 /* the acpi ged is always exist */ 980 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lams->acpi_ged), dev, 981 errp); 982 } 983 984 static void virt_machine_device_unplug_request(HotplugHandler *hotplug_dev, 985 DeviceState *dev, Error **errp) 986 { 987 if (memhp_type_supported(dev)) { 988 virt_mem_unplug_request(hotplug_dev, dev, errp); 989 } 990 } 991 992 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 993 DeviceState *dev, Error **errp) 994 { 995 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 996 997 hotplug_handler_unplug(HOTPLUG_HANDLER(lams->acpi_ged), dev, errp); 998 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lams)); 999 qdev_unrealize(dev); 1000 } 1001 1002 static void virt_machine_device_unplug(HotplugHandler *hotplug_dev, 1003 DeviceState *dev, Error **errp) 1004 { 1005 if (memhp_type_supported(dev)) { 1006 virt_mem_unplug(hotplug_dev, dev, errp); 1007 } 1008 } 1009 1010 static void virt_mem_plug(HotplugHandler *hotplug_dev, 1011 DeviceState *dev, Error **errp) 1012 { 1013 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1014 1015 pc_dimm_plug(PC_DIMM(dev), MACHINE(lams)); 1016 hotplug_handler_plug(HOTPLUG_HANDLER(lams->acpi_ged), 1017 dev, &error_abort); 1018 } 1019 1020 static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1021 DeviceState *dev, Error **errp) 1022 { 1023 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1024 MachineClass *mc = MACHINE_GET_CLASS(lams); 1025 1026 if (device_is_dynamic_sysbus(mc, dev)) { 1027 if (lams->platform_bus_dev) { 1028 platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev), 1029 SYS_BUS_DEVICE(dev)); 1030 } 1031 } else if (memhp_type_supported(dev)) { 1032 virt_mem_plug(hotplug_dev, dev, errp); 1033 } 1034 } 1035 1036 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1037 DeviceState *dev) 1038 { 1039 MachineClass *mc = MACHINE_GET_CLASS(machine); 1040 1041 if (device_is_dynamic_sysbus(mc, dev) || 1042 memhp_type_supported(dev)) { 1043 return HOTPLUG_HANDLER(machine); 1044 } 1045 return NULL; 1046 } 1047 1048 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1049 { 1050 int n; 1051 unsigned int max_cpus = ms->smp.max_cpus; 1052 1053 if (ms->possible_cpus) { 1054 assert(ms->possible_cpus->len == max_cpus); 1055 return ms->possible_cpus; 1056 } 1057 1058 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1059 sizeof(CPUArchId) * max_cpus); 1060 ms->possible_cpus->len = max_cpus; 1061 for (n = 0; n < ms->possible_cpus->len; n++) { 1062 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1063 ms->possible_cpus->cpus[n].arch_id = n; 1064 1065 ms->possible_cpus->cpus[n].props.has_socket_id = true; 1066 ms->possible_cpus->cpus[n].props.socket_id = 1067 n / (ms->smp.cores * ms->smp.threads); 1068 ms->possible_cpus->cpus[n].props.has_core_id = true; 1069 ms->possible_cpus->cpus[n].props.core_id = 1070 n / ms->smp.threads % ms->smp.cores; 1071 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1072 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 1073 } 1074 return ms->possible_cpus; 1075 } 1076 1077 static CpuInstanceProperties 1078 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1079 { 1080 MachineClass *mc = MACHINE_GET_CLASS(ms); 1081 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1082 1083 assert(cpu_index < possible_cpus->len); 1084 return possible_cpus->cpus[cpu_index].props; 1085 } 1086 1087 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1088 { 1089 int64_t nidx = 0; 1090 1091 if (ms->numa_state->num_nodes) { 1092 nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes); 1093 if (ms->numa_state->num_nodes <= nidx) { 1094 nidx = ms->numa_state->num_nodes - 1; 1095 } 1096 } 1097 return nidx; 1098 } 1099 1100 static void loongarch_class_init(ObjectClass *oc, void *data) 1101 { 1102 MachineClass *mc = MACHINE_CLASS(oc); 1103 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1104 1105 mc->desc = "Loongson-3A5000 LS7A1000 machine"; 1106 mc->init = loongarch_init; 1107 mc->default_ram_size = 1 * GiB; 1108 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 1109 mc->default_ram_id = "loongarch.ram"; 1110 mc->max_cpus = LOONGARCH_MAX_CPUS; 1111 mc->is_default = 1; 1112 mc->default_kernel_irqchip_split = false; 1113 mc->block_default_type = IF_VIRTIO; 1114 mc->default_boot_order = "c"; 1115 mc->no_cdrom = 1; 1116 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1117 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1118 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1119 mc->numa_mem_supported = true; 1120 mc->auto_enable_numa_with_memhp = true; 1121 mc->auto_enable_numa_with_memdev = true; 1122 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1123 mc->default_nic = "virtio-net-pci"; 1124 hc->plug = loongarch_machine_device_plug_cb; 1125 hc->pre_plug = virt_machine_device_pre_plug; 1126 hc->unplug_request = virt_machine_device_unplug_request; 1127 hc->unplug = virt_machine_device_unplug; 1128 1129 object_class_property_add(oc, "acpi", "OnOffAuto", 1130 loongarch_get_acpi, loongarch_set_acpi, 1131 NULL, NULL); 1132 object_class_property_set_description(oc, "acpi", 1133 "Enable ACPI"); 1134 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1135 #ifdef CONFIG_TPM 1136 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1137 #endif 1138 } 1139 1140 static const TypeInfo loongarch_machine_types[] = { 1141 { 1142 .name = TYPE_LOONGARCH_MACHINE, 1143 .parent = TYPE_MACHINE, 1144 .instance_size = sizeof(LoongArchMachineState), 1145 .class_init = loongarch_class_init, 1146 .instance_init = loongarch_machine_initfn, 1147 .interfaces = (InterfaceInfo[]) { 1148 { TYPE_HOTPLUG_HANDLER }, 1149 { } 1150 }, 1151 } 1152 }; 1153 1154 DEFINE_TYPES(loongarch_machine_types) 1155