1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/sysemu.h" 14 #include "sysemu/qtest.h" 15 #include "sysemu/runstate.h" 16 #include "sysemu/reset.h" 17 #include "sysemu/rtc.h" 18 #include "hw/loongarch/virt.h" 19 #include "exec/address-spaces.h" 20 #include "hw/irq.h" 21 #include "net/net.h" 22 #include "hw/loader.h" 23 #include "elf.h" 24 #include "hw/intc/loongarch_ipi.h" 25 #include "hw/intc/loongarch_extioi.h" 26 #include "hw/intc/loongarch_pch_pic.h" 27 #include "hw/intc/loongarch_pch_msi.h" 28 #include "hw/pci-host/ls7a.h" 29 #include "hw/pci-host/gpex.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/loongarch/fw_cfg.h" 32 #include "target/loongarch/cpu.h" 33 #include "hw/firmware/smbios.h" 34 #include "hw/acpi/aml-build.h" 35 #include "qapi/qapi-visit-common.h" 36 #include "hw/acpi/generic_event_device.h" 37 #include "hw/mem/nvdimm.h" 38 #include "sysemu/device_tree.h" 39 #include <libfdt.h> 40 #include "hw/core/sysbus-fdt.h" 41 #include "hw/platform-bus.h" 42 #include "hw/display/ramfb.h" 43 #include "hw/mem/pc-dimm.h" 44 #include "sysemu/tpm.h" 45 #include "sysemu/block-backend.h" 46 #include "hw/block/flash.h" 47 #include "qemu/error-report.h" 48 49 static PFlashCFI01 *virt_flash_create1(LoongArchMachineState *lams, 50 const char *name, 51 const char *alias_prop_name) 52 { 53 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 54 55 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 56 qdev_prop_set_uint8(dev, "width", 4); 57 qdev_prop_set_uint8(dev, "device-width", 2); 58 qdev_prop_set_bit(dev, "big-endian", false); 59 qdev_prop_set_uint16(dev, "id0", 0x89); 60 qdev_prop_set_uint16(dev, "id1", 0x18); 61 qdev_prop_set_uint16(dev, "id2", 0x00); 62 qdev_prop_set_uint16(dev, "id3", 0x00); 63 qdev_prop_set_string(dev, "name", name); 64 object_property_add_child(OBJECT(lams), name, OBJECT(dev)); 65 object_property_add_alias(OBJECT(lams), alias_prop_name, 66 OBJECT(dev), "drive"); 67 return PFLASH_CFI01(dev); 68 } 69 70 static void virt_flash_create(LoongArchMachineState *lams) 71 { 72 lams->flash[0] = virt_flash_create1(lams, "virt.flash0", "pflash0"); 73 lams->flash[1] = virt_flash_create1(lams, "virt.flash1", "pflash1"); 74 } 75 76 static void virt_flash_map1(PFlashCFI01 *flash, 77 hwaddr base, hwaddr size, 78 MemoryRegion *sysmem) 79 { 80 DeviceState *dev = DEVICE(flash); 81 BlockBackend *blk; 82 hwaddr real_size = size; 83 84 blk = pflash_cfi01_get_blk(flash); 85 if (blk) { 86 real_size = blk_getlength(blk); 87 assert(real_size && real_size <= size); 88 } 89 90 assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE)); 91 assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 92 93 qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE); 94 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 95 memory_region_add_subregion(sysmem, base, 96 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 97 } 98 99 static void virt_flash_map(LoongArchMachineState *lams, 100 MemoryRegion *sysmem) 101 { 102 PFlashCFI01 *flash0 = lams->flash[0]; 103 PFlashCFI01 *flash1 = lams->flash[1]; 104 105 virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem); 106 virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem); 107 } 108 109 static void fdt_add_cpuic_node(LoongArchMachineState *lams, 110 uint32_t *cpuintc_phandle) 111 { 112 MachineState *ms = MACHINE(lams); 113 char *nodename; 114 115 *cpuintc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 116 nodename = g_strdup_printf("/cpuic"); 117 qemu_fdt_add_subnode(ms->fdt, nodename); 118 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *cpuintc_phandle); 119 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 120 "loongson,cpu-interrupt-controller"); 121 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 122 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 123 g_free(nodename); 124 } 125 126 static void fdt_add_eiointc_node(LoongArchMachineState *lams, 127 uint32_t *cpuintc_phandle, 128 uint32_t *eiointc_phandle) 129 { 130 MachineState *ms = MACHINE(lams); 131 char *nodename; 132 hwaddr extioi_base = APIC_BASE; 133 hwaddr extioi_size = EXTIOI_SIZE; 134 135 *eiointc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 136 nodename = g_strdup_printf("/eiointc@%" PRIx64, extioi_base); 137 qemu_fdt_add_subnode(ms->fdt, nodename); 138 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *eiointc_phandle); 139 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 140 "loongson,ls2k2000-eiointc"); 141 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 142 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 143 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 144 *cpuintc_phandle); 145 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", 3); 146 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, 147 extioi_base, 0x0, extioi_size); 148 g_free(nodename); 149 } 150 151 static void fdt_add_pch_pic_node(LoongArchMachineState *lams, 152 uint32_t *eiointc_phandle, 153 uint32_t *pch_pic_phandle) 154 { 155 MachineState *ms = MACHINE(lams); 156 char *nodename; 157 hwaddr pch_pic_base = VIRT_PCH_REG_BASE; 158 hwaddr pch_pic_size = VIRT_PCH_REG_SIZE; 159 160 *pch_pic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 161 nodename = g_strdup_printf("/platic@%" PRIx64, pch_pic_base); 162 qemu_fdt_add_subnode(ms->fdt, nodename); 163 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_pic_phandle); 164 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 165 "loongson,pch-pic-1.0"); 166 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, 167 pch_pic_base, 0, pch_pic_size); 168 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 169 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 2); 170 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 171 *eiointc_phandle); 172 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,pic-base-vec", 0); 173 g_free(nodename); 174 } 175 176 static void fdt_add_pch_msi_node(LoongArchMachineState *lams, 177 uint32_t *eiointc_phandle, 178 uint32_t *pch_msi_phandle) 179 { 180 MachineState *ms = MACHINE(lams); 181 char *nodename; 182 hwaddr pch_msi_base = VIRT_PCH_MSI_ADDR_LOW; 183 hwaddr pch_msi_size = VIRT_PCH_MSI_SIZE; 184 185 *pch_msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 186 nodename = g_strdup_printf("/msi@%" PRIx64, pch_msi_base); 187 qemu_fdt_add_subnode(ms->fdt, nodename); 188 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_msi_phandle); 189 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 190 "loongson,pch-msi-1.0"); 191 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 192 0, pch_msi_base, 193 0, pch_msi_size); 194 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 195 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 196 *eiointc_phandle); 197 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-base-vec", 198 VIRT_PCH_PIC_IRQ_NUM); 199 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-num-vecs", 200 EXTIOI_IRQS - VIRT_PCH_PIC_IRQ_NUM); 201 g_free(nodename); 202 } 203 204 static void fdt_add_flash_node(LoongArchMachineState *lams) 205 { 206 MachineState *ms = MACHINE(lams); 207 char *nodename; 208 MemoryRegion *flash_mem; 209 210 hwaddr flash0_base; 211 hwaddr flash0_size; 212 213 hwaddr flash1_base; 214 hwaddr flash1_size; 215 216 flash_mem = pflash_cfi01_get_memory(lams->flash[0]); 217 flash0_base = flash_mem->addr; 218 flash0_size = memory_region_size(flash_mem); 219 220 flash_mem = pflash_cfi01_get_memory(lams->flash[1]); 221 flash1_base = flash_mem->addr; 222 flash1_size = memory_region_size(flash_mem); 223 224 nodename = g_strdup_printf("/flash@%" PRIx64, flash0_base); 225 qemu_fdt_add_subnode(ms->fdt, nodename); 226 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 227 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 228 2, flash0_base, 2, flash0_size, 229 2, flash1_base, 2, flash1_size); 230 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 231 g_free(nodename); 232 } 233 234 static void fdt_add_rtc_node(LoongArchMachineState *lams) 235 { 236 char *nodename; 237 hwaddr base = VIRT_RTC_REG_BASE; 238 hwaddr size = VIRT_RTC_LEN; 239 MachineState *ms = MACHINE(lams); 240 241 nodename = g_strdup_printf("/rtc@%" PRIx64, base); 242 qemu_fdt_add_subnode(ms->fdt, nodename); 243 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc"); 244 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 245 g_free(nodename); 246 } 247 248 static void fdt_add_uart_node(LoongArchMachineState *lams) 249 { 250 char *nodename; 251 hwaddr base = VIRT_UART_BASE; 252 hwaddr size = VIRT_UART_SIZE; 253 MachineState *ms = MACHINE(lams); 254 255 nodename = g_strdup_printf("/serial@%" PRIx64, base); 256 qemu_fdt_add_subnode(ms->fdt, nodename); 257 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); 258 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); 259 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); 260 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 261 g_free(nodename); 262 } 263 264 static void create_fdt(LoongArchMachineState *lams) 265 { 266 MachineState *ms = MACHINE(lams); 267 268 ms->fdt = create_device_tree(&lams->fdt_size); 269 if (!ms->fdt) { 270 error_report("create_device_tree() failed"); 271 exit(1); 272 } 273 274 /* Header */ 275 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 276 "linux,dummy-loongson3"); 277 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 278 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 279 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 280 } 281 282 static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) 283 { 284 int num; 285 const MachineState *ms = MACHINE(lams); 286 int smp_cpus = ms->smp.cpus; 287 288 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 289 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 290 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 291 292 /* cpu nodes */ 293 for (num = smp_cpus - 1; num >= 0; num--) { 294 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 295 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 296 CPUState *cs = CPU(cpu); 297 298 qemu_fdt_add_subnode(ms->fdt, nodename); 299 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 300 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 301 cpu->dtb_compatible); 302 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 303 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 304 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 305 } 306 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 307 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 308 qemu_fdt_alloc_phandle(ms->fdt)); 309 g_free(nodename); 310 } 311 312 /*cpu map */ 313 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 314 315 for (num = smp_cpus - 1; num >= 0; num--) { 316 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 317 char *map_path; 318 319 if (ms->smp.threads > 1) { 320 map_path = g_strdup_printf( 321 "/cpus/cpu-map/socket%d/core%d/thread%d", 322 num / (ms->smp.cores * ms->smp.threads), 323 (num / ms->smp.threads) % ms->smp.cores, 324 num % ms->smp.threads); 325 } else { 326 map_path = g_strdup_printf( 327 "/cpus/cpu-map/socket%d/core%d", 328 num / ms->smp.cores, 329 num % ms->smp.cores); 330 } 331 qemu_fdt_add_path(ms->fdt, map_path); 332 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 333 334 g_free(map_path); 335 g_free(cpu_path); 336 } 337 } 338 339 static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) 340 { 341 char *nodename; 342 hwaddr base = VIRT_FWCFG_BASE; 343 const MachineState *ms = MACHINE(lams); 344 345 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 346 qemu_fdt_add_subnode(ms->fdt, nodename); 347 qemu_fdt_setprop_string(ms->fdt, nodename, 348 "compatible", "qemu,fw-cfg-mmio"); 349 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 350 2, base, 2, 0x18); 351 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 352 g_free(nodename); 353 } 354 355 static void fdt_add_pcie_node(const LoongArchMachineState *lams) 356 { 357 char *nodename; 358 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 359 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 360 hwaddr base_pio = VIRT_PCI_IO_BASE; 361 hwaddr size_pio = VIRT_PCI_IO_SIZE; 362 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 363 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 364 hwaddr base = base_pcie; 365 366 const MachineState *ms = MACHINE(lams); 367 368 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 369 qemu_fdt_add_subnode(ms->fdt, nodename); 370 qemu_fdt_setprop_string(ms->fdt, nodename, 371 "compatible", "pci-host-ecam-generic"); 372 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 373 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 374 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 375 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 376 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 377 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 378 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 379 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 380 2, base_pcie, 2, size_pcie); 381 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 382 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 383 2, base_pio, 2, size_pio, 384 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 385 2, base_mmio, 2, size_mmio); 386 g_free(nodename); 387 } 388 389 static void fdt_add_irqchip_node(LoongArchMachineState *lams) 390 { 391 MachineState *ms = MACHINE(lams); 392 char *nodename; 393 uint32_t irqchip_phandle; 394 395 irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt); 396 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle); 397 398 nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE); 399 qemu_fdt_add_subnode(ms->fdt, nodename); 400 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 401 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 402 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 403 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 404 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 405 406 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 407 "loongarch,ls7a"); 408 409 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 410 2, VIRT_IOAPIC_REG_BASE, 411 2, PCH_PIC_ROUTE_ENTRY_OFFSET); 412 413 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle); 414 g_free(nodename); 415 } 416 417 static void fdt_add_memory_node(MachineState *ms, 418 uint64_t base, uint64_t size, int node_id) 419 { 420 char *nodename = g_strdup_printf("/memory@%" PRIx64, base); 421 422 qemu_fdt_add_subnode(ms->fdt, nodename); 423 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, 0, size); 424 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 425 426 if (ms->numa_state && ms->numa_state->num_nodes) { 427 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); 428 } 429 430 g_free(nodename); 431 } 432 433 static void virt_build_smbios(LoongArchMachineState *lams) 434 { 435 MachineState *ms = MACHINE(lams); 436 MachineClass *mc = MACHINE_GET_CLASS(lams); 437 uint8_t *smbios_tables, *smbios_anchor; 438 size_t smbios_tables_len, smbios_anchor_len; 439 const char *product = "QEMU Virtual Machine"; 440 441 if (!lams->fw_cfg) { 442 return; 443 } 444 445 smbios_set_defaults("QEMU", product, mc->name, true); 446 447 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 448 NULL, 0, 449 &smbios_tables, &smbios_tables_len, 450 &smbios_anchor, &smbios_anchor_len, &error_fatal); 451 452 if (smbios_anchor) { 453 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", 454 smbios_tables, smbios_tables_len); 455 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", 456 smbios_anchor, smbios_anchor_len); 457 } 458 } 459 460 static void virt_machine_done(Notifier *notifier, void *data) 461 { 462 LoongArchMachineState *lams = container_of(notifier, 463 LoongArchMachineState, machine_done); 464 virt_build_smbios(lams); 465 loongarch_acpi_setup(lams); 466 } 467 468 static void virt_powerdown_req(Notifier *notifier, void *opaque) 469 { 470 LoongArchMachineState *s = container_of(notifier, 471 LoongArchMachineState, powerdown_notifier); 472 473 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 474 } 475 476 struct memmap_entry *memmap_table; 477 unsigned memmap_entries; 478 479 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 480 { 481 /* Ensure there are no duplicate entries. */ 482 for (unsigned i = 0; i < memmap_entries; i++) { 483 assert(memmap_table[i].address != address); 484 } 485 486 memmap_table = g_renew(struct memmap_entry, memmap_table, 487 memmap_entries + 1); 488 memmap_table[memmap_entries].address = cpu_to_le64(address); 489 memmap_table[memmap_entries].length = cpu_to_le64(length); 490 memmap_table[memmap_entries].type = cpu_to_le32(type); 491 memmap_table[memmap_entries].reserved = 0; 492 memmap_entries++; 493 } 494 495 static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams) 496 { 497 DeviceState *dev; 498 MachineState *ms = MACHINE(lams); 499 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 500 501 if (ms->ram_slots) { 502 event |= ACPI_GED_MEM_HOTPLUG_EVT; 503 } 504 dev = qdev_new(TYPE_ACPI_GED); 505 qdev_prop_set_uint32(dev, "ged-event", event); 506 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 507 508 /* ged event */ 509 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 510 /* memory hotplug */ 511 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 512 /* ged regs used for reset and power down */ 513 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 514 515 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 516 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 517 return dev; 518 } 519 520 static DeviceState *create_platform_bus(DeviceState *pch_pic) 521 { 522 DeviceState *dev; 523 SysBusDevice *sysbus; 524 int i, irq; 525 MemoryRegion *sysmem = get_system_memory(); 526 527 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 528 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 529 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 530 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 531 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 532 533 sysbus = SYS_BUS_DEVICE(dev); 534 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 535 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 536 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 537 } 538 539 memory_region_add_subregion(sysmem, 540 VIRT_PLATFORM_BUS_BASEADDRESS, 541 sysbus_mmio_get_region(sysbus, 0)); 542 return dev; 543 } 544 545 static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams) 546 { 547 MachineClass *mc = MACHINE_GET_CLASS(lams); 548 DeviceState *gpex_dev; 549 SysBusDevice *d; 550 PCIBus *pci_bus; 551 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 552 MemoryRegion *mmio_alias, *mmio_reg; 553 int i; 554 555 gpex_dev = qdev_new(TYPE_GPEX_HOST); 556 d = SYS_BUS_DEVICE(gpex_dev); 557 sysbus_realize_and_unref(d, &error_fatal); 558 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 559 lams->pci_bus = pci_bus; 560 561 /* Map only part size_ecam bytes of ECAM space */ 562 ecam_alias = g_new0(MemoryRegion, 1); 563 ecam_reg = sysbus_mmio_get_region(d, 0); 564 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 565 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 566 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 567 ecam_alias); 568 569 /* Map PCI mem space */ 570 mmio_alias = g_new0(MemoryRegion, 1); 571 mmio_reg = sysbus_mmio_get_region(d, 1); 572 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 573 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 574 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 575 mmio_alias); 576 577 /* Map PCI IO port space. */ 578 pio_alias = g_new0(MemoryRegion, 1); 579 pio_reg = sysbus_mmio_get_region(d, 2); 580 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 581 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 582 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 583 pio_alias); 584 585 for (i = 0; i < GPEX_NUM_IRQS; i++) { 586 sysbus_connect_irq(d, i, 587 qdev_get_gpio_in(pch_pic, 16 + i)); 588 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 589 } 590 591 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 592 qdev_get_gpio_in(pch_pic, 593 VIRT_UART_IRQ - VIRT_GSI_BASE), 594 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 595 fdt_add_uart_node(lams); 596 597 /* Network init */ 598 pci_init_nic_devices(pci_bus, mc->default_nic); 599 600 /* 601 * There are some invalid guest memory access. 602 * Create some unimplemented devices to emulate this. 603 */ 604 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 605 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 606 qdev_get_gpio_in(pch_pic, 607 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 608 fdt_add_rtc_node(lams); 609 610 /* acpi ged */ 611 lams->acpi_ged = create_acpi_ged(pch_pic, lams); 612 /* platform bus */ 613 lams->platform_bus_dev = create_platform_bus(pch_pic); 614 } 615 616 static void loongarch_irq_init(LoongArchMachineState *lams) 617 { 618 MachineState *ms = MACHINE(lams); 619 DeviceState *pch_pic, *pch_msi, *cpudev; 620 DeviceState *ipi, *extioi; 621 SysBusDevice *d; 622 LoongArchCPU *lacpu; 623 CPULoongArchState *env; 624 CPUState *cpu_state; 625 int cpu, pin, i, start, num; 626 uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle; 627 628 /* 629 * The connection of interrupts: 630 * +-----+ +---------+ +-------+ 631 * | IPI |--> | CPUINTC | <-- | Timer | 632 * +-----+ +---------+ +-------+ 633 * ^ 634 * | 635 * +---------+ 636 * | EIOINTC | 637 * +---------+ 638 * ^ ^ 639 * | | 640 * +---------+ +---------+ 641 * | PCH-PIC | | PCH-MSI | 642 * +---------+ +---------+ 643 * ^ ^ ^ 644 * | | | 645 * +--------+ +---------+ +---------+ 646 * | UARTs | | Devices | | Devices | 647 * +--------+ +---------+ +---------+ 648 */ 649 650 /* Create IPI device */ 651 ipi = qdev_new(TYPE_LOONGARCH_IPI); 652 qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); 653 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 654 655 /* IPI iocsr memory region */ 656 memory_region_add_subregion(&lams->system_iocsr, SMP_IPI_MAILBOX, 657 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); 658 memory_region_add_subregion(&lams->system_iocsr, MAIL_SEND_ADDR, 659 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); 660 661 /* Add cpu interrupt-controller */ 662 fdt_add_cpuic_node(lams, &cpuintc_phandle); 663 664 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 665 cpu_state = qemu_get_cpu(cpu); 666 cpudev = DEVICE(cpu_state); 667 lacpu = LOONGARCH_CPU(cpu_state); 668 env = &(lacpu->env); 669 env->address_space_iocsr = &lams->as_iocsr; 670 671 /* connect ipi irq to cpu irq */ 672 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); 673 env->ipistate = ipi; 674 } 675 676 /* Create EXTIOI device */ 677 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 678 qdev_prop_set_uint32(extioi, "num-cpu", ms->smp.cpus); 679 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 680 memory_region_add_subregion(&lams->system_iocsr, APIC_BASE, 681 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); 682 683 /* 684 * connect ext irq to the cpu irq 685 * cpu_pin[9:2] <= intc_pin[7:0] 686 */ 687 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 688 cpudev = DEVICE(qemu_get_cpu(cpu)); 689 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 690 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 691 qdev_get_gpio_in(cpudev, pin + 2)); 692 } 693 } 694 695 /* Add Extend I/O Interrupt Controller node */ 696 fdt_add_eiointc_node(lams, &cpuintc_phandle, &eiointc_phandle); 697 698 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 699 num = VIRT_PCH_PIC_IRQ_NUM; 700 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 701 d = SYS_BUS_DEVICE(pch_pic); 702 sysbus_realize_and_unref(d, &error_fatal); 703 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 704 sysbus_mmio_get_region(d, 0)); 705 memory_region_add_subregion(get_system_memory(), 706 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 707 sysbus_mmio_get_region(d, 1)); 708 memory_region_add_subregion(get_system_memory(), 709 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 710 sysbus_mmio_get_region(d, 2)); 711 712 /* Connect pch_pic irqs to extioi */ 713 for (i = 0; i < num; i++) { 714 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 715 } 716 717 /* Add PCH PIC node */ 718 fdt_add_pch_pic_node(lams, &eiointc_phandle, &pch_pic_phandle); 719 720 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 721 start = num; 722 num = EXTIOI_IRQS - start; 723 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 724 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 725 d = SYS_BUS_DEVICE(pch_msi); 726 sysbus_realize_and_unref(d, &error_fatal); 727 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 728 for (i = 0; i < num; i++) { 729 /* Connect pch_msi irqs to extioi */ 730 qdev_connect_gpio_out(DEVICE(d), i, 731 qdev_get_gpio_in(extioi, i + start)); 732 } 733 734 /* Add PCH MSI node */ 735 fdt_add_pch_msi_node(lams, &eiointc_phandle, &pch_msi_phandle); 736 737 loongarch_devices_init(pch_pic, lams); 738 } 739 740 static void loongarch_firmware_init(LoongArchMachineState *lams) 741 { 742 char *filename = MACHINE(lams)->firmware; 743 char *bios_name = NULL; 744 int bios_size, i; 745 BlockBackend *pflash_blk0; 746 MemoryRegion *mr; 747 748 lams->bios_loaded = false; 749 750 /* Map legacy -drive if=pflash to machine properties */ 751 for (i = 0; i < ARRAY_SIZE(lams->flash); i++) { 752 pflash_cfi01_legacy_drive(lams->flash[i], 753 drive_get(IF_PFLASH, 0, i)); 754 } 755 756 virt_flash_map(lams, get_system_memory()); 757 758 pflash_blk0 = pflash_cfi01_get_blk(lams->flash[0]); 759 760 if (pflash_blk0) { 761 if (filename) { 762 error_report("cannot use both '-bios' and '-drive if=pflash'" 763 "options at once"); 764 exit(1); 765 } 766 lams->bios_loaded = true; 767 return; 768 } 769 770 if (filename) { 771 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 772 if (!bios_name) { 773 error_report("Could not find ROM image '%s'", filename); 774 exit(1); 775 } 776 777 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lams->flash[0]), 0); 778 bios_size = load_image_mr(bios_name, mr); 779 if (bios_size < 0) { 780 error_report("Could not load ROM image '%s'", bios_name); 781 exit(1); 782 } 783 g_free(bios_name); 784 lams->bios_loaded = true; 785 } 786 } 787 788 789 static void loongarch_qemu_write(void *opaque, hwaddr addr, 790 uint64_t val, unsigned size) 791 { 792 } 793 794 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) 795 { 796 switch (addr) { 797 case VERSION_REG: 798 return 0x11ULL; 799 case FEATURE_REG: 800 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 801 1ULL << IOCSRF_CSRIPI; 802 case VENDOR_REG: 803 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 804 case CPUNAME_REG: 805 return 0x303030354133ULL; /* "3A5000" */ 806 case MISC_FUNC_REG: 807 return 1ULL << IOCSRM_EXTIOI_EN; 808 } 809 return 0ULL; 810 } 811 812 static const MemoryRegionOps loongarch_qemu_ops = { 813 .read = loongarch_qemu_read, 814 .write = loongarch_qemu_write, 815 .endianness = DEVICE_LITTLE_ENDIAN, 816 .valid = { 817 .min_access_size = 4, 818 .max_access_size = 8, 819 }, 820 .impl = { 821 .min_access_size = 8, 822 .max_access_size = 8, 823 }, 824 }; 825 826 static void loongarch_init(MachineState *machine) 827 { 828 LoongArchCPU *lacpu; 829 const char *cpu_model = machine->cpu_type; 830 ram_addr_t offset = 0; 831 ram_addr_t ram_size = machine->ram_size; 832 uint64_t highram_size = 0, phyAddr = 0; 833 MemoryRegion *address_space_mem = get_system_memory(); 834 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 835 int nb_numa_nodes = machine->numa_state->num_nodes; 836 NodeInfo *numa_info = machine->numa_state->nodes; 837 int i; 838 const CPUArchIdList *possible_cpus; 839 MachineClass *mc = MACHINE_GET_CLASS(machine); 840 CPUState *cpu; 841 char *ramName = NULL; 842 843 if (!cpu_model) { 844 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 845 } 846 847 if (ram_size < 1 * GiB) { 848 error_report("ram_size must be greater than 1G."); 849 exit(1); 850 } 851 create_fdt(lams); 852 853 /* Create IOCSR space */ 854 memory_region_init_io(&lams->system_iocsr, OBJECT(machine), NULL, 855 machine, "iocsr", UINT64_MAX); 856 address_space_init(&lams->as_iocsr, &lams->system_iocsr, "IOCSR"); 857 memory_region_init_io(&lams->iocsr_mem, OBJECT(machine), 858 &loongarch_qemu_ops, 859 machine, "iocsr_misc", 0x428); 860 memory_region_add_subregion(&lams->system_iocsr, 0, &lams->iocsr_mem); 861 862 /* Init CPUs */ 863 possible_cpus = mc->possible_cpu_arch_ids(machine); 864 for (i = 0; i < possible_cpus->len; i++) { 865 cpu = cpu_create(machine->cpu_type); 866 cpu->cpu_index = i; 867 machine->possible_cpus->cpus[i].cpu = cpu; 868 lacpu = LOONGARCH_CPU(cpu); 869 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; 870 } 871 fdt_add_cpu_nodes(lams); 872 873 /* Node0 memory */ 874 memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1); 875 fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0); 876 memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram", 877 machine->ram, offset, VIRT_LOWMEM_SIZE); 878 memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem); 879 880 offset += VIRT_LOWMEM_SIZE; 881 if (nb_numa_nodes > 0) { 882 assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE); 883 highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE; 884 } else { 885 highram_size = ram_size - VIRT_LOWMEM_SIZE; 886 } 887 phyAddr = VIRT_HIGHMEM_BASE; 888 memmap_add_entry(phyAddr, highram_size, 1); 889 fdt_add_memory_node(machine, phyAddr, highram_size, 0); 890 memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram", 891 machine->ram, offset, highram_size); 892 memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem); 893 894 /* Node1 - Nodemax memory */ 895 offset += highram_size; 896 phyAddr += highram_size; 897 898 for (i = 1; i < nb_numa_nodes; i++) { 899 MemoryRegion *nodemem = g_new(MemoryRegion, 1); 900 ramName = g_strdup_printf("loongarch.node%d.ram", i); 901 memory_region_init_alias(nodemem, NULL, ramName, machine->ram, 902 offset, numa_info[i].node_mem); 903 memory_region_add_subregion(address_space_mem, phyAddr, nodemem); 904 memmap_add_entry(phyAddr, numa_info[i].node_mem, 1); 905 fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i); 906 offset += numa_info[i].node_mem; 907 phyAddr += numa_info[i].node_mem; 908 } 909 910 /* initialize device memory address space */ 911 if (machine->ram_size < machine->maxram_size) { 912 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 913 hwaddr device_mem_base; 914 915 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 916 error_report("unsupported amount of memory slots: %"PRIu64, 917 machine->ram_slots); 918 exit(EXIT_FAILURE); 919 } 920 921 if (QEMU_ALIGN_UP(machine->maxram_size, 922 TARGET_PAGE_SIZE) != machine->maxram_size) { 923 error_report("maximum memory size must by aligned to multiple of " 924 "%d bytes", TARGET_PAGE_SIZE); 925 exit(EXIT_FAILURE); 926 } 927 /* device memory base is the top of high memory address. */ 928 device_mem_base = ROUND_UP(VIRT_HIGHMEM_BASE + highram_size, 1 * GiB); 929 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 930 } 931 932 /* load the BIOS image. */ 933 loongarch_firmware_init(lams); 934 935 /* fw_cfg init */ 936 lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine); 937 rom_set_fw(lams->fw_cfg); 938 if (lams->fw_cfg != NULL) { 939 fw_cfg_add_file(lams->fw_cfg, "etc/memmap", 940 memmap_table, 941 sizeof(struct memmap_entry) * (memmap_entries)); 942 } 943 fdt_add_fw_cfg_node(lams); 944 fdt_add_flash_node(lams); 945 946 /* Initialize the IO interrupt subsystem */ 947 loongarch_irq_init(lams); 948 fdt_add_irqchip_node(lams); 949 platform_bus_add_all_fdt_nodes(machine->fdt, "/intc", 950 VIRT_PLATFORM_BUS_BASEADDRESS, 951 VIRT_PLATFORM_BUS_SIZE, 952 VIRT_PLATFORM_BUS_IRQ); 953 lams->machine_done.notify = virt_machine_done; 954 qemu_add_machine_init_done_notifier(&lams->machine_done); 955 /* connect powerdown request */ 956 lams->powerdown_notifier.notify = virt_powerdown_req; 957 qemu_register_powerdown_notifier(&lams->powerdown_notifier); 958 959 fdt_add_pcie_node(lams); 960 /* 961 * Since lowmem region starts from 0 and Linux kernel legacy start address 962 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer 963 * access. FDT size limit with 1 MiB. 964 * Put the FDT into the memory map as a ROM image: this will ensure 965 * the FDT is copied again upon reset, even if addr points into RAM. 966 */ 967 qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size); 968 rom_add_blob_fixed_as("fdt", machine->fdt, lams->fdt_size, FDT_BASE, 969 &address_space_memory); 970 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 971 rom_ptr_for_as(&address_space_memory, FDT_BASE, lams->fdt_size)); 972 973 lams->bootinfo.ram_size = ram_size; 974 loongarch_load_kernel(machine, &lams->bootinfo); 975 } 976 977 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) 978 { 979 if (lams->acpi == ON_OFF_AUTO_OFF) { 980 return false; 981 } 982 return true; 983 } 984 985 static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, 986 void *opaque, Error **errp) 987 { 988 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 989 OnOffAuto acpi = lams->acpi; 990 991 visit_type_OnOffAuto(v, name, &acpi, errp); 992 } 993 994 static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, 995 void *opaque, Error **errp) 996 { 997 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 998 999 visit_type_OnOffAuto(v, name, &lams->acpi, errp); 1000 } 1001 1002 static void loongarch_machine_initfn(Object *obj) 1003 { 1004 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 1005 1006 lams->acpi = ON_OFF_AUTO_AUTO; 1007 lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1008 lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1009 virt_flash_create(lams); 1010 } 1011 1012 static bool memhp_type_supported(DeviceState *dev) 1013 { 1014 /* we only support pc dimm now */ 1015 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 1016 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1017 } 1018 1019 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1020 Error **errp) 1021 { 1022 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 1023 } 1024 1025 static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev, 1026 DeviceState *dev, Error **errp) 1027 { 1028 if (memhp_type_supported(dev)) { 1029 virt_mem_pre_plug(hotplug_dev, dev, errp); 1030 } 1031 } 1032 1033 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 1034 DeviceState *dev, Error **errp) 1035 { 1036 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1037 1038 /* the acpi ged is always exist */ 1039 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lams->acpi_ged), dev, 1040 errp); 1041 } 1042 1043 static void virt_machine_device_unplug_request(HotplugHandler *hotplug_dev, 1044 DeviceState *dev, Error **errp) 1045 { 1046 if (memhp_type_supported(dev)) { 1047 virt_mem_unplug_request(hotplug_dev, dev, errp); 1048 } 1049 } 1050 1051 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 1052 DeviceState *dev, Error **errp) 1053 { 1054 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1055 1056 hotplug_handler_unplug(HOTPLUG_HANDLER(lams->acpi_ged), dev, errp); 1057 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lams)); 1058 qdev_unrealize(dev); 1059 } 1060 1061 static void virt_machine_device_unplug(HotplugHandler *hotplug_dev, 1062 DeviceState *dev, Error **errp) 1063 { 1064 if (memhp_type_supported(dev)) { 1065 virt_mem_unplug(hotplug_dev, dev, errp); 1066 } 1067 } 1068 1069 static void virt_mem_plug(HotplugHandler *hotplug_dev, 1070 DeviceState *dev, Error **errp) 1071 { 1072 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1073 1074 pc_dimm_plug(PC_DIMM(dev), MACHINE(lams)); 1075 hotplug_handler_plug(HOTPLUG_HANDLER(lams->acpi_ged), 1076 dev, &error_abort); 1077 } 1078 1079 static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1080 DeviceState *dev, Error **errp) 1081 { 1082 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1083 MachineClass *mc = MACHINE_GET_CLASS(lams); 1084 1085 if (device_is_dynamic_sysbus(mc, dev)) { 1086 if (lams->platform_bus_dev) { 1087 platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev), 1088 SYS_BUS_DEVICE(dev)); 1089 } 1090 } else if (memhp_type_supported(dev)) { 1091 virt_mem_plug(hotplug_dev, dev, errp); 1092 } 1093 } 1094 1095 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1096 DeviceState *dev) 1097 { 1098 MachineClass *mc = MACHINE_GET_CLASS(machine); 1099 1100 if (device_is_dynamic_sysbus(mc, dev) || 1101 memhp_type_supported(dev)) { 1102 return HOTPLUG_HANDLER(machine); 1103 } 1104 return NULL; 1105 } 1106 1107 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1108 { 1109 int n; 1110 unsigned int max_cpus = ms->smp.max_cpus; 1111 1112 if (ms->possible_cpus) { 1113 assert(ms->possible_cpus->len == max_cpus); 1114 return ms->possible_cpus; 1115 } 1116 1117 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1118 sizeof(CPUArchId) * max_cpus); 1119 ms->possible_cpus->len = max_cpus; 1120 for (n = 0; n < ms->possible_cpus->len; n++) { 1121 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1122 ms->possible_cpus->cpus[n].arch_id = n; 1123 1124 ms->possible_cpus->cpus[n].props.has_socket_id = true; 1125 ms->possible_cpus->cpus[n].props.socket_id = 1126 n / (ms->smp.cores * ms->smp.threads); 1127 ms->possible_cpus->cpus[n].props.has_core_id = true; 1128 ms->possible_cpus->cpus[n].props.core_id = 1129 n / ms->smp.threads % ms->smp.cores; 1130 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1131 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 1132 } 1133 return ms->possible_cpus; 1134 } 1135 1136 static CpuInstanceProperties 1137 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1138 { 1139 MachineClass *mc = MACHINE_GET_CLASS(ms); 1140 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1141 1142 assert(cpu_index < possible_cpus->len); 1143 return possible_cpus->cpus[cpu_index].props; 1144 } 1145 1146 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1147 { 1148 int64_t nidx = 0; 1149 1150 if (ms->numa_state->num_nodes) { 1151 nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes); 1152 if (ms->numa_state->num_nodes <= nidx) { 1153 nidx = ms->numa_state->num_nodes - 1; 1154 } 1155 } 1156 return nidx; 1157 } 1158 1159 static void loongarch_class_init(ObjectClass *oc, void *data) 1160 { 1161 MachineClass *mc = MACHINE_CLASS(oc); 1162 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1163 1164 mc->desc = "Loongson-3A5000 LS7A1000 machine"; 1165 mc->init = loongarch_init; 1166 mc->default_ram_size = 1 * GiB; 1167 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 1168 mc->default_ram_id = "loongarch.ram"; 1169 mc->max_cpus = LOONGARCH_MAX_CPUS; 1170 mc->is_default = 1; 1171 mc->default_kernel_irqchip_split = false; 1172 mc->block_default_type = IF_VIRTIO; 1173 mc->default_boot_order = "c"; 1174 mc->no_cdrom = 1; 1175 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1176 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1177 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1178 mc->numa_mem_supported = true; 1179 mc->auto_enable_numa_with_memhp = true; 1180 mc->auto_enable_numa_with_memdev = true; 1181 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1182 mc->default_nic = "virtio-net-pci"; 1183 hc->plug = loongarch_machine_device_plug_cb; 1184 hc->pre_plug = virt_machine_device_pre_plug; 1185 hc->unplug_request = virt_machine_device_unplug_request; 1186 hc->unplug = virt_machine_device_unplug; 1187 1188 object_class_property_add(oc, "acpi", "OnOffAuto", 1189 loongarch_get_acpi, loongarch_set_acpi, 1190 NULL, NULL); 1191 object_class_property_set_description(oc, "acpi", 1192 "Enable ACPI"); 1193 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1194 #ifdef CONFIG_TPM 1195 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1196 #endif 1197 } 1198 1199 static const TypeInfo loongarch_machine_types[] = { 1200 { 1201 .name = TYPE_LOONGARCH_MACHINE, 1202 .parent = TYPE_MACHINE, 1203 .instance_size = sizeof(LoongArchMachineState), 1204 .class_init = loongarch_class_init, 1205 .instance_init = loongarch_machine_initfn, 1206 .interfaces = (InterfaceInfo[]) { 1207 { TYPE_HOTPLUG_HANDLER }, 1208 { } 1209 }, 1210 } 1211 }; 1212 1213 DEFINE_TYPES(loongarch_machine_types) 1214