1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial-mm.h" 13 #include "system/kvm.h" 14 #include "system/tcg.h" 15 #include "system/system.h" 16 #include "system/qtest.h" 17 #include "system/runstate.h" 18 #include "system/reset.h" 19 #include "system/rtc.h" 20 #include "hw/loongarch/virt.h" 21 #include "exec/address-spaces.h" 22 #include "hw/irq.h" 23 #include "net/net.h" 24 #include "hw/loader.h" 25 #include "elf.h" 26 #include "hw/intc/loongarch_ipi.h" 27 #include "hw/intc/loongarch_extioi.h" 28 #include "hw/intc/loongarch_pch_pic.h" 29 #include "hw/intc/loongarch_pch_msi.h" 30 #include "hw/pci-host/ls7a.h" 31 #include "hw/pci-host/gpex.h" 32 #include "hw/misc/unimp.h" 33 #include "hw/loongarch/fw_cfg.h" 34 #include "target/loongarch/cpu.h" 35 #include "hw/firmware/smbios.h" 36 #include "qapi/qapi-visit-common.h" 37 #include "hw/acpi/generic_event_device.h" 38 #include "hw/mem/nvdimm.h" 39 #include "hw/platform-bus.h" 40 #include "hw/display/ramfb.h" 41 #include "hw/mem/pc-dimm.h" 42 #include "system/tpm.h" 43 #include "system/block-backend.h" 44 #include "hw/block/flash.h" 45 #include "hw/virtio/virtio-iommu.h" 46 #include "qemu/error-report.h" 47 48 static bool virt_is_veiointc_enabled(LoongArchVirtMachineState *lvms) 49 { 50 if (lvms->veiointc == ON_OFF_AUTO_OFF) { 51 return false; 52 } 53 return true; 54 } 55 56 static void virt_get_veiointc(Object *obj, Visitor *v, const char *name, 57 void *opaque, Error **errp) 58 { 59 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 60 OnOffAuto veiointc = lvms->veiointc; 61 62 visit_type_OnOffAuto(v, name, &veiointc, errp); 63 } 64 65 static void virt_set_veiointc(Object *obj, Visitor *v, const char *name, 66 void *opaque, Error **errp) 67 { 68 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 69 70 visit_type_OnOffAuto(v, name, &lvms->veiointc, errp); 71 } 72 73 static PFlashCFI01 *virt_flash_create1(LoongArchVirtMachineState *lvms, 74 const char *name, 75 const char *alias_prop_name) 76 { 77 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 78 79 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 80 qdev_prop_set_uint8(dev, "width", 4); 81 qdev_prop_set_uint8(dev, "device-width", 2); 82 qdev_prop_set_bit(dev, "big-endian", false); 83 qdev_prop_set_uint16(dev, "id0", 0x89); 84 qdev_prop_set_uint16(dev, "id1", 0x18); 85 qdev_prop_set_uint16(dev, "id2", 0x00); 86 qdev_prop_set_uint16(dev, "id3", 0x00); 87 qdev_prop_set_string(dev, "name", name); 88 object_property_add_child(OBJECT(lvms), name, OBJECT(dev)); 89 object_property_add_alias(OBJECT(lvms), alias_prop_name, 90 OBJECT(dev), "drive"); 91 return PFLASH_CFI01(dev); 92 } 93 94 static void virt_flash_create(LoongArchVirtMachineState *lvms) 95 { 96 lvms->flash[0] = virt_flash_create1(lvms, "virt.flash0", "pflash0"); 97 lvms->flash[1] = virt_flash_create1(lvms, "virt.flash1", "pflash1"); 98 } 99 100 static void virt_flash_map1(PFlashCFI01 *flash, 101 hwaddr base, hwaddr size, 102 MemoryRegion *sysmem) 103 { 104 DeviceState *dev = DEVICE(flash); 105 BlockBackend *blk; 106 hwaddr real_size = size; 107 108 blk = pflash_cfi01_get_blk(flash); 109 if (blk) { 110 real_size = blk_getlength(blk); 111 assert(real_size && real_size <= size); 112 } 113 114 assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE)); 115 assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 116 117 qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE); 118 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 119 memory_region_add_subregion(sysmem, base, 120 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 121 } 122 123 static void virt_flash_map(LoongArchVirtMachineState *lvms, 124 MemoryRegion *sysmem) 125 { 126 PFlashCFI01 *flash0 = lvms->flash[0]; 127 PFlashCFI01 *flash1 = lvms->flash[1]; 128 129 virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem); 130 virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem); 131 } 132 133 static void virt_build_smbios(LoongArchVirtMachineState *lvms) 134 { 135 MachineState *ms = MACHINE(lvms); 136 MachineClass *mc = MACHINE_GET_CLASS(lvms); 137 uint8_t *smbios_tables, *smbios_anchor; 138 size_t smbios_tables_len, smbios_anchor_len; 139 const char *product = "QEMU Virtual Machine"; 140 141 if (!lvms->fw_cfg) { 142 return; 143 } 144 145 smbios_set_defaults("QEMU", product, mc->name); 146 147 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 148 NULL, 0, 149 &smbios_tables, &smbios_tables_len, 150 &smbios_anchor, &smbios_anchor_len, &error_fatal); 151 152 if (smbios_anchor) { 153 fw_cfg_add_file(lvms->fw_cfg, "etc/smbios/smbios-tables", 154 smbios_tables, smbios_tables_len); 155 fw_cfg_add_file(lvms->fw_cfg, "etc/smbios/smbios-anchor", 156 smbios_anchor, smbios_anchor_len); 157 } 158 } 159 160 static void virt_done(Notifier *notifier, void *data) 161 { 162 LoongArchVirtMachineState *lvms = container_of(notifier, 163 LoongArchVirtMachineState, machine_done); 164 virt_build_smbios(lvms); 165 virt_acpi_setup(lvms); 166 virt_fdt_setup(lvms); 167 } 168 169 static void virt_powerdown_req(Notifier *notifier, void *opaque) 170 { 171 LoongArchVirtMachineState *s; 172 173 s = container_of(notifier, LoongArchVirtMachineState, powerdown_notifier); 174 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 175 } 176 177 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 178 { 179 /* Ensure there are no duplicate entries. */ 180 for (unsigned i = 0; i < memmap_entries; i++) { 181 assert(memmap_table[i].address != address); 182 } 183 184 memmap_table = g_renew(struct memmap_entry, memmap_table, 185 memmap_entries + 1); 186 memmap_table[memmap_entries].address = cpu_to_le64(address); 187 memmap_table[memmap_entries].length = cpu_to_le64(length); 188 memmap_table[memmap_entries].type = cpu_to_le32(type); 189 memmap_table[memmap_entries].reserved = 0; 190 memmap_entries++; 191 } 192 193 static DeviceState *create_acpi_ged(DeviceState *pch_pic, 194 LoongArchVirtMachineState *lvms) 195 { 196 DeviceState *dev; 197 MachineState *ms = MACHINE(lvms); 198 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 199 200 if (ms->ram_slots) { 201 event |= ACPI_GED_MEM_HOTPLUG_EVT; 202 } 203 dev = qdev_new(TYPE_ACPI_GED); 204 qdev_prop_set_uint32(dev, "ged-event", event); 205 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 206 207 /* ged event */ 208 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 209 /* memory hotplug */ 210 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 211 /* ged regs used for reset and power down */ 212 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 213 214 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 215 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 216 return dev; 217 } 218 219 static DeviceState *create_platform_bus(DeviceState *pch_pic) 220 { 221 DeviceState *dev; 222 SysBusDevice *sysbus; 223 int i, irq; 224 MemoryRegion *sysmem = get_system_memory(); 225 226 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 227 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 228 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 229 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 230 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 231 232 sysbus = SYS_BUS_DEVICE(dev); 233 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 234 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 235 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 236 } 237 238 memory_region_add_subregion(sysmem, 239 VIRT_PLATFORM_BUS_BASEADDRESS, 240 sysbus_mmio_get_region(sysbus, 0)); 241 return dev; 242 } 243 244 static void virt_devices_init(DeviceState *pch_pic, 245 LoongArchVirtMachineState *lvms) 246 { 247 MachineClass *mc = MACHINE_GET_CLASS(lvms); 248 DeviceState *gpex_dev; 249 SysBusDevice *d; 250 PCIBus *pci_bus; 251 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 252 MemoryRegion *mmio_alias, *mmio_reg; 253 int i; 254 255 gpex_dev = qdev_new(TYPE_GPEX_HOST); 256 d = SYS_BUS_DEVICE(gpex_dev); 257 sysbus_realize_and_unref(d, &error_fatal); 258 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 259 lvms->pci_bus = pci_bus; 260 261 /* Map only part size_ecam bytes of ECAM space */ 262 ecam_alias = g_new0(MemoryRegion, 1); 263 ecam_reg = sysbus_mmio_get_region(d, 0); 264 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 265 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 266 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 267 ecam_alias); 268 269 /* Map PCI mem space */ 270 mmio_alias = g_new0(MemoryRegion, 1); 271 mmio_reg = sysbus_mmio_get_region(d, 1); 272 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 273 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 274 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 275 mmio_alias); 276 277 /* Map PCI IO port space. */ 278 pio_alias = g_new0(MemoryRegion, 1); 279 pio_reg = sysbus_mmio_get_region(d, 2); 280 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 281 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 282 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 283 pio_alias); 284 285 for (i = 0; i < PCI_NUM_PINS; i++) { 286 sysbus_connect_irq(d, i, 287 qdev_get_gpio_in(pch_pic, 16 + i)); 288 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 289 } 290 291 /* 292 * Create uart fdt node in reverse order so that they appear 293 * in the finished device tree lowest address first 294 */ 295 for (i = VIRT_UART_COUNT; i-- > 0;) { 296 hwaddr base = VIRT_UART_BASE + i * VIRT_UART_SIZE; 297 int irq = VIRT_UART_IRQ + i - VIRT_GSI_BASE; 298 serial_mm_init(get_system_memory(), base, 0, 299 qdev_get_gpio_in(pch_pic, irq), 300 115200, serial_hd(i), DEVICE_LITTLE_ENDIAN); 301 } 302 303 /* Network init */ 304 pci_init_nic_devices(pci_bus, mc->default_nic); 305 306 /* 307 * There are some invalid guest memory access. 308 * Create some unimplemented devices to emulate this. 309 */ 310 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 311 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 312 qdev_get_gpio_in(pch_pic, 313 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 314 315 /* acpi ged */ 316 lvms->acpi_ged = create_acpi_ged(pch_pic, lvms); 317 /* platform bus */ 318 lvms->platform_bus_dev = create_platform_bus(pch_pic); 319 } 320 321 static void virt_cpu_irq_init(LoongArchVirtMachineState *lvms) 322 { 323 int num, pin; 324 MachineState *ms = MACHINE(lvms); 325 MachineClass *mc = MACHINE_GET_CLASS(ms); 326 const CPUArchIdList *possible_cpus; 327 CPUState *cs; 328 329 /* cpu nodes */ 330 possible_cpus = mc->possible_cpu_arch_ids(ms); 331 for (num = 0; num < possible_cpus->len; num++) { 332 cs = possible_cpus->cpus[num].cpu; 333 if (cs == NULL) { 334 continue; 335 } 336 337 /* connect ipi irq to cpu irq */ 338 qdev_connect_gpio_out(lvms->ipi, num, 339 qdev_get_gpio_in(DEVICE(cs), IRQ_IPI)); 340 341 /* 342 * connect ext irq to the cpu irq 343 * cpu_pin[9:2] <= intc_pin[7:0] 344 */ 345 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 346 qdev_connect_gpio_out(lvms->extioi, (num * LS3A_INTC_IP + pin), 347 qdev_get_gpio_in(DEVICE(cs), pin + 2)); 348 } 349 } 350 } 351 352 static void virt_irq_init(LoongArchVirtMachineState *lvms) 353 { 354 DeviceState *pch_pic, *pch_msi; 355 DeviceState *ipi, *extioi; 356 SysBusDevice *d; 357 int i, start, num; 358 359 /* 360 * Extended IRQ model. 361 * | 362 * +-----------+ +-------------|--------+ +-----------+ 363 * | IPI/Timer | --> | CPUINTC(0-3)|(4-255) | <-- | IPI/Timer | 364 * +-----------+ +-------------|--------+ +-----------+ 365 * ^ | 366 * | 367 * +---------+ 368 * | EIOINTC | 369 * +---------+ 370 * ^ ^ 371 * | | 372 * +---------+ +---------+ 373 * | PCH-PIC | | PCH-MSI | 374 * +---------+ +---------+ 375 * ^ ^ ^ 376 * | | | 377 * +--------+ +---------+ +---------+ 378 * | UARTs | | Devices | | Devices | 379 * +--------+ +---------+ +---------+ 380 * 381 * Virt extended IRQ model. 382 * 383 * +-----+ +---------------+ +-------+ 384 * | IPI |--> | CPUINTC(0-255)| <-- | Timer | 385 * +-----+ +---------------+ +-------+ 386 * ^ 387 * | 388 * +-----------+ 389 * | V-EIOINTC | 390 * +-----------+ 391 * ^ ^ 392 * | | 393 * +---------+ +---------+ 394 * | PCH-PIC | | PCH-MSI | 395 * +---------+ +---------+ 396 * ^ ^ ^ 397 * | | | 398 * +--------+ +---------+ +---------+ 399 * | UARTs | | Devices | | Devices | 400 * +--------+ +---------+ +---------+ 401 */ 402 403 /* Create IPI device */ 404 ipi = qdev_new(TYPE_LOONGARCH_IPI); 405 lvms->ipi = ipi; 406 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 407 408 /* IPI iocsr memory region */ 409 memory_region_add_subregion(&lvms->system_iocsr, SMP_IPI_MAILBOX, 410 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); 411 memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR, 412 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); 413 414 /* Create EXTIOI device */ 415 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 416 lvms->extioi = extioi; 417 if (virt_is_veiointc_enabled(lvms)) { 418 qdev_prop_set_bit(extioi, "has-virtualization-extension", true); 419 } 420 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 421 memory_region_add_subregion(&lvms->system_iocsr, APIC_BASE, 422 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); 423 if (virt_is_veiointc_enabled(lvms)) { 424 memory_region_add_subregion(&lvms->system_iocsr, EXTIOI_VIRT_BASE, 425 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 1)); 426 } 427 428 virt_cpu_irq_init(lvms); 429 pch_pic = qdev_new(TYPE_LOONGARCH_PIC); 430 num = VIRT_PCH_PIC_IRQ_NUM; 431 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 432 d = SYS_BUS_DEVICE(pch_pic); 433 sysbus_realize_and_unref(d, &error_fatal); 434 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 435 sysbus_mmio_get_region(d, 0)); 436 memory_region_add_subregion(get_system_memory(), 437 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 438 sysbus_mmio_get_region(d, 1)); 439 memory_region_add_subregion(get_system_memory(), 440 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 441 sysbus_mmio_get_region(d, 2)); 442 443 /* Connect pch_pic irqs to extioi */ 444 for (i = 0; i < num; i++) { 445 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 446 } 447 448 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 449 start = num; 450 num = EXTIOI_IRQS - start; 451 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 452 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 453 d = SYS_BUS_DEVICE(pch_msi); 454 sysbus_realize_and_unref(d, &error_fatal); 455 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 456 for (i = 0; i < num; i++) { 457 /* Connect pch_msi irqs to extioi */ 458 qdev_connect_gpio_out(DEVICE(d), i, 459 qdev_get_gpio_in(extioi, i + start)); 460 } 461 462 virt_devices_init(pch_pic, lvms); 463 } 464 465 static void virt_firmware_init(LoongArchVirtMachineState *lvms) 466 { 467 char *filename = MACHINE(lvms)->firmware; 468 char *bios_name = NULL; 469 int bios_size, i; 470 BlockBackend *pflash_blk0; 471 MemoryRegion *mr; 472 473 lvms->bios_loaded = false; 474 475 /* Map legacy -drive if=pflash to machine properties */ 476 for (i = 0; i < ARRAY_SIZE(lvms->flash); i++) { 477 pflash_cfi01_legacy_drive(lvms->flash[i], 478 drive_get(IF_PFLASH, 0, i)); 479 } 480 481 virt_flash_map(lvms, get_system_memory()); 482 483 pflash_blk0 = pflash_cfi01_get_blk(lvms->flash[0]); 484 485 if (pflash_blk0) { 486 if (filename) { 487 error_report("cannot use both '-bios' and '-drive if=pflash'" 488 "options at once"); 489 exit(1); 490 } 491 lvms->bios_loaded = true; 492 return; 493 } 494 495 if (filename) { 496 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 497 if (!bios_name) { 498 error_report("Could not find ROM image '%s'", filename); 499 exit(1); 500 } 501 502 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lvms->flash[0]), 0); 503 bios_size = load_image_mr(bios_name, mr); 504 if (bios_size < 0) { 505 error_report("Could not load ROM image '%s'", bios_name); 506 exit(1); 507 } 508 g_free(bios_name); 509 lvms->bios_loaded = true; 510 } 511 } 512 513 static MemTxResult virt_iocsr_misc_write(void *opaque, hwaddr addr, 514 uint64_t val, unsigned size, 515 MemTxAttrs attrs) 516 { 517 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(opaque); 518 uint64_t features; 519 520 switch (addr) { 521 case MISC_FUNC_REG: 522 if (!virt_is_veiointc_enabled(lvms)) { 523 return MEMTX_OK; 524 } 525 526 features = address_space_ldl(&lvms->as_iocsr, 527 EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, 528 attrs, NULL); 529 if (val & BIT_ULL(IOCSRM_EXTIOI_EN)) { 530 features |= BIT(EXTIOI_ENABLE); 531 } 532 if (val & BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE)) { 533 features |= BIT(EXTIOI_ENABLE_INT_ENCODE); 534 } 535 536 address_space_stl(&lvms->as_iocsr, 537 EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, 538 features, attrs, NULL); 539 break; 540 default: 541 g_assert_not_reached(); 542 } 543 544 return MEMTX_OK; 545 } 546 547 static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr, 548 uint64_t *data, 549 unsigned size, MemTxAttrs attrs) 550 { 551 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(opaque); 552 uint64_t ret = 0; 553 int features; 554 555 switch (addr) { 556 case VERSION_REG: 557 ret = 0x11ULL; 558 break; 559 case FEATURE_REG: 560 ret = BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); 561 if (kvm_enabled()) { 562 ret |= BIT(IOCSRF_VM); 563 } 564 break; 565 case VENDOR_REG: 566 ret = 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 567 break; 568 case CPUNAME_REG: 569 ret = 0x303030354133ULL; /* "3A5000" */ 570 break; 571 case MISC_FUNC_REG: 572 if (!virt_is_veiointc_enabled(lvms)) { 573 ret |= BIT_ULL(IOCSRM_EXTIOI_EN); 574 break; 575 } 576 577 features = address_space_ldl(&lvms->as_iocsr, 578 EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, 579 attrs, NULL); 580 if (features & BIT(EXTIOI_ENABLE)) { 581 ret |= BIT_ULL(IOCSRM_EXTIOI_EN); 582 } 583 if (features & BIT(EXTIOI_ENABLE_INT_ENCODE)) { 584 ret |= BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE); 585 } 586 break; 587 default: 588 g_assert_not_reached(); 589 } 590 591 *data = ret; 592 return MEMTX_OK; 593 } 594 595 static const MemoryRegionOps virt_iocsr_misc_ops = { 596 .read_with_attrs = virt_iocsr_misc_read, 597 .write_with_attrs = virt_iocsr_misc_write, 598 .endianness = DEVICE_LITTLE_ENDIAN, 599 .valid = { 600 .min_access_size = 4, 601 .max_access_size = 8, 602 }, 603 .impl = { 604 .min_access_size = 8, 605 .max_access_size = 8, 606 }, 607 }; 608 609 static void fw_cfg_add_memory(MachineState *ms) 610 { 611 hwaddr base, size, ram_size, gap; 612 int nb_numa_nodes, nodes; 613 NodeInfo *numa_info; 614 615 ram_size = ms->ram_size; 616 base = VIRT_LOWMEM_BASE; 617 gap = VIRT_LOWMEM_SIZE; 618 nodes = nb_numa_nodes = ms->numa_state->num_nodes; 619 numa_info = ms->numa_state->nodes; 620 if (!nodes) { 621 nodes = 1; 622 } 623 624 /* add fw_cfg memory map of node0 */ 625 if (nb_numa_nodes) { 626 size = numa_info[0].node_mem; 627 } else { 628 size = ram_size; 629 } 630 631 if (size >= gap) { 632 memmap_add_entry(base, gap, 1); 633 size -= gap; 634 base = VIRT_HIGHMEM_BASE; 635 } 636 637 if (size) { 638 memmap_add_entry(base, size, 1); 639 base += size; 640 } 641 642 if (nodes < 2) { 643 return; 644 } 645 646 /* add fw_cfg memory map of other nodes */ 647 if (numa_info[0].node_mem < gap && ram_size > gap) { 648 /* 649 * memory map for the maining nodes splited into two part 650 * lowram: [base, +(gap - numa_info[0].node_mem)) 651 * highram: [VIRT_HIGHMEM_BASE, +(ram_size - gap)) 652 */ 653 memmap_add_entry(base, gap - numa_info[0].node_mem, 1); 654 size = ram_size - gap; 655 base = VIRT_HIGHMEM_BASE; 656 } else { 657 size = ram_size - numa_info[0].node_mem; 658 } 659 660 if (size) { 661 memmap_add_entry(base, size, 1); 662 } 663 } 664 665 static void virt_init(MachineState *machine) 666 { 667 LoongArchCPU *lacpu; 668 const char *cpu_model = machine->cpu_type; 669 MemoryRegion *address_space_mem = get_system_memory(); 670 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine); 671 int i; 672 hwaddr base, size, ram_size = machine->ram_size; 673 const CPUArchIdList *possible_cpus; 674 MachineClass *mc = MACHINE_GET_CLASS(machine); 675 CPUState *cpu; 676 677 if (!cpu_model) { 678 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 679 } 680 681 /* Create IOCSR space */ 682 memory_region_init_io(&lvms->system_iocsr, OBJECT(machine), NULL, 683 machine, "iocsr", UINT64_MAX); 684 address_space_init(&lvms->as_iocsr, &lvms->system_iocsr, "IOCSR"); 685 memory_region_init_io(&lvms->iocsr_mem, OBJECT(machine), 686 &virt_iocsr_misc_ops, 687 machine, "iocsr_misc", 0x428); 688 memory_region_add_subregion(&lvms->system_iocsr, 0, &lvms->iocsr_mem); 689 690 /* Init CPUs */ 691 possible_cpus = mc->possible_cpu_arch_ids(machine); 692 for (i = 0; i < possible_cpus->len; i++) { 693 cpu = cpu_create(machine->cpu_type); 694 cpu->cpu_index = i; 695 machine->possible_cpus->cpus[i].cpu = cpu; 696 lacpu = LOONGARCH_CPU(cpu); 697 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; 698 lacpu->env.address_space_iocsr = &lvms->as_iocsr; 699 } 700 fw_cfg_add_memory(machine); 701 702 /* Node0 memory */ 703 size = ram_size; 704 base = VIRT_LOWMEM_BASE; 705 if (size > VIRT_LOWMEM_SIZE) { 706 size = VIRT_LOWMEM_SIZE; 707 } 708 709 memory_region_init_alias(&lvms->lowmem, NULL, "loongarch.lowram", 710 machine->ram, base, size); 711 memory_region_add_subregion(address_space_mem, base, &lvms->lowmem); 712 base += size; 713 if (ram_size - size) { 714 base = VIRT_HIGHMEM_BASE; 715 memory_region_init_alias(&lvms->highmem, NULL, "loongarch.highram", 716 machine->ram, VIRT_LOWMEM_BASE + size, ram_size - size); 717 memory_region_add_subregion(address_space_mem, base, &lvms->highmem); 718 base += ram_size - size; 719 } 720 721 /* initialize device memory address space */ 722 if (machine->ram_size < machine->maxram_size) { 723 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 724 725 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 726 error_report("unsupported amount of memory slots: %"PRIu64, 727 machine->ram_slots); 728 exit(EXIT_FAILURE); 729 } 730 731 if (QEMU_ALIGN_UP(machine->maxram_size, 732 TARGET_PAGE_SIZE) != machine->maxram_size) { 733 error_report("maximum memory size must by aligned to multiple of " 734 "%d bytes", TARGET_PAGE_SIZE); 735 exit(EXIT_FAILURE); 736 } 737 machine_memory_devices_init(machine, base, device_mem_size); 738 } 739 740 /* load the BIOS image. */ 741 virt_firmware_init(lvms); 742 743 /* fw_cfg init */ 744 lvms->fw_cfg = virt_fw_cfg_init(ram_size, machine); 745 rom_set_fw(lvms->fw_cfg); 746 if (lvms->fw_cfg != NULL) { 747 fw_cfg_add_file(lvms->fw_cfg, "etc/memmap", 748 memmap_table, 749 sizeof(struct memmap_entry) * (memmap_entries)); 750 } 751 752 /* Initialize the IO interrupt subsystem */ 753 virt_irq_init(lvms); 754 lvms->machine_done.notify = virt_done; 755 qemu_add_machine_init_done_notifier(&lvms->machine_done); 756 /* connect powerdown request */ 757 lvms->powerdown_notifier.notify = virt_powerdown_req; 758 qemu_register_powerdown_notifier(&lvms->powerdown_notifier); 759 760 lvms->bootinfo.ram_size = ram_size; 761 loongarch_load_kernel(machine, &lvms->bootinfo); 762 } 763 764 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 765 void *opaque, Error **errp) 766 { 767 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 768 OnOffAuto acpi = lvms->acpi; 769 770 visit_type_OnOffAuto(v, name, &acpi, errp); 771 } 772 773 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 774 void *opaque, Error **errp) 775 { 776 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 777 778 visit_type_OnOffAuto(v, name, &lvms->acpi, errp); 779 } 780 781 static void virt_initfn(Object *obj) 782 { 783 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 784 785 if (tcg_enabled()) { 786 lvms->veiointc = ON_OFF_AUTO_OFF; 787 } 788 lvms->acpi = ON_OFF_AUTO_AUTO; 789 lvms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 790 lvms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 791 virt_flash_create(lvms); 792 } 793 794 static bool memhp_type_supported(DeviceState *dev) 795 { 796 /* we only support pc dimm now */ 797 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 798 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 799 } 800 801 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 802 Error **errp) 803 { 804 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 805 } 806 807 static void virt_device_pre_plug(HotplugHandler *hotplug_dev, 808 DeviceState *dev, Error **errp) 809 { 810 if (memhp_type_supported(dev)) { 811 virt_mem_pre_plug(hotplug_dev, dev, errp); 812 } 813 } 814 815 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 816 DeviceState *dev, Error **errp) 817 { 818 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 819 820 /* the acpi ged is always exist */ 821 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lvms->acpi_ged), dev, 822 errp); 823 } 824 825 static void virt_device_unplug_request(HotplugHandler *hotplug_dev, 826 DeviceState *dev, Error **errp) 827 { 828 if (memhp_type_supported(dev)) { 829 virt_mem_unplug_request(hotplug_dev, dev, errp); 830 } 831 } 832 833 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 834 DeviceState *dev, Error **errp) 835 { 836 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 837 838 hotplug_handler_unplug(HOTPLUG_HANDLER(lvms->acpi_ged), dev, errp); 839 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lvms)); 840 qdev_unrealize(dev); 841 } 842 843 static void virt_device_unplug(HotplugHandler *hotplug_dev, 844 DeviceState *dev, Error **errp) 845 { 846 if (memhp_type_supported(dev)) { 847 virt_mem_unplug(hotplug_dev, dev, errp); 848 } 849 } 850 851 static void virt_mem_plug(HotplugHandler *hotplug_dev, 852 DeviceState *dev, Error **errp) 853 { 854 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 855 856 pc_dimm_plug(PC_DIMM(dev), MACHINE(lvms)); 857 hotplug_handler_plug(HOTPLUG_HANDLER(lvms->acpi_ged), 858 dev, &error_abort); 859 } 860 861 static void virt_device_plug_cb(HotplugHandler *hotplug_dev, 862 DeviceState *dev, Error **errp) 863 { 864 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 865 MachineClass *mc = MACHINE_GET_CLASS(lvms); 866 PlatformBusDevice *pbus; 867 868 if (device_is_dynamic_sysbus(mc, dev)) { 869 if (lvms->platform_bus_dev) { 870 pbus = PLATFORM_BUS_DEVICE(lvms->platform_bus_dev); 871 platform_bus_link_device(pbus, SYS_BUS_DEVICE(dev)); 872 } 873 } else if (memhp_type_supported(dev)) { 874 virt_mem_plug(hotplug_dev, dev, errp); 875 } 876 } 877 878 static HotplugHandler *virt_get_hotplug_handler(MachineState *machine, 879 DeviceState *dev) 880 { 881 MachineClass *mc = MACHINE_GET_CLASS(machine); 882 883 if (device_is_dynamic_sysbus(mc, dev) || 884 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 885 memhp_type_supported(dev)) { 886 return HOTPLUG_HANDLER(machine); 887 } 888 return NULL; 889 } 890 891 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 892 { 893 int n; 894 unsigned int max_cpus = ms->smp.max_cpus; 895 896 if (ms->possible_cpus) { 897 assert(ms->possible_cpus->len == max_cpus); 898 return ms->possible_cpus; 899 } 900 901 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 902 sizeof(CPUArchId) * max_cpus); 903 ms->possible_cpus->len = max_cpus; 904 for (n = 0; n < ms->possible_cpus->len; n++) { 905 ms->possible_cpus->cpus[n].type = ms->cpu_type; 906 ms->possible_cpus->cpus[n].arch_id = n; 907 908 ms->possible_cpus->cpus[n].props.has_socket_id = true; 909 ms->possible_cpus->cpus[n].props.socket_id = 910 n / (ms->smp.cores * ms->smp.threads); 911 ms->possible_cpus->cpus[n].props.has_core_id = true; 912 ms->possible_cpus->cpus[n].props.core_id = 913 n / ms->smp.threads % ms->smp.cores; 914 ms->possible_cpus->cpus[n].props.has_thread_id = true; 915 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 916 } 917 return ms->possible_cpus; 918 } 919 920 static CpuInstanceProperties virt_cpu_index_to_props(MachineState *ms, 921 unsigned cpu_index) 922 { 923 MachineClass *mc = MACHINE_GET_CLASS(ms); 924 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 925 926 assert(cpu_index < possible_cpus->len); 927 return possible_cpus->cpus[cpu_index].props; 928 } 929 930 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 931 { 932 int64_t socket_id; 933 934 if (ms->numa_state->num_nodes) { 935 socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 936 return socket_id % ms->numa_state->num_nodes; 937 } else { 938 return 0; 939 } 940 } 941 942 static void virt_class_init(ObjectClass *oc, void *data) 943 { 944 MachineClass *mc = MACHINE_CLASS(oc); 945 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 946 947 mc->init = virt_init; 948 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 949 mc->default_ram_id = "loongarch.ram"; 950 mc->desc = "QEMU LoongArch Virtual Machine"; 951 mc->max_cpus = LOONGARCH_MAX_CPUS; 952 mc->is_default = 1; 953 mc->default_kernel_irqchip_split = false; 954 mc->block_default_type = IF_VIRTIO; 955 mc->default_boot_order = "c"; 956 mc->no_cdrom = 1; 957 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 958 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 959 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 960 mc->numa_mem_supported = true; 961 mc->auto_enable_numa_with_memhp = true; 962 mc->auto_enable_numa_with_memdev = true; 963 mc->get_hotplug_handler = virt_get_hotplug_handler; 964 mc->default_nic = "virtio-net-pci"; 965 hc->plug = virt_device_plug_cb; 966 hc->pre_plug = virt_device_pre_plug; 967 hc->unplug_request = virt_device_unplug_request; 968 hc->unplug = virt_device_unplug; 969 970 object_class_property_add(oc, "acpi", "OnOffAuto", 971 virt_get_acpi, virt_set_acpi, 972 NULL, NULL); 973 object_class_property_set_description(oc, "acpi", 974 "Enable ACPI"); 975 object_class_property_add(oc, "v-eiointc", "OnOffAuto", 976 virt_get_veiointc, virt_set_veiointc, 977 NULL, NULL); 978 object_class_property_set_description(oc, "v-eiointc", 979 "Enable Virt Extend I/O Interrupt Controller."); 980 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 981 #ifdef CONFIG_TPM 982 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 983 #endif 984 } 985 986 static const TypeInfo virt_machine_types[] = { 987 { 988 .name = TYPE_LOONGARCH_VIRT_MACHINE, 989 .parent = TYPE_MACHINE, 990 .instance_size = sizeof(LoongArchVirtMachineState), 991 .class_init = virt_class_init, 992 .instance_init = virt_initfn, 993 .interfaces = (InterfaceInfo[]) { 994 { TYPE_HOTPLUG_HANDLER }, 995 { } 996 }, 997 } 998 }; 999 1000 DEFINE_TYPES(virt_machine_types) 1001