1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial-mm.h" 13 #include "system/kvm.h" 14 #include "system/tcg.h" 15 #include "system/system.h" 16 #include "system/qtest.h" 17 #include "system/runstate.h" 18 #include "system/reset.h" 19 #include "system/rtc.h" 20 #include "hw/loongarch/virt.h" 21 #include "exec/address-spaces.h" 22 #include "hw/irq.h" 23 #include "net/net.h" 24 #include "hw/loader.h" 25 #include "elf.h" 26 #include "hw/intc/loongarch_ipi.h" 27 #include "hw/intc/loongarch_extioi.h" 28 #include "hw/intc/loongarch_pch_pic.h" 29 #include "hw/intc/loongarch_pch_msi.h" 30 #include "hw/pci-host/ls7a.h" 31 #include "hw/pci-host/gpex.h" 32 #include "hw/misc/unimp.h" 33 #include "hw/loongarch/fw_cfg.h" 34 #include "target/loongarch/cpu.h" 35 #include "hw/firmware/smbios.h" 36 #include "qapi/qapi-visit-common.h" 37 #include "hw/acpi/generic_event_device.h" 38 #include "hw/mem/nvdimm.h" 39 #include "hw/platform-bus.h" 40 #include "hw/display/ramfb.h" 41 #include "hw/mem/pc-dimm.h" 42 #include "system/tpm.h" 43 #include "system/block-backend.h" 44 #include "hw/block/flash.h" 45 #include "hw/virtio/virtio-iommu.h" 46 #include "qemu/error-report.h" 47 48 static void virt_get_veiointc(Object *obj, Visitor *v, const char *name, 49 void *opaque, Error **errp) 50 { 51 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 52 OnOffAuto veiointc = lvms->veiointc; 53 54 visit_type_OnOffAuto(v, name, &veiointc, errp); 55 } 56 57 static void virt_set_veiointc(Object *obj, Visitor *v, const char *name, 58 void *opaque, Error **errp) 59 { 60 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 61 62 visit_type_OnOffAuto(v, name, &lvms->veiointc, errp); 63 } 64 65 static PFlashCFI01 *virt_flash_create1(LoongArchVirtMachineState *lvms, 66 const char *name, 67 const char *alias_prop_name) 68 { 69 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 70 71 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 72 qdev_prop_set_uint8(dev, "width", 4); 73 qdev_prop_set_uint8(dev, "device-width", 2); 74 qdev_prop_set_bit(dev, "big-endian", false); 75 qdev_prop_set_uint16(dev, "id0", 0x89); 76 qdev_prop_set_uint16(dev, "id1", 0x18); 77 qdev_prop_set_uint16(dev, "id2", 0x00); 78 qdev_prop_set_uint16(dev, "id3", 0x00); 79 qdev_prop_set_string(dev, "name", name); 80 object_property_add_child(OBJECT(lvms), name, OBJECT(dev)); 81 object_property_add_alias(OBJECT(lvms), alias_prop_name, 82 OBJECT(dev), "drive"); 83 return PFLASH_CFI01(dev); 84 } 85 86 static void virt_flash_create(LoongArchVirtMachineState *lvms) 87 { 88 lvms->flash[0] = virt_flash_create1(lvms, "virt.flash0", "pflash0"); 89 lvms->flash[1] = virt_flash_create1(lvms, "virt.flash1", "pflash1"); 90 } 91 92 static void virt_flash_map1(PFlashCFI01 *flash, 93 hwaddr base, hwaddr size, 94 MemoryRegion *sysmem) 95 { 96 DeviceState *dev = DEVICE(flash); 97 BlockBackend *blk; 98 hwaddr real_size = size; 99 100 blk = pflash_cfi01_get_blk(flash); 101 if (blk) { 102 real_size = blk_getlength(blk); 103 assert(real_size && real_size <= size); 104 } 105 106 assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE)); 107 assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 108 109 qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE); 110 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 111 memory_region_add_subregion(sysmem, base, 112 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 113 } 114 115 static void virt_flash_map(LoongArchVirtMachineState *lvms, 116 MemoryRegion *sysmem) 117 { 118 PFlashCFI01 *flash0 = lvms->flash[0]; 119 PFlashCFI01 *flash1 = lvms->flash[1]; 120 121 virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem); 122 virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem); 123 } 124 125 static void virt_build_smbios(LoongArchVirtMachineState *lvms) 126 { 127 MachineState *ms = MACHINE(lvms); 128 MachineClass *mc = MACHINE_GET_CLASS(lvms); 129 uint8_t *smbios_tables, *smbios_anchor; 130 size_t smbios_tables_len, smbios_anchor_len; 131 const char *product = "QEMU Virtual Machine"; 132 133 if (!lvms->fw_cfg) { 134 return; 135 } 136 137 smbios_set_defaults("QEMU", product, mc->name); 138 139 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 140 NULL, 0, 141 &smbios_tables, &smbios_tables_len, 142 &smbios_anchor, &smbios_anchor_len, &error_fatal); 143 144 if (smbios_anchor) { 145 fw_cfg_add_file(lvms->fw_cfg, "etc/smbios/smbios-tables", 146 smbios_tables, smbios_tables_len); 147 fw_cfg_add_file(lvms->fw_cfg, "etc/smbios/smbios-anchor", 148 smbios_anchor, smbios_anchor_len); 149 } 150 } 151 152 static void virt_done(Notifier *notifier, void *data) 153 { 154 LoongArchVirtMachineState *lvms = container_of(notifier, 155 LoongArchVirtMachineState, machine_done); 156 virt_build_smbios(lvms); 157 virt_acpi_setup(lvms); 158 virt_fdt_setup(lvms); 159 } 160 161 static void virt_powerdown_req(Notifier *notifier, void *opaque) 162 { 163 LoongArchVirtMachineState *s; 164 165 s = container_of(notifier, LoongArchVirtMachineState, powerdown_notifier); 166 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 167 } 168 169 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 170 { 171 /* Ensure there are no duplicate entries. */ 172 for (unsigned i = 0; i < memmap_entries; i++) { 173 assert(memmap_table[i].address != address); 174 } 175 176 memmap_table = g_renew(struct memmap_entry, memmap_table, 177 memmap_entries + 1); 178 memmap_table[memmap_entries].address = cpu_to_le64(address); 179 memmap_table[memmap_entries].length = cpu_to_le64(length); 180 memmap_table[memmap_entries].type = cpu_to_le32(type); 181 memmap_table[memmap_entries].reserved = 0; 182 memmap_entries++; 183 } 184 185 static DeviceState *create_acpi_ged(DeviceState *pch_pic, 186 LoongArchVirtMachineState *lvms) 187 { 188 DeviceState *dev; 189 MachineState *ms = MACHINE(lvms); 190 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 191 192 if (ms->ram_slots) { 193 event |= ACPI_GED_MEM_HOTPLUG_EVT; 194 } 195 dev = qdev_new(TYPE_ACPI_GED); 196 qdev_prop_set_uint32(dev, "ged-event", event); 197 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 198 199 /* ged event */ 200 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 201 /* memory hotplug */ 202 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 203 /* ged regs used for reset and power down */ 204 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 205 206 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 207 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 208 return dev; 209 } 210 211 static DeviceState *create_platform_bus(DeviceState *pch_pic) 212 { 213 DeviceState *dev; 214 SysBusDevice *sysbus; 215 int i, irq; 216 MemoryRegion *sysmem = get_system_memory(); 217 218 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 219 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 220 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 221 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 222 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 223 224 sysbus = SYS_BUS_DEVICE(dev); 225 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 226 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 227 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 228 } 229 230 memory_region_add_subregion(sysmem, 231 VIRT_PLATFORM_BUS_BASEADDRESS, 232 sysbus_mmio_get_region(sysbus, 0)); 233 return dev; 234 } 235 236 static void virt_devices_init(DeviceState *pch_pic, 237 LoongArchVirtMachineState *lvms) 238 { 239 MachineClass *mc = MACHINE_GET_CLASS(lvms); 240 DeviceState *gpex_dev; 241 SysBusDevice *d; 242 PCIBus *pci_bus; 243 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 244 MemoryRegion *mmio_alias, *mmio_reg; 245 int i; 246 247 gpex_dev = qdev_new(TYPE_GPEX_HOST); 248 d = SYS_BUS_DEVICE(gpex_dev); 249 sysbus_realize_and_unref(d, &error_fatal); 250 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 251 lvms->pci_bus = pci_bus; 252 253 /* Map only part size_ecam bytes of ECAM space */ 254 ecam_alias = g_new0(MemoryRegion, 1); 255 ecam_reg = sysbus_mmio_get_region(d, 0); 256 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 257 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 258 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 259 ecam_alias); 260 261 /* Map PCI mem space */ 262 mmio_alias = g_new0(MemoryRegion, 1); 263 mmio_reg = sysbus_mmio_get_region(d, 1); 264 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 265 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 266 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 267 mmio_alias); 268 269 /* Map PCI IO port space. */ 270 pio_alias = g_new0(MemoryRegion, 1); 271 pio_reg = sysbus_mmio_get_region(d, 2); 272 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 273 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 274 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 275 pio_alias); 276 277 for (i = 0; i < PCI_NUM_PINS; i++) { 278 sysbus_connect_irq(d, i, 279 qdev_get_gpio_in(pch_pic, 16 + i)); 280 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 281 } 282 283 /* 284 * Create uart fdt node in reverse order so that they appear 285 * in the finished device tree lowest address first 286 */ 287 for (i = VIRT_UART_COUNT; i-- > 0;) { 288 hwaddr base = VIRT_UART_BASE + i * VIRT_UART_SIZE; 289 int irq = VIRT_UART_IRQ + i - VIRT_GSI_BASE; 290 serial_mm_init(get_system_memory(), base, 0, 291 qdev_get_gpio_in(pch_pic, irq), 292 115200, serial_hd(i), DEVICE_LITTLE_ENDIAN); 293 } 294 295 /* Network init */ 296 pci_init_nic_devices(pci_bus, mc->default_nic); 297 298 /* 299 * There are some invalid guest memory access. 300 * Create some unimplemented devices to emulate this. 301 */ 302 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 303 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 304 qdev_get_gpio_in(pch_pic, 305 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 306 307 /* acpi ged */ 308 lvms->acpi_ged = create_acpi_ged(pch_pic, lvms); 309 /* platform bus */ 310 lvms->platform_bus_dev = create_platform_bus(pch_pic); 311 } 312 313 static void virt_cpu_irq_init(LoongArchVirtMachineState *lvms) 314 { 315 int num, pin; 316 MachineState *ms = MACHINE(lvms); 317 MachineClass *mc = MACHINE_GET_CLASS(ms); 318 const CPUArchIdList *possible_cpus; 319 CPUState *cs; 320 321 /* cpu nodes */ 322 possible_cpus = mc->possible_cpu_arch_ids(ms); 323 for (num = 0; num < possible_cpus->len; num++) { 324 cs = possible_cpus->cpus[num].cpu; 325 if (cs == NULL) { 326 continue; 327 } 328 329 /* connect ipi irq to cpu irq */ 330 qdev_connect_gpio_out(lvms->ipi, num, 331 qdev_get_gpio_in(DEVICE(cs), IRQ_IPI)); 332 333 /* 334 * connect ext irq to the cpu irq 335 * cpu_pin[9:2] <= intc_pin[7:0] 336 */ 337 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 338 qdev_connect_gpio_out(lvms->extioi, (num * LS3A_INTC_IP + pin), 339 qdev_get_gpio_in(DEVICE(cs), pin + 2)); 340 } 341 } 342 } 343 344 static void virt_irq_init(LoongArchVirtMachineState *lvms) 345 { 346 DeviceState *pch_pic, *pch_msi; 347 DeviceState *ipi, *extioi; 348 SysBusDevice *d; 349 int i, start, num; 350 351 /* 352 * Extended IRQ model. 353 * | 354 * +-----------+ +-------------|--------+ +-----------+ 355 * | IPI/Timer | --> | CPUINTC(0-3)|(4-255) | <-- | IPI/Timer | 356 * +-----------+ +-------------|--------+ +-----------+ 357 * ^ | 358 * | 359 * +---------+ 360 * | EIOINTC | 361 * +---------+ 362 * ^ ^ 363 * | | 364 * +---------+ +---------+ 365 * | PCH-PIC | | PCH-MSI | 366 * +---------+ +---------+ 367 * ^ ^ ^ 368 * | | | 369 * +--------+ +---------+ +---------+ 370 * | UARTs | | Devices | | Devices | 371 * +--------+ +---------+ +---------+ 372 * 373 * Virt extended IRQ model. 374 * 375 * +-----+ +---------------+ +-------+ 376 * | IPI |--> | CPUINTC(0-255)| <-- | Timer | 377 * +-----+ +---------------+ +-------+ 378 * ^ 379 * | 380 * +-----------+ 381 * | V-EIOINTC | 382 * +-----------+ 383 * ^ ^ 384 * | | 385 * +---------+ +---------+ 386 * | PCH-PIC | | PCH-MSI | 387 * +---------+ +---------+ 388 * ^ ^ ^ 389 * | | | 390 * +--------+ +---------+ +---------+ 391 * | UARTs | | Devices | | Devices | 392 * +--------+ +---------+ +---------+ 393 */ 394 395 /* Create IPI device */ 396 ipi = qdev_new(TYPE_LOONGARCH_IPI); 397 lvms->ipi = ipi; 398 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 399 400 /* IPI iocsr memory region */ 401 memory_region_add_subregion(&lvms->system_iocsr, SMP_IPI_MAILBOX, 402 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); 403 memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR, 404 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); 405 406 /* Create EXTIOI device */ 407 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 408 lvms->extioi = extioi; 409 if (virt_is_veiointc_enabled(lvms)) { 410 qdev_prop_set_bit(extioi, "has-virtualization-extension", true); 411 } 412 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 413 memory_region_add_subregion(&lvms->system_iocsr, APIC_BASE, 414 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); 415 if (virt_is_veiointc_enabled(lvms)) { 416 memory_region_add_subregion(&lvms->system_iocsr, EXTIOI_VIRT_BASE, 417 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 1)); 418 } 419 420 virt_cpu_irq_init(lvms); 421 pch_pic = qdev_new(TYPE_LOONGARCH_PIC); 422 num = VIRT_PCH_PIC_IRQ_NUM; 423 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 424 d = SYS_BUS_DEVICE(pch_pic); 425 sysbus_realize_and_unref(d, &error_fatal); 426 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 427 sysbus_mmio_get_region(d, 0)); 428 memory_region_add_subregion(get_system_memory(), 429 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 430 sysbus_mmio_get_region(d, 1)); 431 memory_region_add_subregion(get_system_memory(), 432 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 433 sysbus_mmio_get_region(d, 2)); 434 435 /* Connect pch_pic irqs to extioi */ 436 for (i = 0; i < num; i++) { 437 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 438 } 439 440 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 441 start = num; 442 num = EXTIOI_IRQS - start; 443 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 444 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 445 d = SYS_BUS_DEVICE(pch_msi); 446 sysbus_realize_and_unref(d, &error_fatal); 447 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 448 for (i = 0; i < num; i++) { 449 /* Connect pch_msi irqs to extioi */ 450 qdev_connect_gpio_out(DEVICE(d), i, 451 qdev_get_gpio_in(extioi, i + start)); 452 } 453 454 virt_devices_init(pch_pic, lvms); 455 } 456 457 static void virt_firmware_init(LoongArchVirtMachineState *lvms) 458 { 459 char *filename = MACHINE(lvms)->firmware; 460 char *bios_name = NULL; 461 int bios_size, i; 462 BlockBackend *pflash_blk0; 463 MemoryRegion *mr; 464 465 lvms->bios_loaded = false; 466 467 /* Map legacy -drive if=pflash to machine properties */ 468 for (i = 0; i < ARRAY_SIZE(lvms->flash); i++) { 469 pflash_cfi01_legacy_drive(lvms->flash[i], 470 drive_get(IF_PFLASH, 0, i)); 471 } 472 473 virt_flash_map(lvms, get_system_memory()); 474 475 pflash_blk0 = pflash_cfi01_get_blk(lvms->flash[0]); 476 477 if (pflash_blk0) { 478 if (filename) { 479 error_report("cannot use both '-bios' and '-drive if=pflash'" 480 "options at once"); 481 exit(1); 482 } 483 lvms->bios_loaded = true; 484 return; 485 } 486 487 if (filename) { 488 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 489 if (!bios_name) { 490 error_report("Could not find ROM image '%s'", filename); 491 exit(1); 492 } 493 494 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lvms->flash[0]), 0); 495 bios_size = load_image_mr(bios_name, mr); 496 if (bios_size < 0) { 497 error_report("Could not load ROM image '%s'", bios_name); 498 exit(1); 499 } 500 g_free(bios_name); 501 lvms->bios_loaded = true; 502 } 503 } 504 505 static MemTxResult virt_iocsr_misc_write(void *opaque, hwaddr addr, 506 uint64_t val, unsigned size, 507 MemTxAttrs attrs) 508 { 509 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(opaque); 510 uint64_t features; 511 512 switch (addr) { 513 case MISC_FUNC_REG: 514 if (!virt_is_veiointc_enabled(lvms)) { 515 return MEMTX_OK; 516 } 517 518 features = address_space_ldl(&lvms->as_iocsr, 519 EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, 520 attrs, NULL); 521 if (val & BIT_ULL(IOCSRM_EXTIOI_EN)) { 522 features |= BIT(EXTIOI_ENABLE); 523 } 524 if (val & BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE)) { 525 features |= BIT(EXTIOI_ENABLE_INT_ENCODE); 526 } 527 528 address_space_stl(&lvms->as_iocsr, 529 EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, 530 features, attrs, NULL); 531 break; 532 default: 533 g_assert_not_reached(); 534 } 535 536 return MEMTX_OK; 537 } 538 539 static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr, 540 uint64_t *data, 541 unsigned size, MemTxAttrs attrs) 542 { 543 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(opaque); 544 uint64_t ret = 0; 545 int features; 546 547 switch (addr) { 548 case VERSION_REG: 549 ret = 0x11ULL; 550 break; 551 case FEATURE_REG: 552 ret = BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); 553 if (kvm_enabled()) { 554 ret |= BIT(IOCSRF_VM); 555 } 556 break; 557 case VENDOR_REG: 558 ret = 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 559 break; 560 case CPUNAME_REG: 561 ret = 0x303030354133ULL; /* "3A5000" */ 562 break; 563 case MISC_FUNC_REG: 564 if (!virt_is_veiointc_enabled(lvms)) { 565 ret |= BIT_ULL(IOCSRM_EXTIOI_EN); 566 break; 567 } 568 569 features = address_space_ldl(&lvms->as_iocsr, 570 EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG, 571 attrs, NULL); 572 if (features & BIT(EXTIOI_ENABLE)) { 573 ret |= BIT_ULL(IOCSRM_EXTIOI_EN); 574 } 575 if (features & BIT(EXTIOI_ENABLE_INT_ENCODE)) { 576 ret |= BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE); 577 } 578 break; 579 default: 580 g_assert_not_reached(); 581 } 582 583 *data = ret; 584 return MEMTX_OK; 585 } 586 587 static const MemoryRegionOps virt_iocsr_misc_ops = { 588 .read_with_attrs = virt_iocsr_misc_read, 589 .write_with_attrs = virt_iocsr_misc_write, 590 .endianness = DEVICE_LITTLE_ENDIAN, 591 .valid = { 592 .min_access_size = 4, 593 .max_access_size = 8, 594 }, 595 .impl = { 596 .min_access_size = 8, 597 .max_access_size = 8, 598 }, 599 }; 600 601 static void fw_cfg_add_memory(MachineState *ms) 602 { 603 hwaddr base, size, ram_size, gap; 604 int nb_numa_nodes, nodes; 605 NodeInfo *numa_info; 606 607 ram_size = ms->ram_size; 608 base = VIRT_LOWMEM_BASE; 609 gap = VIRT_LOWMEM_SIZE; 610 nodes = nb_numa_nodes = ms->numa_state->num_nodes; 611 numa_info = ms->numa_state->nodes; 612 if (!nodes) { 613 nodes = 1; 614 } 615 616 /* add fw_cfg memory map of node0 */ 617 if (nb_numa_nodes) { 618 size = numa_info[0].node_mem; 619 } else { 620 size = ram_size; 621 } 622 623 if (size >= gap) { 624 memmap_add_entry(base, gap, 1); 625 size -= gap; 626 base = VIRT_HIGHMEM_BASE; 627 } 628 629 if (size) { 630 memmap_add_entry(base, size, 1); 631 base += size; 632 } 633 634 if (nodes < 2) { 635 return; 636 } 637 638 /* add fw_cfg memory map of other nodes */ 639 if (numa_info[0].node_mem < gap && ram_size > gap) { 640 /* 641 * memory map for the maining nodes splited into two part 642 * lowram: [base, +(gap - numa_info[0].node_mem)) 643 * highram: [VIRT_HIGHMEM_BASE, +(ram_size - gap)) 644 */ 645 memmap_add_entry(base, gap - numa_info[0].node_mem, 1); 646 size = ram_size - gap; 647 base = VIRT_HIGHMEM_BASE; 648 } else { 649 size = ram_size - numa_info[0].node_mem; 650 } 651 652 if (size) { 653 memmap_add_entry(base, size, 1); 654 } 655 } 656 657 static void virt_init(MachineState *machine) 658 { 659 LoongArchCPU *lacpu; 660 const char *cpu_model = machine->cpu_type; 661 MemoryRegion *address_space_mem = get_system_memory(); 662 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine); 663 int i; 664 hwaddr base, size, ram_size = machine->ram_size; 665 const CPUArchIdList *possible_cpus; 666 MachineClass *mc = MACHINE_GET_CLASS(machine); 667 CPUState *cpu; 668 669 if (!cpu_model) { 670 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 671 } 672 673 /* Create IOCSR space */ 674 memory_region_init_io(&lvms->system_iocsr, OBJECT(machine), NULL, 675 machine, "iocsr", UINT64_MAX); 676 address_space_init(&lvms->as_iocsr, &lvms->system_iocsr, "IOCSR"); 677 memory_region_init_io(&lvms->iocsr_mem, OBJECT(machine), 678 &virt_iocsr_misc_ops, 679 machine, "iocsr_misc", 0x428); 680 memory_region_add_subregion(&lvms->system_iocsr, 0, &lvms->iocsr_mem); 681 682 /* Init CPUs */ 683 possible_cpus = mc->possible_cpu_arch_ids(machine); 684 for (i = 0; i < possible_cpus->len; i++) { 685 cpu = cpu_create(machine->cpu_type); 686 cpu->cpu_index = i; 687 machine->possible_cpus->cpus[i].cpu = cpu; 688 lacpu = LOONGARCH_CPU(cpu); 689 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; 690 lacpu->env.address_space_iocsr = &lvms->as_iocsr; 691 } 692 fw_cfg_add_memory(machine); 693 694 /* Node0 memory */ 695 size = ram_size; 696 base = VIRT_LOWMEM_BASE; 697 if (size > VIRT_LOWMEM_SIZE) { 698 size = VIRT_LOWMEM_SIZE; 699 } 700 701 memory_region_init_alias(&lvms->lowmem, NULL, "loongarch.lowram", 702 machine->ram, base, size); 703 memory_region_add_subregion(address_space_mem, base, &lvms->lowmem); 704 base += size; 705 if (ram_size - size) { 706 base = VIRT_HIGHMEM_BASE; 707 memory_region_init_alias(&lvms->highmem, NULL, "loongarch.highram", 708 machine->ram, VIRT_LOWMEM_BASE + size, ram_size - size); 709 memory_region_add_subregion(address_space_mem, base, &lvms->highmem); 710 base += ram_size - size; 711 } 712 713 /* initialize device memory address space */ 714 if (machine->ram_size < machine->maxram_size) { 715 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 716 717 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 718 error_report("unsupported amount of memory slots: %"PRIu64, 719 machine->ram_slots); 720 exit(EXIT_FAILURE); 721 } 722 723 if (QEMU_ALIGN_UP(machine->maxram_size, 724 TARGET_PAGE_SIZE) != machine->maxram_size) { 725 error_report("maximum memory size must by aligned to multiple of " 726 "%d bytes", TARGET_PAGE_SIZE); 727 exit(EXIT_FAILURE); 728 } 729 machine_memory_devices_init(machine, base, device_mem_size); 730 } 731 732 /* load the BIOS image. */ 733 virt_firmware_init(lvms); 734 735 /* fw_cfg init */ 736 lvms->fw_cfg = virt_fw_cfg_init(ram_size, machine); 737 rom_set_fw(lvms->fw_cfg); 738 if (lvms->fw_cfg != NULL) { 739 fw_cfg_add_file(lvms->fw_cfg, "etc/memmap", 740 memmap_table, 741 sizeof(struct memmap_entry) * (memmap_entries)); 742 } 743 744 /* Initialize the IO interrupt subsystem */ 745 virt_irq_init(lvms); 746 lvms->machine_done.notify = virt_done; 747 qemu_add_machine_init_done_notifier(&lvms->machine_done); 748 /* connect powerdown request */ 749 lvms->powerdown_notifier.notify = virt_powerdown_req; 750 qemu_register_powerdown_notifier(&lvms->powerdown_notifier); 751 752 lvms->bootinfo.ram_size = ram_size; 753 loongarch_load_kernel(machine, &lvms->bootinfo); 754 } 755 756 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 757 void *opaque, Error **errp) 758 { 759 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 760 OnOffAuto acpi = lvms->acpi; 761 762 visit_type_OnOffAuto(v, name, &acpi, errp); 763 } 764 765 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 766 void *opaque, Error **errp) 767 { 768 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 769 770 visit_type_OnOffAuto(v, name, &lvms->acpi, errp); 771 } 772 773 static void virt_initfn(Object *obj) 774 { 775 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 776 777 if (tcg_enabled()) { 778 lvms->veiointc = ON_OFF_AUTO_OFF; 779 } 780 lvms->acpi = ON_OFF_AUTO_AUTO; 781 lvms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 782 lvms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 783 virt_flash_create(lvms); 784 } 785 786 static bool memhp_type_supported(DeviceState *dev) 787 { 788 /* we only support pc dimm now */ 789 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 790 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 791 } 792 793 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 794 Error **errp) 795 { 796 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 797 } 798 799 static void virt_device_pre_plug(HotplugHandler *hotplug_dev, 800 DeviceState *dev, Error **errp) 801 { 802 if (memhp_type_supported(dev)) { 803 virt_mem_pre_plug(hotplug_dev, dev, errp); 804 } 805 } 806 807 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 808 DeviceState *dev, Error **errp) 809 { 810 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 811 812 /* the acpi ged is always exist */ 813 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lvms->acpi_ged), dev, 814 errp); 815 } 816 817 static void virt_device_unplug_request(HotplugHandler *hotplug_dev, 818 DeviceState *dev, Error **errp) 819 { 820 if (memhp_type_supported(dev)) { 821 virt_mem_unplug_request(hotplug_dev, dev, errp); 822 } 823 } 824 825 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 826 DeviceState *dev, Error **errp) 827 { 828 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 829 830 hotplug_handler_unplug(HOTPLUG_HANDLER(lvms->acpi_ged), dev, errp); 831 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lvms)); 832 qdev_unrealize(dev); 833 } 834 835 static void virt_device_unplug(HotplugHandler *hotplug_dev, 836 DeviceState *dev, Error **errp) 837 { 838 if (memhp_type_supported(dev)) { 839 virt_mem_unplug(hotplug_dev, dev, errp); 840 } 841 } 842 843 static void virt_mem_plug(HotplugHandler *hotplug_dev, 844 DeviceState *dev, Error **errp) 845 { 846 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 847 848 pc_dimm_plug(PC_DIMM(dev), MACHINE(lvms)); 849 hotplug_handler_plug(HOTPLUG_HANDLER(lvms->acpi_ged), 850 dev, &error_abort); 851 } 852 853 static void virt_device_plug_cb(HotplugHandler *hotplug_dev, 854 DeviceState *dev, Error **errp) 855 { 856 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 857 MachineClass *mc = MACHINE_GET_CLASS(lvms); 858 PlatformBusDevice *pbus; 859 860 if (device_is_dynamic_sysbus(mc, dev)) { 861 if (lvms->platform_bus_dev) { 862 pbus = PLATFORM_BUS_DEVICE(lvms->platform_bus_dev); 863 platform_bus_link_device(pbus, SYS_BUS_DEVICE(dev)); 864 } 865 } else if (memhp_type_supported(dev)) { 866 virt_mem_plug(hotplug_dev, dev, errp); 867 } 868 } 869 870 static HotplugHandler *virt_get_hotplug_handler(MachineState *machine, 871 DeviceState *dev) 872 { 873 MachineClass *mc = MACHINE_GET_CLASS(machine); 874 875 if (device_is_dynamic_sysbus(mc, dev) || 876 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 877 memhp_type_supported(dev)) { 878 return HOTPLUG_HANDLER(machine); 879 } 880 return NULL; 881 } 882 883 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 884 { 885 int n; 886 unsigned int max_cpus = ms->smp.max_cpus; 887 888 if (ms->possible_cpus) { 889 assert(ms->possible_cpus->len == max_cpus); 890 return ms->possible_cpus; 891 } 892 893 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 894 sizeof(CPUArchId) * max_cpus); 895 ms->possible_cpus->len = max_cpus; 896 for (n = 0; n < ms->possible_cpus->len; n++) { 897 ms->possible_cpus->cpus[n].type = ms->cpu_type; 898 ms->possible_cpus->cpus[n].arch_id = n; 899 900 ms->possible_cpus->cpus[n].props.has_socket_id = true; 901 ms->possible_cpus->cpus[n].props.socket_id = 902 n / (ms->smp.cores * ms->smp.threads); 903 ms->possible_cpus->cpus[n].props.has_core_id = true; 904 ms->possible_cpus->cpus[n].props.core_id = 905 n / ms->smp.threads % ms->smp.cores; 906 ms->possible_cpus->cpus[n].props.has_thread_id = true; 907 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 908 } 909 return ms->possible_cpus; 910 } 911 912 static CpuInstanceProperties virt_cpu_index_to_props(MachineState *ms, 913 unsigned cpu_index) 914 { 915 MachineClass *mc = MACHINE_GET_CLASS(ms); 916 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 917 918 assert(cpu_index < possible_cpus->len); 919 return possible_cpus->cpus[cpu_index].props; 920 } 921 922 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 923 { 924 int64_t socket_id; 925 926 if (ms->numa_state->num_nodes) { 927 socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 928 return socket_id % ms->numa_state->num_nodes; 929 } else { 930 return 0; 931 } 932 } 933 934 static void virt_class_init(ObjectClass *oc, void *data) 935 { 936 MachineClass *mc = MACHINE_CLASS(oc); 937 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 938 939 mc->init = virt_init; 940 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 941 mc->default_ram_id = "loongarch.ram"; 942 mc->desc = "QEMU LoongArch Virtual Machine"; 943 mc->max_cpus = LOONGARCH_MAX_CPUS; 944 mc->is_default = 1; 945 mc->default_kernel_irqchip_split = false; 946 mc->block_default_type = IF_VIRTIO; 947 mc->default_boot_order = "c"; 948 mc->no_cdrom = 1; 949 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 950 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 951 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 952 mc->numa_mem_supported = true; 953 mc->auto_enable_numa_with_memhp = true; 954 mc->auto_enable_numa_with_memdev = true; 955 mc->get_hotplug_handler = virt_get_hotplug_handler; 956 mc->default_nic = "virtio-net-pci"; 957 hc->plug = virt_device_plug_cb; 958 hc->pre_plug = virt_device_pre_plug; 959 hc->unplug_request = virt_device_unplug_request; 960 hc->unplug = virt_device_unplug; 961 962 object_class_property_add(oc, "acpi", "OnOffAuto", 963 virt_get_acpi, virt_set_acpi, 964 NULL, NULL); 965 object_class_property_set_description(oc, "acpi", 966 "Enable ACPI"); 967 object_class_property_add(oc, "v-eiointc", "OnOffAuto", 968 virt_get_veiointc, virt_set_veiointc, 969 NULL, NULL); 970 object_class_property_set_description(oc, "v-eiointc", 971 "Enable Virt Extend I/O Interrupt Controller."); 972 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 973 #ifdef CONFIG_TPM 974 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 975 #endif 976 } 977 978 static const TypeInfo virt_machine_types[] = { 979 { 980 .name = TYPE_LOONGARCH_VIRT_MACHINE, 981 .parent = TYPE_MACHINE, 982 .instance_size = sizeof(LoongArchVirtMachineState), 983 .class_init = virt_class_init, 984 .instance_init = virt_initfn, 985 .interfaces = (InterfaceInfo[]) { 986 { TYPE_HOTPLUG_HANDLER }, 987 { } 988 }, 989 } 990 }; 991 992 DEFINE_TYPES(virt_machine_types) 993