1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/sysemu.h" 14 #include "sysemu/qtest.h" 15 #include "sysemu/runstate.h" 16 #include "sysemu/reset.h" 17 #include "sysemu/rtc.h" 18 #include "hw/loongarch/virt.h" 19 #include "exec/address-spaces.h" 20 #include "hw/irq.h" 21 #include "net/net.h" 22 #include "hw/loader.h" 23 #include "elf.h" 24 #include "hw/intc/loongarch_ipi.h" 25 #include "hw/intc/loongarch_extioi.h" 26 #include "hw/intc/loongarch_pch_pic.h" 27 #include "hw/intc/loongarch_pch_msi.h" 28 #include "hw/pci-host/ls7a.h" 29 #include "hw/pci-host/gpex.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/loongarch/fw_cfg.h" 32 #include "target/loongarch/cpu.h" 33 #include "hw/firmware/smbios.h" 34 #include "hw/acpi/aml-build.h" 35 #include "qapi/qapi-visit-common.h" 36 #include "hw/acpi/generic_event_device.h" 37 #include "hw/mem/nvdimm.h" 38 #include "sysemu/device_tree.h" 39 #include <libfdt.h> 40 #include "hw/core/sysbus-fdt.h" 41 #include "hw/platform-bus.h" 42 #include "hw/display/ramfb.h" 43 #include "hw/mem/pc-dimm.h" 44 #include "sysemu/tpm.h" 45 #include "sysemu/block-backend.h" 46 #include "hw/block/flash.h" 47 #include "qemu/error-report.h" 48 49 50 struct loaderparams { 51 uint64_t ram_size; 52 const char *kernel_filename; 53 const char *kernel_cmdline; 54 const char *initrd_filename; 55 }; 56 57 static void virt_flash_create(LoongArchMachineState *lams) 58 { 59 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 60 61 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 62 qdev_prop_set_uint8(dev, "width", 4); 63 qdev_prop_set_uint8(dev, "device-width", 2); 64 qdev_prop_set_bit(dev, "big-endian", false); 65 qdev_prop_set_uint16(dev, "id0", 0x89); 66 qdev_prop_set_uint16(dev, "id1", 0x18); 67 qdev_prop_set_uint16(dev, "id2", 0x00); 68 qdev_prop_set_uint16(dev, "id3", 0x00); 69 qdev_prop_set_string(dev, "name", "virt.flash"); 70 object_property_add_child(OBJECT(lams), "virt.flash", OBJECT(dev)); 71 object_property_add_alias(OBJECT(lams), "pflash", 72 OBJECT(dev), "drive"); 73 74 lams->flash = PFLASH_CFI01(dev); 75 } 76 77 static void virt_flash_map(LoongArchMachineState *lams, 78 MemoryRegion *sysmem) 79 { 80 PFlashCFI01 *flash = lams->flash; 81 DeviceState *dev = DEVICE(flash); 82 hwaddr base = VIRT_FLASH_BASE; 83 hwaddr size = VIRT_FLASH_SIZE; 84 85 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 86 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 87 88 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 89 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 90 memory_region_add_subregion(sysmem, base, 91 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 92 93 } 94 95 static void fdt_add_flash_node(LoongArchMachineState *lams) 96 { 97 MachineState *ms = MACHINE(lams); 98 char *nodename; 99 100 hwaddr flash_base = VIRT_FLASH_BASE; 101 hwaddr flash_size = VIRT_FLASH_SIZE; 102 103 nodename = g_strdup_printf("/flash@%" PRIx64, flash_base); 104 qemu_fdt_add_subnode(ms->fdt, nodename); 105 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 106 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 107 2, flash_base, 2, flash_size); 108 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 109 g_free(nodename); 110 } 111 112 static void fdt_add_rtc_node(LoongArchMachineState *lams) 113 { 114 char *nodename; 115 hwaddr base = VIRT_RTC_REG_BASE; 116 hwaddr size = VIRT_RTC_LEN; 117 MachineState *ms = MACHINE(lams); 118 119 nodename = g_strdup_printf("/rtc@%" PRIx64, base); 120 qemu_fdt_add_subnode(ms->fdt, nodename); 121 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc"); 122 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 123 g_free(nodename); 124 } 125 126 static void fdt_add_uart_node(LoongArchMachineState *lams) 127 { 128 char *nodename; 129 hwaddr base = VIRT_UART_BASE; 130 hwaddr size = VIRT_UART_SIZE; 131 MachineState *ms = MACHINE(lams); 132 133 nodename = g_strdup_printf("/serial@%" PRIx64, base); 134 qemu_fdt_add_subnode(ms->fdt, nodename); 135 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); 136 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); 137 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); 138 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 139 g_free(nodename); 140 } 141 142 static void create_fdt(LoongArchMachineState *lams) 143 { 144 MachineState *ms = MACHINE(lams); 145 146 ms->fdt = create_device_tree(&lams->fdt_size); 147 if (!ms->fdt) { 148 error_report("create_device_tree() failed"); 149 exit(1); 150 } 151 152 /* Header */ 153 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 154 "linux,dummy-loongson3"); 155 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 156 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 157 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 158 } 159 160 static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) 161 { 162 int num; 163 const MachineState *ms = MACHINE(lams); 164 int smp_cpus = ms->smp.cpus; 165 166 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 167 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 168 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 169 170 /* cpu nodes */ 171 for (num = smp_cpus - 1; num >= 0; num--) { 172 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 173 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 174 CPUState *cs = CPU(cpu); 175 176 qemu_fdt_add_subnode(ms->fdt, nodename); 177 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 178 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 179 cpu->dtb_compatible); 180 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 181 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 182 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 183 } 184 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 185 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 186 qemu_fdt_alloc_phandle(ms->fdt)); 187 g_free(nodename); 188 } 189 190 /*cpu map */ 191 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 192 193 for (num = smp_cpus - 1; num >= 0; num--) { 194 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 195 char *map_path; 196 197 if (ms->smp.threads > 1) { 198 map_path = g_strdup_printf( 199 "/cpus/cpu-map/socket%d/core%d/thread%d", 200 num / (ms->smp.cores * ms->smp.threads), 201 (num / ms->smp.threads) % ms->smp.cores, 202 num % ms->smp.threads); 203 } else { 204 map_path = g_strdup_printf( 205 "/cpus/cpu-map/socket%d/core%d", 206 num / ms->smp.cores, 207 num % ms->smp.cores); 208 } 209 qemu_fdt_add_path(ms->fdt, map_path); 210 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 211 212 g_free(map_path); 213 g_free(cpu_path); 214 } 215 } 216 217 static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) 218 { 219 char *nodename; 220 hwaddr base = VIRT_FWCFG_BASE; 221 const MachineState *ms = MACHINE(lams); 222 223 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 224 qemu_fdt_add_subnode(ms->fdt, nodename); 225 qemu_fdt_setprop_string(ms->fdt, nodename, 226 "compatible", "qemu,fw-cfg-mmio"); 227 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 228 2, base, 2, 0x18); 229 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 230 g_free(nodename); 231 } 232 233 static void fdt_add_pcie_node(const LoongArchMachineState *lams) 234 { 235 char *nodename; 236 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 237 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 238 hwaddr base_pio = VIRT_PCI_IO_BASE; 239 hwaddr size_pio = VIRT_PCI_IO_SIZE; 240 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 241 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 242 hwaddr base = base_pcie; 243 244 const MachineState *ms = MACHINE(lams); 245 246 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 247 qemu_fdt_add_subnode(ms->fdt, nodename); 248 qemu_fdt_setprop_string(ms->fdt, nodename, 249 "compatible", "pci-host-ecam-generic"); 250 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 251 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 252 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 253 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 254 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 255 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 256 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 257 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 258 2, base_pcie, 2, size_pcie); 259 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 260 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 261 2, base_pio, 2, size_pio, 262 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 263 2, base_mmio, 2, size_mmio); 264 g_free(nodename); 265 } 266 267 static void fdt_add_irqchip_node(LoongArchMachineState *lams) 268 { 269 MachineState *ms = MACHINE(lams); 270 char *nodename; 271 uint32_t irqchip_phandle; 272 273 irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt); 274 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle); 275 276 nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE); 277 qemu_fdt_add_subnode(ms->fdt, nodename); 278 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 279 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 280 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 281 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 282 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 283 284 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 285 "loongarch,ls7a"); 286 287 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 288 2, VIRT_IOAPIC_REG_BASE, 289 2, PCH_PIC_ROUTE_ENTRY_OFFSET); 290 291 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle); 292 g_free(nodename); 293 } 294 295 static void fdt_add_memory_node(MachineState *ms, 296 uint64_t base, uint64_t size, int node_id) 297 { 298 char *nodename = g_strdup_printf("/memory@%" PRIx64, base); 299 300 qemu_fdt_add_subnode(ms->fdt, nodename); 301 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 302 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 303 304 if (ms->numa_state && ms->numa_state->num_nodes) { 305 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); 306 } 307 308 g_free(nodename); 309 } 310 311 #define PM_BASE 0x10080000 312 #define PM_SIZE 0x100 313 #define PM_CTRL 0x10 314 315 static void virt_build_smbios(LoongArchMachineState *lams) 316 { 317 MachineState *ms = MACHINE(lams); 318 MachineClass *mc = MACHINE_GET_CLASS(lams); 319 uint8_t *smbios_tables, *smbios_anchor; 320 size_t smbios_tables_len, smbios_anchor_len; 321 const char *product = "QEMU Virtual Machine"; 322 323 if (!lams->fw_cfg) { 324 return; 325 } 326 327 smbios_set_defaults("QEMU", product, mc->name, false, 328 true, SMBIOS_ENTRY_POINT_TYPE_64); 329 330 smbios_get_tables(ms, NULL, 0, &smbios_tables, &smbios_tables_len, 331 &smbios_anchor, &smbios_anchor_len, &error_fatal); 332 333 if (smbios_anchor) { 334 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", 335 smbios_tables, smbios_tables_len); 336 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", 337 smbios_anchor, smbios_anchor_len); 338 } 339 } 340 341 static void virt_machine_done(Notifier *notifier, void *data) 342 { 343 LoongArchMachineState *lams = container_of(notifier, 344 LoongArchMachineState, machine_done); 345 virt_build_smbios(lams); 346 loongarch_acpi_setup(lams); 347 } 348 349 static void virt_powerdown_req(Notifier *notifier, void *opaque) 350 { 351 LoongArchMachineState *s = container_of(notifier, 352 LoongArchMachineState, powerdown_notifier); 353 354 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 355 } 356 357 struct memmap_entry { 358 uint64_t address; 359 uint64_t length; 360 uint32_t type; 361 uint32_t reserved; 362 }; 363 364 static struct memmap_entry *memmap_table; 365 static unsigned memmap_entries; 366 367 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 368 { 369 /* Ensure there are no duplicate entries. */ 370 for (unsigned i = 0; i < memmap_entries; i++) { 371 assert(memmap_table[i].address != address); 372 } 373 374 memmap_table = g_renew(struct memmap_entry, memmap_table, 375 memmap_entries + 1); 376 memmap_table[memmap_entries].address = cpu_to_le64(address); 377 memmap_table[memmap_entries].length = cpu_to_le64(length); 378 memmap_table[memmap_entries].type = cpu_to_le32(type); 379 memmap_table[memmap_entries].reserved = 0; 380 memmap_entries++; 381 } 382 383 /* 384 * This is a placeholder for missing ACPI, 385 * and will eventually be replaced. 386 */ 387 static uint64_t loongarch_virt_pm_read(void *opaque, hwaddr addr, unsigned size) 388 { 389 return 0; 390 } 391 392 static void loongarch_virt_pm_write(void *opaque, hwaddr addr, 393 uint64_t val, unsigned size) 394 { 395 if (addr != PM_CTRL) { 396 return; 397 } 398 399 switch (val) { 400 case 0x00: 401 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 402 return; 403 case 0xff: 404 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 405 return; 406 default: 407 return; 408 } 409 } 410 411 static const MemoryRegionOps loongarch_virt_pm_ops = { 412 .read = loongarch_virt_pm_read, 413 .write = loongarch_virt_pm_write, 414 .endianness = DEVICE_NATIVE_ENDIAN, 415 .valid = { 416 .min_access_size = 1, 417 .max_access_size = 1 418 } 419 }; 420 421 static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr) 422 { 423 return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS); 424 } 425 426 static int64_t load_kernel_info(const struct loaderparams *loaderparams) 427 { 428 uint64_t kernel_entry, kernel_low, kernel_high; 429 ssize_t kernel_size; 430 431 kernel_size = load_elf(loaderparams->kernel_filename, NULL, 432 cpu_loongarch_virt_to_phys, NULL, 433 &kernel_entry, &kernel_low, 434 &kernel_high, NULL, 0, 435 EM_LOONGARCH, 1, 0); 436 437 if (kernel_size < 0) { 438 error_report("could not load kernel '%s': %s", 439 loaderparams->kernel_filename, 440 load_elf_strerror(kernel_size)); 441 exit(1); 442 } 443 return kernel_entry; 444 } 445 446 static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams) 447 { 448 DeviceState *dev; 449 MachineState *ms = MACHINE(lams); 450 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 451 452 if (ms->ram_slots) { 453 event |= ACPI_GED_MEM_HOTPLUG_EVT; 454 } 455 dev = qdev_new(TYPE_ACPI_GED); 456 qdev_prop_set_uint32(dev, "ged-event", event); 457 458 /* ged event */ 459 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 460 /* memory hotplug */ 461 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 462 /* ged regs used for reset and power down */ 463 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 464 465 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 466 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 467 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 468 return dev; 469 } 470 471 static DeviceState *create_platform_bus(DeviceState *pch_pic) 472 { 473 DeviceState *dev; 474 SysBusDevice *sysbus; 475 int i, irq; 476 MemoryRegion *sysmem = get_system_memory(); 477 478 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 479 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 480 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 481 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 482 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 483 484 sysbus = SYS_BUS_DEVICE(dev); 485 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 486 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 487 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 488 } 489 490 memory_region_add_subregion(sysmem, 491 VIRT_PLATFORM_BUS_BASEADDRESS, 492 sysbus_mmio_get_region(sysbus, 0)); 493 return dev; 494 } 495 496 static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams) 497 { 498 MachineClass *mc = MACHINE_GET_CLASS(lams); 499 DeviceState *gpex_dev; 500 SysBusDevice *d; 501 PCIBus *pci_bus; 502 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 503 MemoryRegion *mmio_alias, *mmio_reg, *pm_mem; 504 int i; 505 506 gpex_dev = qdev_new(TYPE_GPEX_HOST); 507 d = SYS_BUS_DEVICE(gpex_dev); 508 sysbus_realize_and_unref(d, &error_fatal); 509 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 510 lams->pci_bus = pci_bus; 511 512 /* Map only part size_ecam bytes of ECAM space */ 513 ecam_alias = g_new0(MemoryRegion, 1); 514 ecam_reg = sysbus_mmio_get_region(d, 0); 515 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 516 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 517 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 518 ecam_alias); 519 520 /* Map PCI mem space */ 521 mmio_alias = g_new0(MemoryRegion, 1); 522 mmio_reg = sysbus_mmio_get_region(d, 1); 523 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 524 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 525 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 526 mmio_alias); 527 528 /* Map PCI IO port space. */ 529 pio_alias = g_new0(MemoryRegion, 1); 530 pio_reg = sysbus_mmio_get_region(d, 2); 531 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 532 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 533 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 534 pio_alias); 535 536 for (i = 0; i < GPEX_NUM_IRQS; i++) { 537 sysbus_connect_irq(d, i, 538 qdev_get_gpio_in(pch_pic, 16 + i)); 539 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 540 } 541 542 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 543 qdev_get_gpio_in(pch_pic, 544 VIRT_UART_IRQ - VIRT_GSI_BASE), 545 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 546 fdt_add_uart_node(lams); 547 548 /* Network init */ 549 for (i = 0; i < nb_nics; i++) { 550 pci_nic_init_nofail(&nd_table[i], pci_bus, mc->default_nic, NULL); 551 } 552 553 /* 554 * There are some invalid guest memory access. 555 * Create some unimplemented devices to emulate this. 556 */ 557 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 558 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 559 qdev_get_gpio_in(pch_pic, 560 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 561 fdt_add_rtc_node(lams); 562 563 pm_mem = g_new(MemoryRegion, 1); 564 memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops, 565 NULL, "loongarch_virt_pm", PM_SIZE); 566 memory_region_add_subregion(get_system_memory(), PM_BASE, pm_mem); 567 /* acpi ged */ 568 lams->acpi_ged = create_acpi_ged(pch_pic, lams); 569 /* platform bus */ 570 lams->platform_bus_dev = create_platform_bus(pch_pic); 571 } 572 573 static void loongarch_irq_init(LoongArchMachineState *lams) 574 { 575 MachineState *ms = MACHINE(lams); 576 DeviceState *pch_pic, *pch_msi, *cpudev; 577 DeviceState *ipi, *extioi; 578 SysBusDevice *d; 579 LoongArchCPU *lacpu; 580 CPULoongArchState *env; 581 CPUState *cpu_state; 582 int cpu, pin, i, start, num; 583 584 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 585 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 586 587 /* 588 * The connection of interrupts: 589 * +-----+ +---------+ +-------+ 590 * | IPI |--> | CPUINTC | <-- | Timer | 591 * +-----+ +---------+ +-------+ 592 * ^ 593 * | 594 * +---------+ 595 * | EIOINTC | 596 * +---------+ 597 * ^ ^ 598 * | | 599 * +---------+ +---------+ 600 * | PCH-PIC | | PCH-MSI | 601 * +---------+ +---------+ 602 * ^ ^ ^ 603 * | | | 604 * +--------+ +---------+ +---------+ 605 * | UARTs | | Devices | | Devices | 606 * +--------+ +---------+ +---------+ 607 */ 608 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 609 cpu_state = qemu_get_cpu(cpu); 610 cpudev = DEVICE(cpu_state); 611 lacpu = LOONGARCH_CPU(cpu_state); 612 env = &(lacpu->env); 613 614 ipi = qdev_new(TYPE_LOONGARCH_IPI); 615 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 616 617 /* connect ipi irq to cpu irq */ 618 qdev_connect_gpio_out(ipi, 0, qdev_get_gpio_in(cpudev, IRQ_IPI)); 619 /* IPI iocsr memory region */ 620 memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX, 621 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 622 0)); 623 memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR, 624 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 625 1)); 626 /* 627 * extioi iocsr memory region 628 * only one extioi is added on loongarch virt machine 629 * external device interrupt can only be routed to cpu 0-3 630 */ 631 if (cpu < EXTIOI_CPUS) 632 memory_region_add_subregion(&env->system_iocsr, APIC_BASE, 633 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 634 cpu)); 635 env->ipistate = ipi; 636 } 637 638 /* 639 * connect ext irq to the cpu irq 640 * cpu_pin[9:2] <= intc_pin[7:0] 641 */ 642 for (cpu = 0; cpu < MIN(ms->smp.cpus, EXTIOI_CPUS); cpu++) { 643 cpudev = DEVICE(qemu_get_cpu(cpu)); 644 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 645 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 646 qdev_get_gpio_in(cpudev, pin + 2)); 647 } 648 } 649 650 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 651 num = VIRT_PCH_PIC_IRQ_NUM; 652 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 653 d = SYS_BUS_DEVICE(pch_pic); 654 sysbus_realize_and_unref(d, &error_fatal); 655 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 656 sysbus_mmio_get_region(d, 0)); 657 memory_region_add_subregion(get_system_memory(), 658 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 659 sysbus_mmio_get_region(d, 1)); 660 memory_region_add_subregion(get_system_memory(), 661 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 662 sysbus_mmio_get_region(d, 2)); 663 664 /* Connect pch_pic irqs to extioi */ 665 for (i = 0; i < num; i++) { 666 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 667 } 668 669 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 670 start = num; 671 num = EXTIOI_IRQS - start; 672 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 673 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 674 d = SYS_BUS_DEVICE(pch_msi); 675 sysbus_realize_and_unref(d, &error_fatal); 676 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 677 for (i = 0; i < num; i++) { 678 /* Connect pch_msi irqs to extioi */ 679 qdev_connect_gpio_out(DEVICE(d), i, 680 qdev_get_gpio_in(extioi, i + start)); 681 } 682 683 loongarch_devices_init(pch_pic, lams); 684 } 685 686 static void loongarch_firmware_init(LoongArchMachineState *lams) 687 { 688 char *filename = MACHINE(lams)->firmware; 689 char *bios_name = NULL; 690 int bios_size; 691 692 lams->bios_loaded = false; 693 694 virt_flash_map(lams, get_system_memory()); 695 696 if (filename) { 697 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 698 if (!bios_name) { 699 error_report("Could not find ROM image '%s'", filename); 700 exit(1); 701 } 702 703 bios_size = load_image_targphys(bios_name, VIRT_BIOS_BASE, VIRT_BIOS_SIZE); 704 if (bios_size < 0) { 705 error_report("Could not load ROM image '%s'", bios_name); 706 exit(1); 707 } 708 709 g_free(bios_name); 710 711 memory_region_init_ram(&lams->bios, NULL, "loongarch.bios", 712 VIRT_BIOS_SIZE, &error_fatal); 713 memory_region_set_readonly(&lams->bios, true); 714 memory_region_add_subregion(get_system_memory(), VIRT_BIOS_BASE, &lams->bios); 715 lams->bios_loaded = true; 716 } 717 718 } 719 720 static void reset_load_elf(void *opaque) 721 { 722 LoongArchCPU *cpu = opaque; 723 CPULoongArchState *env = &cpu->env; 724 725 cpu_reset(CPU(cpu)); 726 if (env->load_elf) { 727 cpu_set_pc(CPU(cpu), env->elf_address); 728 } 729 } 730 731 static void fw_cfg_add_kernel_info(const struct loaderparams *loaderparams, 732 FWCfgState *fw_cfg) 733 { 734 /* 735 * Expose the kernel, the command line, and the initrd in fw_cfg. 736 * We don't process them here at all, it's all left to the 737 * firmware. 738 */ 739 load_image_to_fw_cfg(fw_cfg, 740 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 741 loaderparams->kernel_filename, 742 false); 743 744 if (loaderparams->initrd_filename) { 745 load_image_to_fw_cfg(fw_cfg, 746 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 747 loaderparams->initrd_filename, false); 748 } 749 750 if (loaderparams->kernel_cmdline) { 751 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 752 strlen(loaderparams->kernel_cmdline) + 1); 753 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 754 loaderparams->kernel_cmdline); 755 } 756 } 757 758 static void loongarch_firmware_boot(LoongArchMachineState *lams, 759 const struct loaderparams *loaderparams) 760 { 761 fw_cfg_add_kernel_info(loaderparams, lams->fw_cfg); 762 } 763 764 static void loongarch_direct_kernel_boot(LoongArchMachineState *lams, 765 const struct loaderparams *loaderparams) 766 { 767 MachineState *machine = MACHINE(lams); 768 int64_t kernel_addr = 0; 769 LoongArchCPU *lacpu; 770 int i; 771 772 kernel_addr = load_kernel_info(loaderparams); 773 if (!machine->firmware) { 774 for (i = 0; i < machine->smp.cpus; i++) { 775 lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); 776 lacpu->env.load_elf = true; 777 lacpu->env.elf_address = kernel_addr; 778 } 779 } 780 } 781 782 static void loongarch_init(MachineState *machine) 783 { 784 LoongArchCPU *lacpu; 785 const char *cpu_model = machine->cpu_type; 786 ram_addr_t offset = 0; 787 ram_addr_t ram_size = machine->ram_size; 788 uint64_t highram_size = 0, phyAddr = 0; 789 MemoryRegion *address_space_mem = get_system_memory(); 790 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 791 int nb_numa_nodes = machine->numa_state->num_nodes; 792 NodeInfo *numa_info = machine->numa_state->nodes; 793 int i; 794 hwaddr fdt_base; 795 const CPUArchIdList *possible_cpus; 796 MachineClass *mc = MACHINE_GET_CLASS(machine); 797 CPUState *cpu; 798 char *ramName = NULL; 799 struct loaderparams loaderparams = { }; 800 801 if (!cpu_model) { 802 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 803 } 804 805 if (ram_size < 1 * GiB) { 806 error_report("ram_size must be greater than 1G."); 807 exit(1); 808 } 809 create_fdt(lams); 810 /* Init CPUs */ 811 812 possible_cpus = mc->possible_cpu_arch_ids(machine); 813 for (i = 0; i < possible_cpus->len; i++) { 814 cpu = cpu_create(machine->cpu_type); 815 cpu->cpu_index = i; 816 machine->possible_cpus->cpus[i].cpu = OBJECT(cpu); 817 lacpu = LOONGARCH_CPU(cpu); 818 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; 819 } 820 fdt_add_cpu_nodes(lams); 821 822 /* Node0 memory */ 823 memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1); 824 fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0); 825 memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram", 826 machine->ram, offset, VIRT_LOWMEM_SIZE); 827 memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem); 828 829 offset += VIRT_LOWMEM_SIZE; 830 if (nb_numa_nodes > 0) { 831 assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE); 832 highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE; 833 } else { 834 highram_size = ram_size - VIRT_LOWMEM_SIZE; 835 } 836 phyAddr = VIRT_HIGHMEM_BASE; 837 memmap_add_entry(phyAddr, highram_size, 1); 838 fdt_add_memory_node(machine, phyAddr, highram_size, 0); 839 memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram", 840 machine->ram, offset, highram_size); 841 memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem); 842 843 /* Node1 - Nodemax memory */ 844 offset += highram_size; 845 phyAddr += highram_size; 846 847 for (i = 1; i < nb_numa_nodes; i++) { 848 MemoryRegion *nodemem = g_new(MemoryRegion, 1); 849 ramName = g_strdup_printf("loongarch.node%d.ram", i); 850 memory_region_init_alias(nodemem, NULL, ramName, machine->ram, 851 offset, numa_info[i].node_mem); 852 memory_region_add_subregion(address_space_mem, phyAddr, nodemem); 853 memmap_add_entry(phyAddr, numa_info[i].node_mem, 1); 854 fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i); 855 offset += numa_info[i].node_mem; 856 phyAddr += numa_info[i].node_mem; 857 } 858 859 /* initialize device memory address space */ 860 if (machine->ram_size < machine->maxram_size) { 861 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 862 hwaddr device_mem_base; 863 864 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 865 error_report("unsupported amount of memory slots: %"PRIu64, 866 machine->ram_slots); 867 exit(EXIT_FAILURE); 868 } 869 870 if (QEMU_ALIGN_UP(machine->maxram_size, 871 TARGET_PAGE_SIZE) != machine->maxram_size) { 872 error_report("maximum memory size must by aligned to multiple of " 873 "%d bytes", TARGET_PAGE_SIZE); 874 exit(EXIT_FAILURE); 875 } 876 /* device memory base is the top of high memory address. */ 877 device_mem_base = ROUND_UP(VIRT_HIGHMEM_BASE + highram_size, 1 * GiB); 878 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 879 } 880 881 /* Add isa io region */ 882 memory_region_init_alias(&lams->isa_io, NULL, "isa-io", 883 get_system_io(), 0, VIRT_ISA_IO_SIZE); 884 memory_region_add_subregion(address_space_mem, VIRT_ISA_IO_BASE, 885 &lams->isa_io); 886 /* load the BIOS image. */ 887 loongarch_firmware_init(lams); 888 889 /* fw_cfg init */ 890 lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine); 891 rom_set_fw(lams->fw_cfg); 892 if (lams->fw_cfg != NULL) { 893 fw_cfg_add_file(lams->fw_cfg, "etc/memmap", 894 memmap_table, 895 sizeof(struct memmap_entry) * (memmap_entries)); 896 } 897 fdt_add_fw_cfg_node(lams); 898 loaderparams.ram_size = ram_size; 899 loaderparams.kernel_filename = machine->kernel_filename; 900 loaderparams.kernel_cmdline = machine->kernel_cmdline; 901 loaderparams.initrd_filename = machine->initrd_filename; 902 /* load the kernel. */ 903 if (loaderparams.kernel_filename) { 904 if (lams->bios_loaded) { 905 loongarch_firmware_boot(lams, &loaderparams); 906 } else { 907 loongarch_direct_kernel_boot(lams, &loaderparams); 908 } 909 } 910 fdt_add_flash_node(lams); 911 /* register reset function */ 912 for (i = 0; i < machine->smp.cpus; i++) { 913 lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); 914 qemu_register_reset(reset_load_elf, lacpu); 915 } 916 /* Initialize the IO interrupt subsystem */ 917 loongarch_irq_init(lams); 918 fdt_add_irqchip_node(lams); 919 platform_bus_add_all_fdt_nodes(machine->fdt, "/intc", 920 VIRT_PLATFORM_BUS_BASEADDRESS, 921 VIRT_PLATFORM_BUS_SIZE, 922 VIRT_PLATFORM_BUS_IRQ); 923 lams->machine_done.notify = virt_machine_done; 924 qemu_add_machine_init_done_notifier(&lams->machine_done); 925 /* connect powerdown request */ 926 lams->powerdown_notifier.notify = virt_powerdown_req; 927 qemu_register_powerdown_notifier(&lams->powerdown_notifier); 928 929 fdt_add_pcie_node(lams); 930 /* 931 * Since lowmem region starts from 0 and Linux kernel legacy start address 932 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer 933 * access. FDT size limit with 1 MiB. 934 * Put the FDT into the memory map as a ROM image: this will ensure 935 * the FDT is copied again upon reset, even if addr points into RAM. 936 */ 937 fdt_base = 1 * MiB; 938 qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size); 939 rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base); 940 } 941 942 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) 943 { 944 if (lams->acpi == ON_OFF_AUTO_OFF) { 945 return false; 946 } 947 return true; 948 } 949 950 static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, 951 void *opaque, Error **errp) 952 { 953 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 954 OnOffAuto acpi = lams->acpi; 955 956 visit_type_OnOffAuto(v, name, &acpi, errp); 957 } 958 959 static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, 960 void *opaque, Error **errp) 961 { 962 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 963 964 visit_type_OnOffAuto(v, name, &lams->acpi, errp); 965 } 966 967 static void loongarch_machine_initfn(Object *obj) 968 { 969 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 970 971 lams->acpi = ON_OFF_AUTO_AUTO; 972 lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 973 lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 974 virt_flash_create(lams); 975 } 976 977 static bool memhp_type_supported(DeviceState *dev) 978 { 979 /* we only support pc dimm now */ 980 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 981 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 982 } 983 984 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 985 Error **errp) 986 { 987 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 988 } 989 990 static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev, 991 DeviceState *dev, Error **errp) 992 { 993 if (memhp_type_supported(dev)) { 994 virt_mem_pre_plug(hotplug_dev, dev, errp); 995 } 996 } 997 998 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 999 DeviceState *dev, Error **errp) 1000 { 1001 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1002 1003 /* the acpi ged is always exist */ 1004 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lams->acpi_ged), dev, 1005 errp); 1006 } 1007 1008 static void virt_machine_device_unplug_request(HotplugHandler *hotplug_dev, 1009 DeviceState *dev, Error **errp) 1010 { 1011 if (memhp_type_supported(dev)) { 1012 virt_mem_unplug_request(hotplug_dev, dev, errp); 1013 } 1014 } 1015 1016 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 1017 DeviceState *dev, Error **errp) 1018 { 1019 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1020 1021 hotplug_handler_unplug(HOTPLUG_HANDLER(lams->acpi_ged), dev, errp); 1022 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lams)); 1023 qdev_unrealize(dev); 1024 } 1025 1026 static void virt_machine_device_unplug(HotplugHandler *hotplug_dev, 1027 DeviceState *dev, Error **errp) 1028 { 1029 if (memhp_type_supported(dev)) { 1030 virt_mem_unplug(hotplug_dev, dev, errp); 1031 } 1032 } 1033 1034 static void virt_mem_plug(HotplugHandler *hotplug_dev, 1035 DeviceState *dev, Error **errp) 1036 { 1037 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1038 1039 pc_dimm_plug(PC_DIMM(dev), MACHINE(lams)); 1040 hotplug_handler_plug(HOTPLUG_HANDLER(lams->acpi_ged), 1041 dev, &error_abort); 1042 } 1043 1044 static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1045 DeviceState *dev, Error **errp) 1046 { 1047 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1048 MachineClass *mc = MACHINE_GET_CLASS(lams); 1049 1050 if (device_is_dynamic_sysbus(mc, dev)) { 1051 if (lams->platform_bus_dev) { 1052 platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev), 1053 SYS_BUS_DEVICE(dev)); 1054 } 1055 } else if (memhp_type_supported(dev)) { 1056 virt_mem_plug(hotplug_dev, dev, errp); 1057 } 1058 } 1059 1060 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1061 DeviceState *dev) 1062 { 1063 MachineClass *mc = MACHINE_GET_CLASS(machine); 1064 1065 if (device_is_dynamic_sysbus(mc, dev) || 1066 memhp_type_supported(dev)) { 1067 return HOTPLUG_HANDLER(machine); 1068 } 1069 return NULL; 1070 } 1071 1072 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1073 { 1074 int n; 1075 unsigned int max_cpus = ms->smp.max_cpus; 1076 1077 if (ms->possible_cpus) { 1078 assert(ms->possible_cpus->len == max_cpus); 1079 return ms->possible_cpus; 1080 } 1081 1082 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1083 sizeof(CPUArchId) * max_cpus); 1084 ms->possible_cpus->len = max_cpus; 1085 for (n = 0; n < ms->possible_cpus->len; n++) { 1086 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1087 ms->possible_cpus->cpus[n].arch_id = n; 1088 1089 ms->possible_cpus->cpus[n].props.has_socket_id = true; 1090 ms->possible_cpus->cpus[n].props.socket_id = 1091 n / (ms->smp.cores * ms->smp.threads); 1092 ms->possible_cpus->cpus[n].props.has_core_id = true; 1093 ms->possible_cpus->cpus[n].props.core_id = 1094 n / ms->smp.threads % ms->smp.cores; 1095 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1096 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 1097 } 1098 return ms->possible_cpus; 1099 } 1100 1101 static CpuInstanceProperties 1102 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1103 { 1104 MachineClass *mc = MACHINE_GET_CLASS(ms); 1105 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1106 1107 assert(cpu_index < possible_cpus->len); 1108 return possible_cpus->cpus[cpu_index].props; 1109 } 1110 1111 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1112 { 1113 int64_t nidx = 0; 1114 1115 if (ms->numa_state->num_nodes) { 1116 nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes); 1117 if (ms->numa_state->num_nodes <= nidx) { 1118 nidx = ms->numa_state->num_nodes - 1; 1119 } 1120 } 1121 return nidx; 1122 } 1123 1124 static void loongarch_class_init(ObjectClass *oc, void *data) 1125 { 1126 MachineClass *mc = MACHINE_CLASS(oc); 1127 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1128 1129 mc->desc = "Loongson-3A5000 LS7A1000 machine"; 1130 mc->init = loongarch_init; 1131 mc->default_ram_size = 1 * GiB; 1132 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 1133 mc->default_ram_id = "loongarch.ram"; 1134 mc->max_cpus = LOONGARCH_MAX_CPUS; 1135 mc->is_default = 1; 1136 mc->default_kernel_irqchip_split = false; 1137 mc->block_default_type = IF_VIRTIO; 1138 mc->default_boot_order = "c"; 1139 mc->no_cdrom = 1; 1140 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1141 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1142 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1143 mc->numa_mem_supported = true; 1144 mc->auto_enable_numa_with_memhp = true; 1145 mc->auto_enable_numa_with_memdev = true; 1146 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1147 mc->default_nic = "virtio-net-pci"; 1148 hc->plug = loongarch_machine_device_plug_cb; 1149 hc->pre_plug = virt_machine_device_pre_plug; 1150 hc->unplug_request = virt_machine_device_unplug_request; 1151 hc->unplug = virt_machine_device_unplug; 1152 1153 object_class_property_add(oc, "acpi", "OnOffAuto", 1154 loongarch_get_acpi, loongarch_set_acpi, 1155 NULL, NULL); 1156 object_class_property_set_description(oc, "acpi", 1157 "Enable ACPI"); 1158 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1159 #ifdef CONFIG_TPM 1160 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1161 #endif 1162 } 1163 1164 static const TypeInfo loongarch_machine_types[] = { 1165 { 1166 .name = TYPE_LOONGARCH_MACHINE, 1167 .parent = TYPE_MACHINE, 1168 .instance_size = sizeof(LoongArchMachineState), 1169 .class_init = loongarch_class_init, 1170 .instance_init = loongarch_machine_initfn, 1171 .interfaces = (InterfaceInfo[]) { 1172 { TYPE_HOTPLUG_HANDLER }, 1173 { } 1174 }, 1175 } 1176 }; 1177 1178 DEFINE_TYPES(loongarch_machine_types) 1179