1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/sysemu.h" 14 #include "sysemu/qtest.h" 15 #include "sysemu/runstate.h" 16 #include "sysemu/reset.h" 17 #include "sysemu/rtc.h" 18 #include "hw/loongarch/virt.h" 19 #include "exec/address-spaces.h" 20 #include "hw/irq.h" 21 #include "net/net.h" 22 #include "hw/loader.h" 23 #include "elf.h" 24 #include "hw/intc/loongarch_ipi.h" 25 #include "hw/intc/loongarch_extioi.h" 26 #include "hw/intc/loongarch_pch_pic.h" 27 #include "hw/intc/loongarch_pch_msi.h" 28 #include "hw/pci-host/ls7a.h" 29 #include "hw/pci-host/gpex.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/loongarch/fw_cfg.h" 32 #include "target/loongarch/cpu.h" 33 #include "hw/firmware/smbios.h" 34 #include "hw/acpi/aml-build.h" 35 #include "qapi/qapi-visit-common.h" 36 #include "hw/acpi/generic_event_device.h" 37 #include "hw/mem/nvdimm.h" 38 #include "sysemu/device_tree.h" 39 #include <libfdt.h> 40 #include "hw/core/sysbus-fdt.h" 41 #include "hw/platform-bus.h" 42 #include "hw/display/ramfb.h" 43 #include "hw/mem/pc-dimm.h" 44 #include "sysemu/tpm.h" 45 #include "sysemu/block-backend.h" 46 #include "hw/block/flash.h" 47 #include "qemu/error-report.h" 48 49 static PFlashCFI01 *virt_flash_create1(LoongArchMachineState *lams, 50 const char *name, 51 const char *alias_prop_name) 52 { 53 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 54 55 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 56 qdev_prop_set_uint8(dev, "width", 4); 57 qdev_prop_set_uint8(dev, "device-width", 2); 58 qdev_prop_set_bit(dev, "big-endian", false); 59 qdev_prop_set_uint16(dev, "id0", 0x89); 60 qdev_prop_set_uint16(dev, "id1", 0x18); 61 qdev_prop_set_uint16(dev, "id2", 0x00); 62 qdev_prop_set_uint16(dev, "id3", 0x00); 63 qdev_prop_set_string(dev, "name", name); 64 object_property_add_child(OBJECT(lams), name, OBJECT(dev)); 65 object_property_add_alias(OBJECT(lams), alias_prop_name, 66 OBJECT(dev), "drive"); 67 return PFLASH_CFI01(dev); 68 } 69 70 static void virt_flash_create(LoongArchMachineState *lams) 71 { 72 lams->flash[0] = virt_flash_create1(lams, "virt.flash0", "pflash0"); 73 lams->flash[1] = virt_flash_create1(lams, "virt.flash1", "pflash1"); 74 } 75 76 static void virt_flash_map1(PFlashCFI01 *flash, 77 hwaddr base, hwaddr size, 78 MemoryRegion *sysmem) 79 { 80 DeviceState *dev = DEVICE(flash); 81 BlockBackend *blk; 82 hwaddr real_size = size; 83 84 blk = pflash_cfi01_get_blk(flash); 85 if (blk) { 86 real_size = blk_getlength(blk); 87 assert(real_size && real_size <= size); 88 } 89 90 assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE)); 91 assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 92 93 qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE); 94 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 95 memory_region_add_subregion(sysmem, base, 96 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 97 } 98 99 static void virt_flash_map(LoongArchMachineState *lams, 100 MemoryRegion *sysmem) 101 { 102 PFlashCFI01 *flash0 = lams->flash[0]; 103 PFlashCFI01 *flash1 = lams->flash[1]; 104 105 virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem); 106 virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem); 107 } 108 109 static void fdt_add_cpuic_node(LoongArchMachineState *lams, 110 uint32_t *cpuintc_phandle) 111 { 112 MachineState *ms = MACHINE(lams); 113 char *nodename; 114 115 *cpuintc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 116 nodename = g_strdup_printf("/cpuic"); 117 qemu_fdt_add_subnode(ms->fdt, nodename); 118 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *cpuintc_phandle); 119 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 120 "loongson,cpu-interrupt-controller"); 121 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 122 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 123 g_free(nodename); 124 } 125 126 static void fdt_add_eiointc_node(LoongArchMachineState *lams, 127 uint32_t *cpuintc_phandle, 128 uint32_t *eiointc_phandle) 129 { 130 MachineState *ms = MACHINE(lams); 131 char *nodename; 132 hwaddr extioi_base = APIC_BASE; 133 hwaddr extioi_size = EXTIOI_SIZE; 134 135 *eiointc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 136 nodename = g_strdup_printf("/eiointc@%" PRIx64, extioi_base); 137 qemu_fdt_add_subnode(ms->fdt, nodename); 138 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *eiointc_phandle); 139 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 140 "loongson,ls2k2000-eiointc"); 141 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 142 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 143 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 144 *cpuintc_phandle); 145 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", 3); 146 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, 147 extioi_base, 0x0, extioi_size); 148 g_free(nodename); 149 } 150 151 static void fdt_add_pch_pic_node(LoongArchMachineState *lams, 152 uint32_t *eiointc_phandle, 153 uint32_t *pch_pic_phandle) 154 { 155 MachineState *ms = MACHINE(lams); 156 char *nodename; 157 hwaddr pch_pic_base = VIRT_PCH_REG_BASE; 158 hwaddr pch_pic_size = VIRT_PCH_REG_SIZE; 159 160 *pch_pic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 161 nodename = g_strdup_printf("/platic@%" PRIx64, pch_pic_base); 162 qemu_fdt_add_subnode(ms->fdt, nodename); 163 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_pic_phandle); 164 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 165 "loongson,pch-pic-1.0"); 166 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, 167 pch_pic_base, 0, pch_pic_size); 168 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 169 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 2); 170 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 171 *eiointc_phandle); 172 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,pic-base-vec", 0); 173 g_free(nodename); 174 } 175 176 static void fdt_add_flash_node(LoongArchMachineState *lams) 177 { 178 MachineState *ms = MACHINE(lams); 179 char *nodename; 180 MemoryRegion *flash_mem; 181 182 hwaddr flash0_base; 183 hwaddr flash0_size; 184 185 hwaddr flash1_base; 186 hwaddr flash1_size; 187 188 flash_mem = pflash_cfi01_get_memory(lams->flash[0]); 189 flash0_base = flash_mem->addr; 190 flash0_size = memory_region_size(flash_mem); 191 192 flash_mem = pflash_cfi01_get_memory(lams->flash[1]); 193 flash1_base = flash_mem->addr; 194 flash1_size = memory_region_size(flash_mem); 195 196 nodename = g_strdup_printf("/flash@%" PRIx64, flash0_base); 197 qemu_fdt_add_subnode(ms->fdt, nodename); 198 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 199 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 200 2, flash0_base, 2, flash0_size, 201 2, flash1_base, 2, flash1_size); 202 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 203 g_free(nodename); 204 } 205 206 static void fdt_add_rtc_node(LoongArchMachineState *lams) 207 { 208 char *nodename; 209 hwaddr base = VIRT_RTC_REG_BASE; 210 hwaddr size = VIRT_RTC_LEN; 211 MachineState *ms = MACHINE(lams); 212 213 nodename = g_strdup_printf("/rtc@%" PRIx64, base); 214 qemu_fdt_add_subnode(ms->fdt, nodename); 215 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc"); 216 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 217 g_free(nodename); 218 } 219 220 static void fdt_add_uart_node(LoongArchMachineState *lams) 221 { 222 char *nodename; 223 hwaddr base = VIRT_UART_BASE; 224 hwaddr size = VIRT_UART_SIZE; 225 MachineState *ms = MACHINE(lams); 226 227 nodename = g_strdup_printf("/serial@%" PRIx64, base); 228 qemu_fdt_add_subnode(ms->fdt, nodename); 229 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); 230 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); 231 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); 232 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 233 g_free(nodename); 234 } 235 236 static void create_fdt(LoongArchMachineState *lams) 237 { 238 MachineState *ms = MACHINE(lams); 239 240 ms->fdt = create_device_tree(&lams->fdt_size); 241 if (!ms->fdt) { 242 error_report("create_device_tree() failed"); 243 exit(1); 244 } 245 246 /* Header */ 247 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 248 "linux,dummy-loongson3"); 249 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 250 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 251 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 252 } 253 254 static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) 255 { 256 int num; 257 const MachineState *ms = MACHINE(lams); 258 int smp_cpus = ms->smp.cpus; 259 260 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 261 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 262 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 263 264 /* cpu nodes */ 265 for (num = smp_cpus - 1; num >= 0; num--) { 266 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 267 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 268 CPUState *cs = CPU(cpu); 269 270 qemu_fdt_add_subnode(ms->fdt, nodename); 271 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 272 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 273 cpu->dtb_compatible); 274 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 275 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 276 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 277 } 278 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 279 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 280 qemu_fdt_alloc_phandle(ms->fdt)); 281 g_free(nodename); 282 } 283 284 /*cpu map */ 285 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 286 287 for (num = smp_cpus - 1; num >= 0; num--) { 288 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 289 char *map_path; 290 291 if (ms->smp.threads > 1) { 292 map_path = g_strdup_printf( 293 "/cpus/cpu-map/socket%d/core%d/thread%d", 294 num / (ms->smp.cores * ms->smp.threads), 295 (num / ms->smp.threads) % ms->smp.cores, 296 num % ms->smp.threads); 297 } else { 298 map_path = g_strdup_printf( 299 "/cpus/cpu-map/socket%d/core%d", 300 num / ms->smp.cores, 301 num % ms->smp.cores); 302 } 303 qemu_fdt_add_path(ms->fdt, map_path); 304 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 305 306 g_free(map_path); 307 g_free(cpu_path); 308 } 309 } 310 311 static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) 312 { 313 char *nodename; 314 hwaddr base = VIRT_FWCFG_BASE; 315 const MachineState *ms = MACHINE(lams); 316 317 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 318 qemu_fdt_add_subnode(ms->fdt, nodename); 319 qemu_fdt_setprop_string(ms->fdt, nodename, 320 "compatible", "qemu,fw-cfg-mmio"); 321 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 322 2, base, 2, 0x18); 323 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 324 g_free(nodename); 325 } 326 327 static void fdt_add_pcie_node(const LoongArchMachineState *lams) 328 { 329 char *nodename; 330 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 331 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 332 hwaddr base_pio = VIRT_PCI_IO_BASE; 333 hwaddr size_pio = VIRT_PCI_IO_SIZE; 334 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 335 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 336 hwaddr base = base_pcie; 337 338 const MachineState *ms = MACHINE(lams); 339 340 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 341 qemu_fdt_add_subnode(ms->fdt, nodename); 342 qemu_fdt_setprop_string(ms->fdt, nodename, 343 "compatible", "pci-host-ecam-generic"); 344 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 345 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 346 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 347 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 348 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 349 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 350 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 351 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 352 2, base_pcie, 2, size_pcie); 353 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 354 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 355 2, base_pio, 2, size_pio, 356 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 357 2, base_mmio, 2, size_mmio); 358 g_free(nodename); 359 } 360 361 static void fdt_add_irqchip_node(LoongArchMachineState *lams) 362 { 363 MachineState *ms = MACHINE(lams); 364 char *nodename; 365 uint32_t irqchip_phandle; 366 367 irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt); 368 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle); 369 370 nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE); 371 qemu_fdt_add_subnode(ms->fdt, nodename); 372 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 373 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 374 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 375 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 376 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 377 378 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 379 "loongarch,ls7a"); 380 381 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 382 2, VIRT_IOAPIC_REG_BASE, 383 2, PCH_PIC_ROUTE_ENTRY_OFFSET); 384 385 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle); 386 g_free(nodename); 387 } 388 389 static void fdt_add_memory_node(MachineState *ms, 390 uint64_t base, uint64_t size, int node_id) 391 { 392 char *nodename = g_strdup_printf("/memory@%" PRIx64, base); 393 394 qemu_fdt_add_subnode(ms->fdt, nodename); 395 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, 0, size); 396 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 397 398 if (ms->numa_state && ms->numa_state->num_nodes) { 399 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); 400 } 401 402 g_free(nodename); 403 } 404 405 static void virt_build_smbios(LoongArchMachineState *lams) 406 { 407 MachineState *ms = MACHINE(lams); 408 MachineClass *mc = MACHINE_GET_CLASS(lams); 409 uint8_t *smbios_tables, *smbios_anchor; 410 size_t smbios_tables_len, smbios_anchor_len; 411 const char *product = "QEMU Virtual Machine"; 412 413 if (!lams->fw_cfg) { 414 return; 415 } 416 417 smbios_set_defaults("QEMU", product, mc->name, true); 418 419 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 420 NULL, 0, 421 &smbios_tables, &smbios_tables_len, 422 &smbios_anchor, &smbios_anchor_len, &error_fatal); 423 424 if (smbios_anchor) { 425 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", 426 smbios_tables, smbios_tables_len); 427 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", 428 smbios_anchor, smbios_anchor_len); 429 } 430 } 431 432 static void virt_machine_done(Notifier *notifier, void *data) 433 { 434 LoongArchMachineState *lams = container_of(notifier, 435 LoongArchMachineState, machine_done); 436 virt_build_smbios(lams); 437 loongarch_acpi_setup(lams); 438 } 439 440 static void virt_powerdown_req(Notifier *notifier, void *opaque) 441 { 442 LoongArchMachineState *s = container_of(notifier, 443 LoongArchMachineState, powerdown_notifier); 444 445 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 446 } 447 448 struct memmap_entry *memmap_table; 449 unsigned memmap_entries; 450 451 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 452 { 453 /* Ensure there are no duplicate entries. */ 454 for (unsigned i = 0; i < memmap_entries; i++) { 455 assert(memmap_table[i].address != address); 456 } 457 458 memmap_table = g_renew(struct memmap_entry, memmap_table, 459 memmap_entries + 1); 460 memmap_table[memmap_entries].address = cpu_to_le64(address); 461 memmap_table[memmap_entries].length = cpu_to_le64(length); 462 memmap_table[memmap_entries].type = cpu_to_le32(type); 463 memmap_table[memmap_entries].reserved = 0; 464 memmap_entries++; 465 } 466 467 static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams) 468 { 469 DeviceState *dev; 470 MachineState *ms = MACHINE(lams); 471 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 472 473 if (ms->ram_slots) { 474 event |= ACPI_GED_MEM_HOTPLUG_EVT; 475 } 476 dev = qdev_new(TYPE_ACPI_GED); 477 qdev_prop_set_uint32(dev, "ged-event", event); 478 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 479 480 /* ged event */ 481 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 482 /* memory hotplug */ 483 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 484 /* ged regs used for reset and power down */ 485 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 486 487 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 488 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 489 return dev; 490 } 491 492 static DeviceState *create_platform_bus(DeviceState *pch_pic) 493 { 494 DeviceState *dev; 495 SysBusDevice *sysbus; 496 int i, irq; 497 MemoryRegion *sysmem = get_system_memory(); 498 499 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 500 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 501 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 502 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 503 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 504 505 sysbus = SYS_BUS_DEVICE(dev); 506 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 507 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 508 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 509 } 510 511 memory_region_add_subregion(sysmem, 512 VIRT_PLATFORM_BUS_BASEADDRESS, 513 sysbus_mmio_get_region(sysbus, 0)); 514 return dev; 515 } 516 517 static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams) 518 { 519 MachineClass *mc = MACHINE_GET_CLASS(lams); 520 DeviceState *gpex_dev; 521 SysBusDevice *d; 522 PCIBus *pci_bus; 523 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 524 MemoryRegion *mmio_alias, *mmio_reg; 525 int i; 526 527 gpex_dev = qdev_new(TYPE_GPEX_HOST); 528 d = SYS_BUS_DEVICE(gpex_dev); 529 sysbus_realize_and_unref(d, &error_fatal); 530 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 531 lams->pci_bus = pci_bus; 532 533 /* Map only part size_ecam bytes of ECAM space */ 534 ecam_alias = g_new0(MemoryRegion, 1); 535 ecam_reg = sysbus_mmio_get_region(d, 0); 536 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 537 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 538 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 539 ecam_alias); 540 541 /* Map PCI mem space */ 542 mmio_alias = g_new0(MemoryRegion, 1); 543 mmio_reg = sysbus_mmio_get_region(d, 1); 544 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 545 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 546 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 547 mmio_alias); 548 549 /* Map PCI IO port space. */ 550 pio_alias = g_new0(MemoryRegion, 1); 551 pio_reg = sysbus_mmio_get_region(d, 2); 552 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 553 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 554 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 555 pio_alias); 556 557 for (i = 0; i < GPEX_NUM_IRQS; i++) { 558 sysbus_connect_irq(d, i, 559 qdev_get_gpio_in(pch_pic, 16 + i)); 560 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 561 } 562 563 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 564 qdev_get_gpio_in(pch_pic, 565 VIRT_UART_IRQ - VIRT_GSI_BASE), 566 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 567 fdt_add_uart_node(lams); 568 569 /* Network init */ 570 pci_init_nic_devices(pci_bus, mc->default_nic); 571 572 /* 573 * There are some invalid guest memory access. 574 * Create some unimplemented devices to emulate this. 575 */ 576 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 577 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 578 qdev_get_gpio_in(pch_pic, 579 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 580 fdt_add_rtc_node(lams); 581 582 /* acpi ged */ 583 lams->acpi_ged = create_acpi_ged(pch_pic, lams); 584 /* platform bus */ 585 lams->platform_bus_dev = create_platform_bus(pch_pic); 586 } 587 588 static void loongarch_irq_init(LoongArchMachineState *lams) 589 { 590 MachineState *ms = MACHINE(lams); 591 DeviceState *pch_pic, *pch_msi, *cpudev; 592 DeviceState *ipi, *extioi; 593 SysBusDevice *d; 594 LoongArchCPU *lacpu; 595 CPULoongArchState *env; 596 CPUState *cpu_state; 597 int cpu, pin, i, start, num; 598 uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle; 599 600 /* 601 * The connection of interrupts: 602 * +-----+ +---------+ +-------+ 603 * | IPI |--> | CPUINTC | <-- | Timer | 604 * +-----+ +---------+ +-------+ 605 * ^ 606 * | 607 * +---------+ 608 * | EIOINTC | 609 * +---------+ 610 * ^ ^ 611 * | | 612 * +---------+ +---------+ 613 * | PCH-PIC | | PCH-MSI | 614 * +---------+ +---------+ 615 * ^ ^ ^ 616 * | | | 617 * +--------+ +---------+ +---------+ 618 * | UARTs | | Devices | | Devices | 619 * +--------+ +---------+ +---------+ 620 */ 621 622 /* Create IPI device */ 623 ipi = qdev_new(TYPE_LOONGARCH_IPI); 624 qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); 625 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 626 627 /* IPI iocsr memory region */ 628 memory_region_add_subregion(&lams->system_iocsr, SMP_IPI_MAILBOX, 629 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); 630 memory_region_add_subregion(&lams->system_iocsr, MAIL_SEND_ADDR, 631 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); 632 633 /* Add cpu interrupt-controller */ 634 fdt_add_cpuic_node(lams, &cpuintc_phandle); 635 636 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 637 cpu_state = qemu_get_cpu(cpu); 638 cpudev = DEVICE(cpu_state); 639 lacpu = LOONGARCH_CPU(cpu_state); 640 env = &(lacpu->env); 641 env->address_space_iocsr = &lams->as_iocsr; 642 643 /* connect ipi irq to cpu irq */ 644 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); 645 env->ipistate = ipi; 646 } 647 648 /* Create EXTIOI device */ 649 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 650 qdev_prop_set_uint32(extioi, "num-cpu", ms->smp.cpus); 651 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 652 memory_region_add_subregion(&lams->system_iocsr, APIC_BASE, 653 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); 654 655 /* 656 * connect ext irq to the cpu irq 657 * cpu_pin[9:2] <= intc_pin[7:0] 658 */ 659 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 660 cpudev = DEVICE(qemu_get_cpu(cpu)); 661 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 662 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 663 qdev_get_gpio_in(cpudev, pin + 2)); 664 } 665 } 666 667 /* Add Extend I/O Interrupt Controller node */ 668 fdt_add_eiointc_node(lams, &cpuintc_phandle, &eiointc_phandle); 669 670 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 671 num = VIRT_PCH_PIC_IRQ_NUM; 672 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 673 d = SYS_BUS_DEVICE(pch_pic); 674 sysbus_realize_and_unref(d, &error_fatal); 675 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 676 sysbus_mmio_get_region(d, 0)); 677 memory_region_add_subregion(get_system_memory(), 678 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 679 sysbus_mmio_get_region(d, 1)); 680 memory_region_add_subregion(get_system_memory(), 681 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 682 sysbus_mmio_get_region(d, 2)); 683 684 /* Connect pch_pic irqs to extioi */ 685 for (i = 0; i < num; i++) { 686 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 687 } 688 689 /* Add PCH PIC node */ 690 fdt_add_pch_pic_node(lams, &eiointc_phandle, &pch_pic_phandle); 691 692 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 693 start = num; 694 num = EXTIOI_IRQS - start; 695 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 696 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 697 d = SYS_BUS_DEVICE(pch_msi); 698 sysbus_realize_and_unref(d, &error_fatal); 699 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 700 for (i = 0; i < num; i++) { 701 /* Connect pch_msi irqs to extioi */ 702 qdev_connect_gpio_out(DEVICE(d), i, 703 qdev_get_gpio_in(extioi, i + start)); 704 } 705 706 loongarch_devices_init(pch_pic, lams); 707 } 708 709 static void loongarch_firmware_init(LoongArchMachineState *lams) 710 { 711 char *filename = MACHINE(lams)->firmware; 712 char *bios_name = NULL; 713 int bios_size, i; 714 BlockBackend *pflash_blk0; 715 MemoryRegion *mr; 716 717 lams->bios_loaded = false; 718 719 /* Map legacy -drive if=pflash to machine properties */ 720 for (i = 0; i < ARRAY_SIZE(lams->flash); i++) { 721 pflash_cfi01_legacy_drive(lams->flash[i], 722 drive_get(IF_PFLASH, 0, i)); 723 } 724 725 virt_flash_map(lams, get_system_memory()); 726 727 pflash_blk0 = pflash_cfi01_get_blk(lams->flash[0]); 728 729 if (pflash_blk0) { 730 if (filename) { 731 error_report("cannot use both '-bios' and '-drive if=pflash'" 732 "options at once"); 733 exit(1); 734 } 735 lams->bios_loaded = true; 736 return; 737 } 738 739 if (filename) { 740 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 741 if (!bios_name) { 742 error_report("Could not find ROM image '%s'", filename); 743 exit(1); 744 } 745 746 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lams->flash[0]), 0); 747 bios_size = load_image_mr(bios_name, mr); 748 if (bios_size < 0) { 749 error_report("Could not load ROM image '%s'", bios_name); 750 exit(1); 751 } 752 g_free(bios_name); 753 lams->bios_loaded = true; 754 } 755 } 756 757 758 static void loongarch_qemu_write(void *opaque, hwaddr addr, 759 uint64_t val, unsigned size) 760 { 761 } 762 763 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) 764 { 765 switch (addr) { 766 case VERSION_REG: 767 return 0x11ULL; 768 case FEATURE_REG: 769 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 770 1ULL << IOCSRF_CSRIPI; 771 case VENDOR_REG: 772 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 773 case CPUNAME_REG: 774 return 0x303030354133ULL; /* "3A5000" */ 775 case MISC_FUNC_REG: 776 return 1ULL << IOCSRM_EXTIOI_EN; 777 } 778 return 0ULL; 779 } 780 781 static const MemoryRegionOps loongarch_qemu_ops = { 782 .read = loongarch_qemu_read, 783 .write = loongarch_qemu_write, 784 .endianness = DEVICE_LITTLE_ENDIAN, 785 .valid = { 786 .min_access_size = 4, 787 .max_access_size = 8, 788 }, 789 .impl = { 790 .min_access_size = 8, 791 .max_access_size = 8, 792 }, 793 }; 794 795 static void loongarch_init(MachineState *machine) 796 { 797 LoongArchCPU *lacpu; 798 const char *cpu_model = machine->cpu_type; 799 ram_addr_t offset = 0; 800 ram_addr_t ram_size = machine->ram_size; 801 uint64_t highram_size = 0, phyAddr = 0; 802 MemoryRegion *address_space_mem = get_system_memory(); 803 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 804 int nb_numa_nodes = machine->numa_state->num_nodes; 805 NodeInfo *numa_info = machine->numa_state->nodes; 806 int i; 807 const CPUArchIdList *possible_cpus; 808 MachineClass *mc = MACHINE_GET_CLASS(machine); 809 CPUState *cpu; 810 char *ramName = NULL; 811 812 if (!cpu_model) { 813 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 814 } 815 816 if (ram_size < 1 * GiB) { 817 error_report("ram_size must be greater than 1G."); 818 exit(1); 819 } 820 create_fdt(lams); 821 822 /* Create IOCSR space */ 823 memory_region_init_io(&lams->system_iocsr, OBJECT(machine), NULL, 824 machine, "iocsr", UINT64_MAX); 825 address_space_init(&lams->as_iocsr, &lams->system_iocsr, "IOCSR"); 826 memory_region_init_io(&lams->iocsr_mem, OBJECT(machine), 827 &loongarch_qemu_ops, 828 machine, "iocsr_misc", 0x428); 829 memory_region_add_subregion(&lams->system_iocsr, 0, &lams->iocsr_mem); 830 831 /* Init CPUs */ 832 possible_cpus = mc->possible_cpu_arch_ids(machine); 833 for (i = 0; i < possible_cpus->len; i++) { 834 cpu = cpu_create(machine->cpu_type); 835 cpu->cpu_index = i; 836 machine->possible_cpus->cpus[i].cpu = cpu; 837 lacpu = LOONGARCH_CPU(cpu); 838 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; 839 } 840 fdt_add_cpu_nodes(lams); 841 842 /* Node0 memory */ 843 memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1); 844 fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0); 845 memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram", 846 machine->ram, offset, VIRT_LOWMEM_SIZE); 847 memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem); 848 849 offset += VIRT_LOWMEM_SIZE; 850 if (nb_numa_nodes > 0) { 851 assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE); 852 highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE; 853 } else { 854 highram_size = ram_size - VIRT_LOWMEM_SIZE; 855 } 856 phyAddr = VIRT_HIGHMEM_BASE; 857 memmap_add_entry(phyAddr, highram_size, 1); 858 fdt_add_memory_node(machine, phyAddr, highram_size, 0); 859 memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram", 860 machine->ram, offset, highram_size); 861 memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem); 862 863 /* Node1 - Nodemax memory */ 864 offset += highram_size; 865 phyAddr += highram_size; 866 867 for (i = 1; i < nb_numa_nodes; i++) { 868 MemoryRegion *nodemem = g_new(MemoryRegion, 1); 869 ramName = g_strdup_printf("loongarch.node%d.ram", i); 870 memory_region_init_alias(nodemem, NULL, ramName, machine->ram, 871 offset, numa_info[i].node_mem); 872 memory_region_add_subregion(address_space_mem, phyAddr, nodemem); 873 memmap_add_entry(phyAddr, numa_info[i].node_mem, 1); 874 fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i); 875 offset += numa_info[i].node_mem; 876 phyAddr += numa_info[i].node_mem; 877 } 878 879 /* initialize device memory address space */ 880 if (machine->ram_size < machine->maxram_size) { 881 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 882 hwaddr device_mem_base; 883 884 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 885 error_report("unsupported amount of memory slots: %"PRIu64, 886 machine->ram_slots); 887 exit(EXIT_FAILURE); 888 } 889 890 if (QEMU_ALIGN_UP(machine->maxram_size, 891 TARGET_PAGE_SIZE) != machine->maxram_size) { 892 error_report("maximum memory size must by aligned to multiple of " 893 "%d bytes", TARGET_PAGE_SIZE); 894 exit(EXIT_FAILURE); 895 } 896 /* device memory base is the top of high memory address. */ 897 device_mem_base = ROUND_UP(VIRT_HIGHMEM_BASE + highram_size, 1 * GiB); 898 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 899 } 900 901 /* load the BIOS image. */ 902 loongarch_firmware_init(lams); 903 904 /* fw_cfg init */ 905 lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine); 906 rom_set_fw(lams->fw_cfg); 907 if (lams->fw_cfg != NULL) { 908 fw_cfg_add_file(lams->fw_cfg, "etc/memmap", 909 memmap_table, 910 sizeof(struct memmap_entry) * (memmap_entries)); 911 } 912 fdt_add_fw_cfg_node(lams); 913 fdt_add_flash_node(lams); 914 915 /* Initialize the IO interrupt subsystem */ 916 loongarch_irq_init(lams); 917 fdt_add_irqchip_node(lams); 918 platform_bus_add_all_fdt_nodes(machine->fdt, "/intc", 919 VIRT_PLATFORM_BUS_BASEADDRESS, 920 VIRT_PLATFORM_BUS_SIZE, 921 VIRT_PLATFORM_BUS_IRQ); 922 lams->machine_done.notify = virt_machine_done; 923 qemu_add_machine_init_done_notifier(&lams->machine_done); 924 /* connect powerdown request */ 925 lams->powerdown_notifier.notify = virt_powerdown_req; 926 qemu_register_powerdown_notifier(&lams->powerdown_notifier); 927 928 fdt_add_pcie_node(lams); 929 /* 930 * Since lowmem region starts from 0 and Linux kernel legacy start address 931 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer 932 * access. FDT size limit with 1 MiB. 933 * Put the FDT into the memory map as a ROM image: this will ensure 934 * the FDT is copied again upon reset, even if addr points into RAM. 935 */ 936 qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size); 937 rom_add_blob_fixed_as("fdt", machine->fdt, lams->fdt_size, FDT_BASE, 938 &address_space_memory); 939 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 940 rom_ptr_for_as(&address_space_memory, FDT_BASE, lams->fdt_size)); 941 942 lams->bootinfo.ram_size = ram_size; 943 loongarch_load_kernel(machine, &lams->bootinfo); 944 } 945 946 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) 947 { 948 if (lams->acpi == ON_OFF_AUTO_OFF) { 949 return false; 950 } 951 return true; 952 } 953 954 static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, 955 void *opaque, Error **errp) 956 { 957 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 958 OnOffAuto acpi = lams->acpi; 959 960 visit_type_OnOffAuto(v, name, &acpi, errp); 961 } 962 963 static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, 964 void *opaque, Error **errp) 965 { 966 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 967 968 visit_type_OnOffAuto(v, name, &lams->acpi, errp); 969 } 970 971 static void loongarch_machine_initfn(Object *obj) 972 { 973 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 974 975 lams->acpi = ON_OFF_AUTO_AUTO; 976 lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 977 lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 978 virt_flash_create(lams); 979 } 980 981 static bool memhp_type_supported(DeviceState *dev) 982 { 983 /* we only support pc dimm now */ 984 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 985 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 986 } 987 988 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 989 Error **errp) 990 { 991 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 992 } 993 994 static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev, 995 DeviceState *dev, Error **errp) 996 { 997 if (memhp_type_supported(dev)) { 998 virt_mem_pre_plug(hotplug_dev, dev, errp); 999 } 1000 } 1001 1002 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 1003 DeviceState *dev, Error **errp) 1004 { 1005 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1006 1007 /* the acpi ged is always exist */ 1008 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lams->acpi_ged), dev, 1009 errp); 1010 } 1011 1012 static void virt_machine_device_unplug_request(HotplugHandler *hotplug_dev, 1013 DeviceState *dev, Error **errp) 1014 { 1015 if (memhp_type_supported(dev)) { 1016 virt_mem_unplug_request(hotplug_dev, dev, errp); 1017 } 1018 } 1019 1020 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 1021 DeviceState *dev, Error **errp) 1022 { 1023 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1024 1025 hotplug_handler_unplug(HOTPLUG_HANDLER(lams->acpi_ged), dev, errp); 1026 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lams)); 1027 qdev_unrealize(dev); 1028 } 1029 1030 static void virt_machine_device_unplug(HotplugHandler *hotplug_dev, 1031 DeviceState *dev, Error **errp) 1032 { 1033 if (memhp_type_supported(dev)) { 1034 virt_mem_unplug(hotplug_dev, dev, errp); 1035 } 1036 } 1037 1038 static void virt_mem_plug(HotplugHandler *hotplug_dev, 1039 DeviceState *dev, Error **errp) 1040 { 1041 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1042 1043 pc_dimm_plug(PC_DIMM(dev), MACHINE(lams)); 1044 hotplug_handler_plug(HOTPLUG_HANDLER(lams->acpi_ged), 1045 dev, &error_abort); 1046 } 1047 1048 static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1049 DeviceState *dev, Error **errp) 1050 { 1051 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1052 MachineClass *mc = MACHINE_GET_CLASS(lams); 1053 1054 if (device_is_dynamic_sysbus(mc, dev)) { 1055 if (lams->platform_bus_dev) { 1056 platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev), 1057 SYS_BUS_DEVICE(dev)); 1058 } 1059 } else if (memhp_type_supported(dev)) { 1060 virt_mem_plug(hotplug_dev, dev, errp); 1061 } 1062 } 1063 1064 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1065 DeviceState *dev) 1066 { 1067 MachineClass *mc = MACHINE_GET_CLASS(machine); 1068 1069 if (device_is_dynamic_sysbus(mc, dev) || 1070 memhp_type_supported(dev)) { 1071 return HOTPLUG_HANDLER(machine); 1072 } 1073 return NULL; 1074 } 1075 1076 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1077 { 1078 int n; 1079 unsigned int max_cpus = ms->smp.max_cpus; 1080 1081 if (ms->possible_cpus) { 1082 assert(ms->possible_cpus->len == max_cpus); 1083 return ms->possible_cpus; 1084 } 1085 1086 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1087 sizeof(CPUArchId) * max_cpus); 1088 ms->possible_cpus->len = max_cpus; 1089 for (n = 0; n < ms->possible_cpus->len; n++) { 1090 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1091 ms->possible_cpus->cpus[n].arch_id = n; 1092 1093 ms->possible_cpus->cpus[n].props.has_socket_id = true; 1094 ms->possible_cpus->cpus[n].props.socket_id = 1095 n / (ms->smp.cores * ms->smp.threads); 1096 ms->possible_cpus->cpus[n].props.has_core_id = true; 1097 ms->possible_cpus->cpus[n].props.core_id = 1098 n / ms->smp.threads % ms->smp.cores; 1099 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1100 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 1101 } 1102 return ms->possible_cpus; 1103 } 1104 1105 static CpuInstanceProperties 1106 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1107 { 1108 MachineClass *mc = MACHINE_GET_CLASS(ms); 1109 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1110 1111 assert(cpu_index < possible_cpus->len); 1112 return possible_cpus->cpus[cpu_index].props; 1113 } 1114 1115 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1116 { 1117 int64_t nidx = 0; 1118 1119 if (ms->numa_state->num_nodes) { 1120 nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes); 1121 if (ms->numa_state->num_nodes <= nidx) { 1122 nidx = ms->numa_state->num_nodes - 1; 1123 } 1124 } 1125 return nidx; 1126 } 1127 1128 static void loongarch_class_init(ObjectClass *oc, void *data) 1129 { 1130 MachineClass *mc = MACHINE_CLASS(oc); 1131 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1132 1133 mc->desc = "Loongson-3A5000 LS7A1000 machine"; 1134 mc->init = loongarch_init; 1135 mc->default_ram_size = 1 * GiB; 1136 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 1137 mc->default_ram_id = "loongarch.ram"; 1138 mc->max_cpus = LOONGARCH_MAX_CPUS; 1139 mc->is_default = 1; 1140 mc->default_kernel_irqchip_split = false; 1141 mc->block_default_type = IF_VIRTIO; 1142 mc->default_boot_order = "c"; 1143 mc->no_cdrom = 1; 1144 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1145 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1146 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1147 mc->numa_mem_supported = true; 1148 mc->auto_enable_numa_with_memhp = true; 1149 mc->auto_enable_numa_with_memdev = true; 1150 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1151 mc->default_nic = "virtio-net-pci"; 1152 hc->plug = loongarch_machine_device_plug_cb; 1153 hc->pre_plug = virt_machine_device_pre_plug; 1154 hc->unplug_request = virt_machine_device_unplug_request; 1155 hc->unplug = virt_machine_device_unplug; 1156 1157 object_class_property_add(oc, "acpi", "OnOffAuto", 1158 loongarch_get_acpi, loongarch_set_acpi, 1159 NULL, NULL); 1160 object_class_property_set_description(oc, "acpi", 1161 "Enable ACPI"); 1162 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1163 #ifdef CONFIG_TPM 1164 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1165 #endif 1166 } 1167 1168 static const TypeInfo loongarch_machine_types[] = { 1169 { 1170 .name = TYPE_LOONGARCH_MACHINE, 1171 .parent = TYPE_MACHINE, 1172 .instance_size = sizeof(LoongArchMachineState), 1173 .class_init = loongarch_class_init, 1174 .instance_init = loongarch_machine_initfn, 1175 .interfaces = (InterfaceInfo[]) { 1176 { TYPE_HOTPLUG_HANDLER }, 1177 { } 1178 }, 1179 } 1180 }; 1181 1182 DEFINE_TYPES(loongarch_machine_types) 1183