1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/sysemu.h" 14 #include "sysemu/qtest.h" 15 #include "sysemu/runstate.h" 16 #include "sysemu/reset.h" 17 #include "sysemu/rtc.h" 18 #include "hw/loongarch/virt.h" 19 #include "exec/address-spaces.h" 20 #include "hw/irq.h" 21 #include "net/net.h" 22 #include "hw/loader.h" 23 #include "elf.h" 24 #include "hw/intc/loongarch_ipi.h" 25 #include "hw/intc/loongarch_extioi.h" 26 #include "hw/intc/loongarch_pch_pic.h" 27 #include "hw/intc/loongarch_pch_msi.h" 28 #include "hw/pci-host/ls7a.h" 29 #include "hw/pci-host/gpex.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/loongarch/fw_cfg.h" 32 #include "target/loongarch/cpu.h" 33 #include "hw/firmware/smbios.h" 34 #include "hw/acpi/aml-build.h" 35 #include "qapi/qapi-visit-common.h" 36 #include "hw/acpi/generic_event_device.h" 37 #include "hw/mem/nvdimm.h" 38 #include "sysemu/device_tree.h" 39 #include <libfdt.h> 40 #include "hw/core/sysbus-fdt.h" 41 #include "hw/platform-bus.h" 42 #include "hw/display/ramfb.h" 43 #include "hw/mem/pc-dimm.h" 44 #include "sysemu/tpm.h" 45 #include "sysemu/block-backend.h" 46 #include "hw/block/flash.h" 47 #include "qemu/error-report.h" 48 49 static PFlashCFI01 *virt_flash_create1(LoongArchMachineState *lams, 50 const char *name, 51 const char *alias_prop_name) 52 { 53 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 54 55 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 56 qdev_prop_set_uint8(dev, "width", 4); 57 qdev_prop_set_uint8(dev, "device-width", 2); 58 qdev_prop_set_bit(dev, "big-endian", false); 59 qdev_prop_set_uint16(dev, "id0", 0x89); 60 qdev_prop_set_uint16(dev, "id1", 0x18); 61 qdev_prop_set_uint16(dev, "id2", 0x00); 62 qdev_prop_set_uint16(dev, "id3", 0x00); 63 qdev_prop_set_string(dev, "name", name); 64 object_property_add_child(OBJECT(lams), name, OBJECT(dev)); 65 object_property_add_alias(OBJECT(lams), alias_prop_name, 66 OBJECT(dev), "drive"); 67 return PFLASH_CFI01(dev); 68 } 69 70 static void virt_flash_create(LoongArchMachineState *lams) 71 { 72 lams->flash[0] = virt_flash_create1(lams, "virt.flash0", "pflash0"); 73 lams->flash[1] = virt_flash_create1(lams, "virt.flash1", "pflash1"); 74 } 75 76 static void virt_flash_map1(PFlashCFI01 *flash, 77 hwaddr base, hwaddr size, 78 MemoryRegion *sysmem) 79 { 80 DeviceState *dev = DEVICE(flash); 81 BlockBackend *blk; 82 hwaddr real_size = size; 83 84 blk = pflash_cfi01_get_blk(flash); 85 if (blk) { 86 real_size = blk_getlength(blk); 87 assert(real_size && real_size <= size); 88 } 89 90 assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE)); 91 assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 92 93 qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE); 94 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 95 memory_region_add_subregion(sysmem, base, 96 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 97 } 98 99 static void virt_flash_map(LoongArchMachineState *lams, 100 MemoryRegion *sysmem) 101 { 102 PFlashCFI01 *flash0 = lams->flash[0]; 103 PFlashCFI01 *flash1 = lams->flash[1]; 104 105 virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem); 106 virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem); 107 } 108 109 static void fdt_add_cpuic_node(LoongArchMachineState *lams, 110 uint32_t *cpuintc_phandle) 111 { 112 MachineState *ms = MACHINE(lams); 113 char *nodename; 114 115 *cpuintc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 116 nodename = g_strdup_printf("/cpuic"); 117 qemu_fdt_add_subnode(ms->fdt, nodename); 118 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *cpuintc_phandle); 119 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 120 "loongson,cpu-interrupt-controller"); 121 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 122 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 123 g_free(nodename); 124 } 125 126 static void fdt_add_eiointc_node(LoongArchMachineState *lams, 127 uint32_t *cpuintc_phandle, 128 uint32_t *eiointc_phandle) 129 { 130 MachineState *ms = MACHINE(lams); 131 char *nodename; 132 hwaddr extioi_base = APIC_BASE; 133 hwaddr extioi_size = EXTIOI_SIZE; 134 135 *eiointc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 136 nodename = g_strdup_printf("/eiointc@%" PRIx64, extioi_base); 137 qemu_fdt_add_subnode(ms->fdt, nodename); 138 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *eiointc_phandle); 139 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 140 "loongson,ls2k2000-eiointc"); 141 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 142 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 143 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 144 *cpuintc_phandle); 145 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", 3); 146 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, 147 extioi_base, 0x0, extioi_size); 148 g_free(nodename); 149 } 150 151 static void fdt_add_pch_pic_node(LoongArchMachineState *lams, 152 uint32_t *eiointc_phandle, 153 uint32_t *pch_pic_phandle) 154 { 155 MachineState *ms = MACHINE(lams); 156 char *nodename; 157 hwaddr pch_pic_base = VIRT_PCH_REG_BASE; 158 hwaddr pch_pic_size = VIRT_PCH_REG_SIZE; 159 160 *pch_pic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 161 nodename = g_strdup_printf("/platic@%" PRIx64, pch_pic_base); 162 qemu_fdt_add_subnode(ms->fdt, nodename); 163 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_pic_phandle); 164 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 165 "loongson,pch-pic-1.0"); 166 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, 167 pch_pic_base, 0, pch_pic_size); 168 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 169 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 2); 170 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 171 *eiointc_phandle); 172 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,pic-base-vec", 0); 173 g_free(nodename); 174 } 175 176 static void fdt_add_pch_msi_node(LoongArchMachineState *lams, 177 uint32_t *eiointc_phandle, 178 uint32_t *pch_msi_phandle) 179 { 180 MachineState *ms = MACHINE(lams); 181 char *nodename; 182 hwaddr pch_msi_base = VIRT_PCH_MSI_ADDR_LOW; 183 hwaddr pch_msi_size = VIRT_PCH_MSI_SIZE; 184 185 *pch_msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 186 nodename = g_strdup_printf("/msi@%" PRIx64, pch_msi_base); 187 qemu_fdt_add_subnode(ms->fdt, nodename); 188 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_msi_phandle); 189 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 190 "loongson,pch-msi-1.0"); 191 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 192 0, pch_msi_base, 193 0, pch_msi_size); 194 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 195 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 196 *eiointc_phandle); 197 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-base-vec", 198 VIRT_PCH_PIC_IRQ_NUM); 199 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-num-vecs", 200 EXTIOI_IRQS - VIRT_PCH_PIC_IRQ_NUM); 201 g_free(nodename); 202 } 203 204 static void fdt_add_flash_node(LoongArchMachineState *lams) 205 { 206 MachineState *ms = MACHINE(lams); 207 char *nodename; 208 MemoryRegion *flash_mem; 209 210 hwaddr flash0_base; 211 hwaddr flash0_size; 212 213 hwaddr flash1_base; 214 hwaddr flash1_size; 215 216 flash_mem = pflash_cfi01_get_memory(lams->flash[0]); 217 flash0_base = flash_mem->addr; 218 flash0_size = memory_region_size(flash_mem); 219 220 flash_mem = pflash_cfi01_get_memory(lams->flash[1]); 221 flash1_base = flash_mem->addr; 222 flash1_size = memory_region_size(flash_mem); 223 224 nodename = g_strdup_printf("/flash@%" PRIx64, flash0_base); 225 qemu_fdt_add_subnode(ms->fdt, nodename); 226 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 227 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 228 2, flash0_base, 2, flash0_size, 229 2, flash1_base, 2, flash1_size); 230 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 231 g_free(nodename); 232 } 233 234 static void fdt_add_rtc_node(LoongArchMachineState *lams) 235 { 236 char *nodename; 237 hwaddr base = VIRT_RTC_REG_BASE; 238 hwaddr size = VIRT_RTC_LEN; 239 MachineState *ms = MACHINE(lams); 240 241 nodename = g_strdup_printf("/rtc@%" PRIx64, base); 242 qemu_fdt_add_subnode(ms->fdt, nodename); 243 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc"); 244 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 245 g_free(nodename); 246 } 247 248 static void fdt_add_uart_node(LoongArchMachineState *lams) 249 { 250 char *nodename; 251 hwaddr base = VIRT_UART_BASE; 252 hwaddr size = VIRT_UART_SIZE; 253 MachineState *ms = MACHINE(lams); 254 255 nodename = g_strdup_printf("/serial@%" PRIx64, base); 256 qemu_fdt_add_subnode(ms->fdt, nodename); 257 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); 258 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); 259 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); 260 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 261 g_free(nodename); 262 } 263 264 static void create_fdt(LoongArchMachineState *lams) 265 { 266 MachineState *ms = MACHINE(lams); 267 268 ms->fdt = create_device_tree(&lams->fdt_size); 269 if (!ms->fdt) { 270 error_report("create_device_tree() failed"); 271 exit(1); 272 } 273 274 /* Header */ 275 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 276 "linux,dummy-loongson3"); 277 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 278 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 279 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 280 } 281 282 static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) 283 { 284 int num; 285 const MachineState *ms = MACHINE(lams); 286 int smp_cpus = ms->smp.cpus; 287 288 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 289 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 290 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 291 292 /* cpu nodes */ 293 for (num = smp_cpus - 1; num >= 0; num--) { 294 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 295 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 296 CPUState *cs = CPU(cpu); 297 298 qemu_fdt_add_subnode(ms->fdt, nodename); 299 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 300 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 301 cpu->dtb_compatible); 302 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 303 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 304 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 305 } 306 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 307 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 308 qemu_fdt_alloc_phandle(ms->fdt)); 309 g_free(nodename); 310 } 311 312 /*cpu map */ 313 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 314 315 for (num = smp_cpus - 1; num >= 0; num--) { 316 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 317 char *map_path; 318 319 if (ms->smp.threads > 1) { 320 map_path = g_strdup_printf( 321 "/cpus/cpu-map/socket%d/core%d/thread%d", 322 num / (ms->smp.cores * ms->smp.threads), 323 (num / ms->smp.threads) % ms->smp.cores, 324 num % ms->smp.threads); 325 } else { 326 map_path = g_strdup_printf( 327 "/cpus/cpu-map/socket%d/core%d", 328 num / ms->smp.cores, 329 num % ms->smp.cores); 330 } 331 qemu_fdt_add_path(ms->fdt, map_path); 332 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 333 334 g_free(map_path); 335 g_free(cpu_path); 336 } 337 } 338 339 static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) 340 { 341 char *nodename; 342 hwaddr base = VIRT_FWCFG_BASE; 343 const MachineState *ms = MACHINE(lams); 344 345 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 346 qemu_fdt_add_subnode(ms->fdt, nodename); 347 qemu_fdt_setprop_string(ms->fdt, nodename, 348 "compatible", "qemu,fw-cfg-mmio"); 349 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 350 2, base, 2, 0x18); 351 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 352 g_free(nodename); 353 } 354 355 static void fdt_add_pcie_irq_map_node(const LoongArchMachineState *lams, 356 char *nodename, 357 uint32_t *pch_pic_phandle) 358 { 359 int pin, dev; 360 uint32_t irq_map_stride = 0; 361 uint32_t full_irq_map[GPEX_NUM_IRQS *GPEX_NUM_IRQS * 10] = {}; 362 uint32_t *irq_map = full_irq_map; 363 const MachineState *ms = MACHINE(lams); 364 365 /* This code creates a standard swizzle of interrupts such that 366 * each device's first interrupt is based on it's PCI_SLOT number. 367 * (See pci_swizzle_map_irq_fn()) 368 * 369 * We only need one entry per interrupt in the table (not one per 370 * possible slot) seeing the interrupt-map-mask will allow the table 371 * to wrap to any number of devices. 372 */ 373 374 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 375 int devfn = dev * 0x8; 376 377 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 378 int irq_nr = 16 + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 379 int i = 0; 380 381 /* Fill PCI address cells */ 382 irq_map[i] = cpu_to_be32(devfn << 8); 383 i += 3; 384 385 /* Fill PCI Interrupt cells */ 386 irq_map[i] = cpu_to_be32(pin + 1); 387 i += 1; 388 389 /* Fill interrupt controller phandle and cells */ 390 irq_map[i++] = cpu_to_be32(*pch_pic_phandle); 391 irq_map[i++] = cpu_to_be32(irq_nr); 392 393 if (!irq_map_stride) { 394 irq_map_stride = i; 395 } 396 irq_map += irq_map_stride; 397 } 398 } 399 400 401 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", full_irq_map, 402 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 403 irq_map_stride * sizeof(uint32_t)); 404 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 405 0x1800, 0, 0, 0x7); 406 } 407 408 static void fdt_add_pcie_node(const LoongArchMachineState *lams, 409 uint32_t *pch_pic_phandle, 410 uint32_t *pch_msi_phandle) 411 { 412 char *nodename; 413 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 414 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 415 hwaddr base_pio = VIRT_PCI_IO_BASE; 416 hwaddr size_pio = VIRT_PCI_IO_SIZE; 417 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 418 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 419 hwaddr base = base_pcie; 420 421 const MachineState *ms = MACHINE(lams); 422 423 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 424 qemu_fdt_add_subnode(ms->fdt, nodename); 425 qemu_fdt_setprop_string(ms->fdt, nodename, 426 "compatible", "pci-host-ecam-generic"); 427 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 428 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 429 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 430 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 431 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 432 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 433 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 434 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 435 2, base_pcie, 2, size_pcie); 436 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 437 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 438 2, base_pio, 2, size_pio, 439 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 440 2, base_mmio, 2, size_mmio); 441 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 442 0, *pch_msi_phandle, 0, 0x10000); 443 444 fdt_add_pcie_irq_map_node(lams, nodename, pch_pic_phandle); 445 446 g_free(nodename); 447 } 448 449 static void fdt_add_irqchip_node(LoongArchMachineState *lams) 450 { 451 MachineState *ms = MACHINE(lams); 452 char *nodename; 453 uint32_t irqchip_phandle; 454 455 irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt); 456 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle); 457 458 nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE); 459 qemu_fdt_add_subnode(ms->fdt, nodename); 460 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 461 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 462 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 463 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 464 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 465 466 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 467 "loongarch,ls7a"); 468 469 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 470 2, VIRT_IOAPIC_REG_BASE, 471 2, PCH_PIC_ROUTE_ENTRY_OFFSET); 472 473 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle); 474 g_free(nodename); 475 } 476 477 static void fdt_add_memory_node(MachineState *ms, 478 uint64_t base, uint64_t size, int node_id) 479 { 480 char *nodename = g_strdup_printf("/memory@%" PRIx64, base); 481 482 qemu_fdt_add_subnode(ms->fdt, nodename); 483 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, 0, size); 484 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 485 486 if (ms->numa_state && ms->numa_state->num_nodes) { 487 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); 488 } 489 490 g_free(nodename); 491 } 492 493 static void virt_build_smbios(LoongArchMachineState *lams) 494 { 495 MachineState *ms = MACHINE(lams); 496 MachineClass *mc = MACHINE_GET_CLASS(lams); 497 uint8_t *smbios_tables, *smbios_anchor; 498 size_t smbios_tables_len, smbios_anchor_len; 499 const char *product = "QEMU Virtual Machine"; 500 501 if (!lams->fw_cfg) { 502 return; 503 } 504 505 smbios_set_defaults("QEMU", product, mc->name, true); 506 507 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 508 NULL, 0, 509 &smbios_tables, &smbios_tables_len, 510 &smbios_anchor, &smbios_anchor_len, &error_fatal); 511 512 if (smbios_anchor) { 513 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", 514 smbios_tables, smbios_tables_len); 515 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", 516 smbios_anchor, smbios_anchor_len); 517 } 518 } 519 520 static void virt_machine_done(Notifier *notifier, void *data) 521 { 522 LoongArchMachineState *lams = container_of(notifier, 523 LoongArchMachineState, machine_done); 524 virt_build_smbios(lams); 525 loongarch_acpi_setup(lams); 526 } 527 528 static void virt_powerdown_req(Notifier *notifier, void *opaque) 529 { 530 LoongArchMachineState *s = container_of(notifier, 531 LoongArchMachineState, powerdown_notifier); 532 533 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 534 } 535 536 struct memmap_entry *memmap_table; 537 unsigned memmap_entries; 538 539 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 540 { 541 /* Ensure there are no duplicate entries. */ 542 for (unsigned i = 0; i < memmap_entries; i++) { 543 assert(memmap_table[i].address != address); 544 } 545 546 memmap_table = g_renew(struct memmap_entry, memmap_table, 547 memmap_entries + 1); 548 memmap_table[memmap_entries].address = cpu_to_le64(address); 549 memmap_table[memmap_entries].length = cpu_to_le64(length); 550 memmap_table[memmap_entries].type = cpu_to_le32(type); 551 memmap_table[memmap_entries].reserved = 0; 552 memmap_entries++; 553 } 554 555 static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams) 556 { 557 DeviceState *dev; 558 MachineState *ms = MACHINE(lams); 559 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 560 561 if (ms->ram_slots) { 562 event |= ACPI_GED_MEM_HOTPLUG_EVT; 563 } 564 dev = qdev_new(TYPE_ACPI_GED); 565 qdev_prop_set_uint32(dev, "ged-event", event); 566 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 567 568 /* ged event */ 569 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 570 /* memory hotplug */ 571 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 572 /* ged regs used for reset and power down */ 573 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 574 575 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 576 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 577 return dev; 578 } 579 580 static DeviceState *create_platform_bus(DeviceState *pch_pic) 581 { 582 DeviceState *dev; 583 SysBusDevice *sysbus; 584 int i, irq; 585 MemoryRegion *sysmem = get_system_memory(); 586 587 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 588 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 589 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 590 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 591 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 592 593 sysbus = SYS_BUS_DEVICE(dev); 594 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 595 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 596 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 597 } 598 599 memory_region_add_subregion(sysmem, 600 VIRT_PLATFORM_BUS_BASEADDRESS, 601 sysbus_mmio_get_region(sysbus, 0)); 602 return dev; 603 } 604 605 static void loongarch_devices_init(DeviceState *pch_pic, 606 LoongArchMachineState *lams, 607 uint32_t *pch_pic_phandle, 608 uint32_t *pch_msi_phandle) 609 { 610 MachineClass *mc = MACHINE_GET_CLASS(lams); 611 DeviceState *gpex_dev; 612 SysBusDevice *d; 613 PCIBus *pci_bus; 614 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 615 MemoryRegion *mmio_alias, *mmio_reg; 616 int i; 617 618 gpex_dev = qdev_new(TYPE_GPEX_HOST); 619 d = SYS_BUS_DEVICE(gpex_dev); 620 sysbus_realize_and_unref(d, &error_fatal); 621 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 622 lams->pci_bus = pci_bus; 623 624 /* Map only part size_ecam bytes of ECAM space */ 625 ecam_alias = g_new0(MemoryRegion, 1); 626 ecam_reg = sysbus_mmio_get_region(d, 0); 627 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 628 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 629 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 630 ecam_alias); 631 632 /* Map PCI mem space */ 633 mmio_alias = g_new0(MemoryRegion, 1); 634 mmio_reg = sysbus_mmio_get_region(d, 1); 635 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 636 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 637 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 638 mmio_alias); 639 640 /* Map PCI IO port space. */ 641 pio_alias = g_new0(MemoryRegion, 1); 642 pio_reg = sysbus_mmio_get_region(d, 2); 643 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 644 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 645 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 646 pio_alias); 647 648 for (i = 0; i < GPEX_NUM_IRQS; i++) { 649 sysbus_connect_irq(d, i, 650 qdev_get_gpio_in(pch_pic, 16 + i)); 651 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 652 } 653 654 /* Add pcie node */ 655 fdt_add_pcie_node(lams, pch_pic_phandle, pch_msi_phandle); 656 657 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 658 qdev_get_gpio_in(pch_pic, 659 VIRT_UART_IRQ - VIRT_GSI_BASE), 660 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 661 fdt_add_uart_node(lams); 662 663 /* Network init */ 664 pci_init_nic_devices(pci_bus, mc->default_nic); 665 666 /* 667 * There are some invalid guest memory access. 668 * Create some unimplemented devices to emulate this. 669 */ 670 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 671 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 672 qdev_get_gpio_in(pch_pic, 673 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 674 fdt_add_rtc_node(lams); 675 676 /* acpi ged */ 677 lams->acpi_ged = create_acpi_ged(pch_pic, lams); 678 /* platform bus */ 679 lams->platform_bus_dev = create_platform_bus(pch_pic); 680 } 681 682 static void loongarch_irq_init(LoongArchMachineState *lams) 683 { 684 MachineState *ms = MACHINE(lams); 685 DeviceState *pch_pic, *pch_msi, *cpudev; 686 DeviceState *ipi, *extioi; 687 SysBusDevice *d; 688 LoongArchCPU *lacpu; 689 CPULoongArchState *env; 690 CPUState *cpu_state; 691 int cpu, pin, i, start, num; 692 uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle; 693 694 /* 695 * The connection of interrupts: 696 * +-----+ +---------+ +-------+ 697 * | IPI |--> | CPUINTC | <-- | Timer | 698 * +-----+ +---------+ +-------+ 699 * ^ 700 * | 701 * +---------+ 702 * | EIOINTC | 703 * +---------+ 704 * ^ ^ 705 * | | 706 * +---------+ +---------+ 707 * | PCH-PIC | | PCH-MSI | 708 * +---------+ +---------+ 709 * ^ ^ ^ 710 * | | | 711 * +--------+ +---------+ +---------+ 712 * | UARTs | | Devices | | Devices | 713 * +--------+ +---------+ +---------+ 714 */ 715 716 /* Create IPI device */ 717 ipi = qdev_new(TYPE_LOONGARCH_IPI); 718 qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); 719 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 720 721 /* IPI iocsr memory region */ 722 memory_region_add_subregion(&lams->system_iocsr, SMP_IPI_MAILBOX, 723 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); 724 memory_region_add_subregion(&lams->system_iocsr, MAIL_SEND_ADDR, 725 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); 726 727 /* Add cpu interrupt-controller */ 728 fdt_add_cpuic_node(lams, &cpuintc_phandle); 729 730 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 731 cpu_state = qemu_get_cpu(cpu); 732 cpudev = DEVICE(cpu_state); 733 lacpu = LOONGARCH_CPU(cpu_state); 734 env = &(lacpu->env); 735 env->address_space_iocsr = &lams->as_iocsr; 736 737 /* connect ipi irq to cpu irq */ 738 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); 739 env->ipistate = ipi; 740 } 741 742 /* Create EXTIOI device */ 743 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 744 qdev_prop_set_uint32(extioi, "num-cpu", ms->smp.cpus); 745 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 746 memory_region_add_subregion(&lams->system_iocsr, APIC_BASE, 747 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); 748 749 /* 750 * connect ext irq to the cpu irq 751 * cpu_pin[9:2] <= intc_pin[7:0] 752 */ 753 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 754 cpudev = DEVICE(qemu_get_cpu(cpu)); 755 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 756 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 757 qdev_get_gpio_in(cpudev, pin + 2)); 758 } 759 } 760 761 /* Add Extend I/O Interrupt Controller node */ 762 fdt_add_eiointc_node(lams, &cpuintc_phandle, &eiointc_phandle); 763 764 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 765 num = VIRT_PCH_PIC_IRQ_NUM; 766 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 767 d = SYS_BUS_DEVICE(pch_pic); 768 sysbus_realize_and_unref(d, &error_fatal); 769 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 770 sysbus_mmio_get_region(d, 0)); 771 memory_region_add_subregion(get_system_memory(), 772 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 773 sysbus_mmio_get_region(d, 1)); 774 memory_region_add_subregion(get_system_memory(), 775 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 776 sysbus_mmio_get_region(d, 2)); 777 778 /* Connect pch_pic irqs to extioi */ 779 for (i = 0; i < num; i++) { 780 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 781 } 782 783 /* Add PCH PIC node */ 784 fdt_add_pch_pic_node(lams, &eiointc_phandle, &pch_pic_phandle); 785 786 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 787 start = num; 788 num = EXTIOI_IRQS - start; 789 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 790 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 791 d = SYS_BUS_DEVICE(pch_msi); 792 sysbus_realize_and_unref(d, &error_fatal); 793 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 794 for (i = 0; i < num; i++) { 795 /* Connect pch_msi irqs to extioi */ 796 qdev_connect_gpio_out(DEVICE(d), i, 797 qdev_get_gpio_in(extioi, i + start)); 798 } 799 800 /* Add PCH MSI node */ 801 fdt_add_pch_msi_node(lams, &eiointc_phandle, &pch_msi_phandle); 802 803 loongarch_devices_init(pch_pic, lams, &pch_pic_phandle, &pch_msi_phandle); 804 } 805 806 static void loongarch_firmware_init(LoongArchMachineState *lams) 807 { 808 char *filename = MACHINE(lams)->firmware; 809 char *bios_name = NULL; 810 int bios_size, i; 811 BlockBackend *pflash_blk0; 812 MemoryRegion *mr; 813 814 lams->bios_loaded = false; 815 816 /* Map legacy -drive if=pflash to machine properties */ 817 for (i = 0; i < ARRAY_SIZE(lams->flash); i++) { 818 pflash_cfi01_legacy_drive(lams->flash[i], 819 drive_get(IF_PFLASH, 0, i)); 820 } 821 822 virt_flash_map(lams, get_system_memory()); 823 824 pflash_blk0 = pflash_cfi01_get_blk(lams->flash[0]); 825 826 if (pflash_blk0) { 827 if (filename) { 828 error_report("cannot use both '-bios' and '-drive if=pflash'" 829 "options at once"); 830 exit(1); 831 } 832 lams->bios_loaded = true; 833 return; 834 } 835 836 if (filename) { 837 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 838 if (!bios_name) { 839 error_report("Could not find ROM image '%s'", filename); 840 exit(1); 841 } 842 843 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lams->flash[0]), 0); 844 bios_size = load_image_mr(bios_name, mr); 845 if (bios_size < 0) { 846 error_report("Could not load ROM image '%s'", bios_name); 847 exit(1); 848 } 849 g_free(bios_name); 850 lams->bios_loaded = true; 851 } 852 } 853 854 855 static void loongarch_qemu_write(void *opaque, hwaddr addr, 856 uint64_t val, unsigned size) 857 { 858 } 859 860 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) 861 { 862 switch (addr) { 863 case VERSION_REG: 864 return 0x11ULL; 865 case FEATURE_REG: 866 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 867 1ULL << IOCSRF_CSRIPI; 868 case VENDOR_REG: 869 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 870 case CPUNAME_REG: 871 return 0x303030354133ULL; /* "3A5000" */ 872 case MISC_FUNC_REG: 873 return 1ULL << IOCSRM_EXTIOI_EN; 874 } 875 return 0ULL; 876 } 877 878 static const MemoryRegionOps loongarch_qemu_ops = { 879 .read = loongarch_qemu_read, 880 .write = loongarch_qemu_write, 881 .endianness = DEVICE_LITTLE_ENDIAN, 882 .valid = { 883 .min_access_size = 4, 884 .max_access_size = 8, 885 }, 886 .impl = { 887 .min_access_size = 8, 888 .max_access_size = 8, 889 }, 890 }; 891 892 static void loongarch_init(MachineState *machine) 893 { 894 LoongArchCPU *lacpu; 895 const char *cpu_model = machine->cpu_type; 896 ram_addr_t offset = 0; 897 ram_addr_t ram_size = machine->ram_size; 898 uint64_t highram_size = 0, phyAddr = 0; 899 MemoryRegion *address_space_mem = get_system_memory(); 900 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 901 int nb_numa_nodes = machine->numa_state->num_nodes; 902 NodeInfo *numa_info = machine->numa_state->nodes; 903 int i; 904 const CPUArchIdList *possible_cpus; 905 MachineClass *mc = MACHINE_GET_CLASS(machine); 906 CPUState *cpu; 907 char *ramName = NULL; 908 909 if (!cpu_model) { 910 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 911 } 912 913 if (ram_size < 1 * GiB) { 914 error_report("ram_size must be greater than 1G."); 915 exit(1); 916 } 917 create_fdt(lams); 918 919 /* Create IOCSR space */ 920 memory_region_init_io(&lams->system_iocsr, OBJECT(machine), NULL, 921 machine, "iocsr", UINT64_MAX); 922 address_space_init(&lams->as_iocsr, &lams->system_iocsr, "IOCSR"); 923 memory_region_init_io(&lams->iocsr_mem, OBJECT(machine), 924 &loongarch_qemu_ops, 925 machine, "iocsr_misc", 0x428); 926 memory_region_add_subregion(&lams->system_iocsr, 0, &lams->iocsr_mem); 927 928 /* Init CPUs */ 929 possible_cpus = mc->possible_cpu_arch_ids(machine); 930 for (i = 0; i < possible_cpus->len; i++) { 931 cpu = cpu_create(machine->cpu_type); 932 cpu->cpu_index = i; 933 machine->possible_cpus->cpus[i].cpu = cpu; 934 lacpu = LOONGARCH_CPU(cpu); 935 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; 936 } 937 fdt_add_cpu_nodes(lams); 938 939 /* Node0 memory */ 940 memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1); 941 fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0); 942 memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram", 943 machine->ram, offset, VIRT_LOWMEM_SIZE); 944 memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem); 945 946 offset += VIRT_LOWMEM_SIZE; 947 if (nb_numa_nodes > 0) { 948 assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE); 949 highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE; 950 } else { 951 highram_size = ram_size - VIRT_LOWMEM_SIZE; 952 } 953 phyAddr = VIRT_HIGHMEM_BASE; 954 memmap_add_entry(phyAddr, highram_size, 1); 955 fdt_add_memory_node(machine, phyAddr, highram_size, 0); 956 memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram", 957 machine->ram, offset, highram_size); 958 memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem); 959 960 /* Node1 - Nodemax memory */ 961 offset += highram_size; 962 phyAddr += highram_size; 963 964 for (i = 1; i < nb_numa_nodes; i++) { 965 MemoryRegion *nodemem = g_new(MemoryRegion, 1); 966 ramName = g_strdup_printf("loongarch.node%d.ram", i); 967 memory_region_init_alias(nodemem, NULL, ramName, machine->ram, 968 offset, numa_info[i].node_mem); 969 memory_region_add_subregion(address_space_mem, phyAddr, nodemem); 970 memmap_add_entry(phyAddr, numa_info[i].node_mem, 1); 971 fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i); 972 offset += numa_info[i].node_mem; 973 phyAddr += numa_info[i].node_mem; 974 } 975 976 /* initialize device memory address space */ 977 if (machine->ram_size < machine->maxram_size) { 978 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 979 hwaddr device_mem_base; 980 981 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 982 error_report("unsupported amount of memory slots: %"PRIu64, 983 machine->ram_slots); 984 exit(EXIT_FAILURE); 985 } 986 987 if (QEMU_ALIGN_UP(machine->maxram_size, 988 TARGET_PAGE_SIZE) != machine->maxram_size) { 989 error_report("maximum memory size must by aligned to multiple of " 990 "%d bytes", TARGET_PAGE_SIZE); 991 exit(EXIT_FAILURE); 992 } 993 /* device memory base is the top of high memory address. */ 994 device_mem_base = ROUND_UP(VIRT_HIGHMEM_BASE + highram_size, 1 * GiB); 995 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 996 } 997 998 /* load the BIOS image. */ 999 loongarch_firmware_init(lams); 1000 1001 /* fw_cfg init */ 1002 lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine); 1003 rom_set_fw(lams->fw_cfg); 1004 if (lams->fw_cfg != NULL) { 1005 fw_cfg_add_file(lams->fw_cfg, "etc/memmap", 1006 memmap_table, 1007 sizeof(struct memmap_entry) * (memmap_entries)); 1008 } 1009 fdt_add_fw_cfg_node(lams); 1010 fdt_add_flash_node(lams); 1011 1012 /* Initialize the IO interrupt subsystem */ 1013 loongarch_irq_init(lams); 1014 fdt_add_irqchip_node(lams); 1015 platform_bus_add_all_fdt_nodes(machine->fdt, "/intc", 1016 VIRT_PLATFORM_BUS_BASEADDRESS, 1017 VIRT_PLATFORM_BUS_SIZE, 1018 VIRT_PLATFORM_BUS_IRQ); 1019 lams->machine_done.notify = virt_machine_done; 1020 qemu_add_machine_init_done_notifier(&lams->machine_done); 1021 /* connect powerdown request */ 1022 lams->powerdown_notifier.notify = virt_powerdown_req; 1023 qemu_register_powerdown_notifier(&lams->powerdown_notifier); 1024 1025 /* 1026 * Since lowmem region starts from 0 and Linux kernel legacy start address 1027 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer 1028 * access. FDT size limit with 1 MiB. 1029 * Put the FDT into the memory map as a ROM image: this will ensure 1030 * the FDT is copied again upon reset, even if addr points into RAM. 1031 */ 1032 qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size); 1033 rom_add_blob_fixed_as("fdt", machine->fdt, lams->fdt_size, FDT_BASE, 1034 &address_space_memory); 1035 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 1036 rom_ptr_for_as(&address_space_memory, FDT_BASE, lams->fdt_size)); 1037 1038 lams->bootinfo.ram_size = ram_size; 1039 loongarch_load_kernel(machine, &lams->bootinfo); 1040 } 1041 1042 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) 1043 { 1044 if (lams->acpi == ON_OFF_AUTO_OFF) { 1045 return false; 1046 } 1047 return true; 1048 } 1049 1050 static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, 1051 void *opaque, Error **errp) 1052 { 1053 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 1054 OnOffAuto acpi = lams->acpi; 1055 1056 visit_type_OnOffAuto(v, name, &acpi, errp); 1057 } 1058 1059 static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, 1060 void *opaque, Error **errp) 1061 { 1062 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 1063 1064 visit_type_OnOffAuto(v, name, &lams->acpi, errp); 1065 } 1066 1067 static void loongarch_machine_initfn(Object *obj) 1068 { 1069 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 1070 1071 lams->acpi = ON_OFF_AUTO_AUTO; 1072 lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1073 lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1074 virt_flash_create(lams); 1075 } 1076 1077 static bool memhp_type_supported(DeviceState *dev) 1078 { 1079 /* we only support pc dimm now */ 1080 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 1081 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1082 } 1083 1084 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1085 Error **errp) 1086 { 1087 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 1088 } 1089 1090 static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev, 1091 DeviceState *dev, Error **errp) 1092 { 1093 if (memhp_type_supported(dev)) { 1094 virt_mem_pre_plug(hotplug_dev, dev, errp); 1095 } 1096 } 1097 1098 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 1099 DeviceState *dev, Error **errp) 1100 { 1101 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1102 1103 /* the acpi ged is always exist */ 1104 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lams->acpi_ged), dev, 1105 errp); 1106 } 1107 1108 static void virt_machine_device_unplug_request(HotplugHandler *hotplug_dev, 1109 DeviceState *dev, Error **errp) 1110 { 1111 if (memhp_type_supported(dev)) { 1112 virt_mem_unplug_request(hotplug_dev, dev, errp); 1113 } 1114 } 1115 1116 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 1117 DeviceState *dev, Error **errp) 1118 { 1119 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1120 1121 hotplug_handler_unplug(HOTPLUG_HANDLER(lams->acpi_ged), dev, errp); 1122 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lams)); 1123 qdev_unrealize(dev); 1124 } 1125 1126 static void virt_machine_device_unplug(HotplugHandler *hotplug_dev, 1127 DeviceState *dev, Error **errp) 1128 { 1129 if (memhp_type_supported(dev)) { 1130 virt_mem_unplug(hotplug_dev, dev, errp); 1131 } 1132 } 1133 1134 static void virt_mem_plug(HotplugHandler *hotplug_dev, 1135 DeviceState *dev, Error **errp) 1136 { 1137 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1138 1139 pc_dimm_plug(PC_DIMM(dev), MACHINE(lams)); 1140 hotplug_handler_plug(HOTPLUG_HANDLER(lams->acpi_ged), 1141 dev, &error_abort); 1142 } 1143 1144 static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1145 DeviceState *dev, Error **errp) 1146 { 1147 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1148 MachineClass *mc = MACHINE_GET_CLASS(lams); 1149 1150 if (device_is_dynamic_sysbus(mc, dev)) { 1151 if (lams->platform_bus_dev) { 1152 platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev), 1153 SYS_BUS_DEVICE(dev)); 1154 } 1155 } else if (memhp_type_supported(dev)) { 1156 virt_mem_plug(hotplug_dev, dev, errp); 1157 } 1158 } 1159 1160 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1161 DeviceState *dev) 1162 { 1163 MachineClass *mc = MACHINE_GET_CLASS(machine); 1164 1165 if (device_is_dynamic_sysbus(mc, dev) || 1166 memhp_type_supported(dev)) { 1167 return HOTPLUG_HANDLER(machine); 1168 } 1169 return NULL; 1170 } 1171 1172 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1173 { 1174 int n; 1175 unsigned int max_cpus = ms->smp.max_cpus; 1176 1177 if (ms->possible_cpus) { 1178 assert(ms->possible_cpus->len == max_cpus); 1179 return ms->possible_cpus; 1180 } 1181 1182 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1183 sizeof(CPUArchId) * max_cpus); 1184 ms->possible_cpus->len = max_cpus; 1185 for (n = 0; n < ms->possible_cpus->len; n++) { 1186 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1187 ms->possible_cpus->cpus[n].arch_id = n; 1188 1189 ms->possible_cpus->cpus[n].props.has_socket_id = true; 1190 ms->possible_cpus->cpus[n].props.socket_id = 1191 n / (ms->smp.cores * ms->smp.threads); 1192 ms->possible_cpus->cpus[n].props.has_core_id = true; 1193 ms->possible_cpus->cpus[n].props.core_id = 1194 n / ms->smp.threads % ms->smp.cores; 1195 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1196 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 1197 } 1198 return ms->possible_cpus; 1199 } 1200 1201 static CpuInstanceProperties 1202 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1203 { 1204 MachineClass *mc = MACHINE_GET_CLASS(ms); 1205 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1206 1207 assert(cpu_index < possible_cpus->len); 1208 return possible_cpus->cpus[cpu_index].props; 1209 } 1210 1211 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1212 { 1213 int64_t nidx = 0; 1214 1215 if (ms->numa_state->num_nodes) { 1216 nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes); 1217 if (ms->numa_state->num_nodes <= nidx) { 1218 nidx = ms->numa_state->num_nodes - 1; 1219 } 1220 } 1221 return nidx; 1222 } 1223 1224 static void loongarch_class_init(ObjectClass *oc, void *data) 1225 { 1226 MachineClass *mc = MACHINE_CLASS(oc); 1227 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1228 1229 mc->desc = "Loongson-3A5000 LS7A1000 machine"; 1230 mc->init = loongarch_init; 1231 mc->default_ram_size = 1 * GiB; 1232 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 1233 mc->default_ram_id = "loongarch.ram"; 1234 mc->max_cpus = LOONGARCH_MAX_CPUS; 1235 mc->is_default = 1; 1236 mc->default_kernel_irqchip_split = false; 1237 mc->block_default_type = IF_VIRTIO; 1238 mc->default_boot_order = "c"; 1239 mc->no_cdrom = 1; 1240 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1241 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1242 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1243 mc->numa_mem_supported = true; 1244 mc->auto_enable_numa_with_memhp = true; 1245 mc->auto_enable_numa_with_memdev = true; 1246 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1247 mc->default_nic = "virtio-net-pci"; 1248 hc->plug = loongarch_machine_device_plug_cb; 1249 hc->pre_plug = virt_machine_device_pre_plug; 1250 hc->unplug_request = virt_machine_device_unplug_request; 1251 hc->unplug = virt_machine_device_unplug; 1252 1253 object_class_property_add(oc, "acpi", "OnOffAuto", 1254 loongarch_get_acpi, loongarch_set_acpi, 1255 NULL, NULL); 1256 object_class_property_set_description(oc, "acpi", 1257 "Enable ACPI"); 1258 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1259 #ifdef CONFIG_TPM 1260 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1261 #endif 1262 } 1263 1264 static const TypeInfo loongarch_machine_types[] = { 1265 { 1266 .name = TYPE_LOONGARCH_MACHINE, 1267 .parent = TYPE_MACHINE, 1268 .instance_size = sizeof(LoongArchMachineState), 1269 .class_init = loongarch_class_init, 1270 .instance_init = loongarch_machine_initfn, 1271 .interfaces = (InterfaceInfo[]) { 1272 { TYPE_HOTPLUG_HANDLER }, 1273 { } 1274 }, 1275 } 1276 }; 1277 1278 DEFINE_TYPES(loongarch_machine_types) 1279