1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/sysemu.h" 14 #include "sysemu/qtest.h" 15 #include "sysemu/runstate.h" 16 #include "sysemu/reset.h" 17 #include "sysemu/rtc.h" 18 #include "hw/loongarch/virt.h" 19 #include "exec/address-spaces.h" 20 #include "hw/irq.h" 21 #include "net/net.h" 22 #include "hw/loader.h" 23 #include "elf.h" 24 #include "hw/intc/loongarch_ipi.h" 25 #include "hw/intc/loongarch_extioi.h" 26 #include "hw/intc/loongarch_pch_pic.h" 27 #include "hw/intc/loongarch_pch_msi.h" 28 #include "hw/pci-host/ls7a.h" 29 #include "hw/pci-host/gpex.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/loongarch/fw_cfg.h" 32 #include "target/loongarch/cpu.h" 33 #include "hw/firmware/smbios.h" 34 #include "hw/acpi/aml-build.h" 35 #include "qapi/qapi-visit-common.h" 36 #include "hw/acpi/generic_event_device.h" 37 #include "hw/mem/nvdimm.h" 38 #include "sysemu/device_tree.h" 39 #include <libfdt.h> 40 #include "hw/core/sysbus-fdt.h" 41 #include "hw/platform-bus.h" 42 #include "hw/display/ramfb.h" 43 #include "hw/mem/pc-dimm.h" 44 45 static void create_fdt(LoongArchMachineState *lams) 46 { 47 MachineState *ms = MACHINE(lams); 48 49 ms->fdt = create_device_tree(&lams->fdt_size); 50 if (!ms->fdt) { 51 error_report("create_device_tree() failed"); 52 exit(1); 53 } 54 55 /* Header */ 56 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 57 "linux,dummy-loongson3"); 58 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 59 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 60 } 61 62 static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) 63 { 64 int num; 65 const MachineState *ms = MACHINE(lams); 66 int smp_cpus = ms->smp.cpus; 67 68 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 69 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 70 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 71 72 /* cpu nodes */ 73 for (num = smp_cpus - 1; num >= 0; num--) { 74 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 75 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 76 77 qemu_fdt_add_subnode(ms->fdt, nodename); 78 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 79 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 80 cpu->dtb_compatible); 81 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 82 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 83 qemu_fdt_alloc_phandle(ms->fdt)); 84 g_free(nodename); 85 } 86 87 /*cpu map */ 88 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 89 90 for (num = smp_cpus - 1; num >= 0; num--) { 91 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 92 char *map_path; 93 94 if (ms->smp.threads > 1) { 95 map_path = g_strdup_printf( 96 "/cpus/cpu-map/socket%d/core%d/thread%d", 97 num / (ms->smp.cores * ms->smp.threads), 98 (num / ms->smp.threads) % ms->smp.cores, 99 num % ms->smp.threads); 100 } else { 101 map_path = g_strdup_printf( 102 "/cpus/cpu-map/socket%d/core%d", 103 num / ms->smp.cores, 104 num % ms->smp.cores); 105 } 106 qemu_fdt_add_path(ms->fdt, map_path); 107 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 108 109 g_free(map_path); 110 g_free(cpu_path); 111 } 112 } 113 114 static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) 115 { 116 char *nodename; 117 hwaddr base = VIRT_FWCFG_BASE; 118 const MachineState *ms = MACHINE(lams); 119 120 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 121 qemu_fdt_add_subnode(ms->fdt, nodename); 122 qemu_fdt_setprop_string(ms->fdt, nodename, 123 "compatible", "qemu,fw-cfg-mmio"); 124 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 125 2, base, 2, 0x18); 126 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 127 g_free(nodename); 128 } 129 130 static void fdt_add_pcie_node(const LoongArchMachineState *lams) 131 { 132 char *nodename; 133 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 134 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 135 hwaddr base_pio = VIRT_PCI_IO_BASE; 136 hwaddr size_pio = VIRT_PCI_IO_SIZE; 137 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 138 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 139 hwaddr base = base_pcie; 140 141 const MachineState *ms = MACHINE(lams); 142 143 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 144 qemu_fdt_add_subnode(ms->fdt, nodename); 145 qemu_fdt_setprop_string(ms->fdt, nodename, 146 "compatible", "pci-host-ecam-generic"); 147 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 148 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 149 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 150 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 151 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 152 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 153 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 154 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 155 2, base_pcie, 2, size_pcie); 156 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 157 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 158 2, base_pio, 2, size_pio, 159 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 160 2, base_mmio, 2, size_mmio); 161 g_free(nodename); 162 } 163 164 static void fdt_add_irqchip_node(LoongArchMachineState *lams) 165 { 166 MachineState *ms = MACHINE(lams); 167 char *nodename; 168 uint32_t irqchip_phandle; 169 170 irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt); 171 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle); 172 173 nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE); 174 qemu_fdt_add_subnode(ms->fdt, nodename); 175 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 176 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 177 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 178 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 179 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 180 181 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 182 "loongarch,ls7a"); 183 184 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 185 2, VIRT_IOAPIC_REG_BASE, 186 2, PCH_PIC_ROUTE_ENTRY_OFFSET); 187 188 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle); 189 g_free(nodename); 190 } 191 192 #define PM_BASE 0x10080000 193 #define PM_SIZE 0x100 194 #define PM_CTRL 0x10 195 196 static void virt_build_smbios(LoongArchMachineState *lams) 197 { 198 MachineState *ms = MACHINE(lams); 199 MachineClass *mc = MACHINE_GET_CLASS(lams); 200 uint8_t *smbios_tables, *smbios_anchor; 201 size_t smbios_tables_len, smbios_anchor_len; 202 const char *product = "QEMU Virtual Machine"; 203 204 if (!lams->fw_cfg) { 205 return; 206 } 207 208 smbios_set_defaults("QEMU", product, mc->name, false, 209 true, SMBIOS_ENTRY_POINT_TYPE_64); 210 211 smbios_get_tables(ms, NULL, 0, &smbios_tables, &smbios_tables_len, 212 &smbios_anchor, &smbios_anchor_len, &error_fatal); 213 214 if (smbios_anchor) { 215 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", 216 smbios_tables, smbios_tables_len); 217 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", 218 smbios_anchor, smbios_anchor_len); 219 } 220 } 221 222 static void virt_machine_done(Notifier *notifier, void *data) 223 { 224 LoongArchMachineState *lams = container_of(notifier, 225 LoongArchMachineState, machine_done); 226 virt_build_smbios(lams); 227 loongarch_acpi_setup(lams); 228 } 229 230 struct memmap_entry { 231 uint64_t address; 232 uint64_t length; 233 uint32_t type; 234 uint32_t reserved; 235 }; 236 237 static struct memmap_entry *memmap_table; 238 static unsigned memmap_entries; 239 240 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 241 { 242 /* Ensure there are no duplicate entries. */ 243 for (unsigned i = 0; i < memmap_entries; i++) { 244 assert(memmap_table[i].address != address); 245 } 246 247 memmap_table = g_renew(struct memmap_entry, memmap_table, 248 memmap_entries + 1); 249 memmap_table[memmap_entries].address = cpu_to_le64(address); 250 memmap_table[memmap_entries].length = cpu_to_le64(length); 251 memmap_table[memmap_entries].type = cpu_to_le32(type); 252 memmap_table[memmap_entries].reserved = 0; 253 memmap_entries++; 254 } 255 256 /* 257 * This is a placeholder for missing ACPI, 258 * and will eventually be replaced. 259 */ 260 static uint64_t loongarch_virt_pm_read(void *opaque, hwaddr addr, unsigned size) 261 { 262 return 0; 263 } 264 265 static void loongarch_virt_pm_write(void *opaque, hwaddr addr, 266 uint64_t val, unsigned size) 267 { 268 if (addr != PM_CTRL) { 269 return; 270 } 271 272 switch (val) { 273 case 0x00: 274 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 275 return; 276 case 0xff: 277 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 278 return; 279 default: 280 return; 281 } 282 } 283 284 static const MemoryRegionOps loongarch_virt_pm_ops = { 285 .read = loongarch_virt_pm_read, 286 .write = loongarch_virt_pm_write, 287 .endianness = DEVICE_NATIVE_ENDIAN, 288 .valid = { 289 .min_access_size = 1, 290 .max_access_size = 1 291 } 292 }; 293 294 static struct _loaderparams { 295 uint64_t ram_size; 296 const char *kernel_filename; 297 const char *kernel_cmdline; 298 const char *initrd_filename; 299 } loaderparams; 300 301 static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr) 302 { 303 return addr & 0x1fffffffll; 304 } 305 306 static int64_t load_kernel_info(void) 307 { 308 uint64_t kernel_entry, kernel_low, kernel_high; 309 ssize_t kernel_size; 310 311 kernel_size = load_elf(loaderparams.kernel_filename, NULL, 312 cpu_loongarch_virt_to_phys, NULL, 313 &kernel_entry, &kernel_low, 314 &kernel_high, NULL, 0, 315 EM_LOONGARCH, 1, 0); 316 317 if (kernel_size < 0) { 318 error_report("could not load kernel '%s': %s", 319 loaderparams.kernel_filename, 320 load_elf_strerror(kernel_size)); 321 exit(1); 322 } 323 return kernel_entry; 324 } 325 326 static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams) 327 { 328 DeviceState *dev; 329 MachineState *ms = MACHINE(lams); 330 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 331 332 if (ms->ram_slots) { 333 event |= ACPI_GED_MEM_HOTPLUG_EVT; 334 } 335 dev = qdev_new(TYPE_ACPI_GED); 336 qdev_prop_set_uint32(dev, "ged-event", event); 337 338 /* ged event */ 339 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 340 /* memory hotplug */ 341 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 342 /* ged regs used for reset and power down */ 343 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 344 345 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 346 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - PCH_PIC_IRQ_OFFSET)); 347 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 348 return dev; 349 } 350 351 static DeviceState *create_platform_bus(DeviceState *pch_pic) 352 { 353 DeviceState *dev; 354 SysBusDevice *sysbus; 355 int i, irq; 356 MemoryRegion *sysmem = get_system_memory(); 357 358 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 359 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 360 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 361 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 362 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 363 364 sysbus = SYS_BUS_DEVICE(dev); 365 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 366 irq = VIRT_PLATFORM_BUS_IRQ - PCH_PIC_IRQ_OFFSET + i; 367 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 368 } 369 370 memory_region_add_subregion(sysmem, 371 VIRT_PLATFORM_BUS_BASEADDRESS, 372 sysbus_mmio_get_region(sysbus, 0)); 373 return dev; 374 } 375 376 static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams) 377 { 378 DeviceState *gpex_dev; 379 SysBusDevice *d; 380 PCIBus *pci_bus; 381 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 382 MemoryRegion *mmio_alias, *mmio_reg, *pm_mem; 383 int i; 384 385 gpex_dev = qdev_new(TYPE_GPEX_HOST); 386 d = SYS_BUS_DEVICE(gpex_dev); 387 sysbus_realize_and_unref(d, &error_fatal); 388 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 389 lams->pci_bus = pci_bus; 390 391 /* Map only part size_ecam bytes of ECAM space */ 392 ecam_alias = g_new0(MemoryRegion, 1); 393 ecam_reg = sysbus_mmio_get_region(d, 0); 394 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 395 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 396 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 397 ecam_alias); 398 399 /* Map PCI mem space */ 400 mmio_alias = g_new0(MemoryRegion, 1); 401 mmio_reg = sysbus_mmio_get_region(d, 1); 402 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 403 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 404 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 405 mmio_alias); 406 407 /* Map PCI IO port space. */ 408 pio_alias = g_new0(MemoryRegion, 1); 409 pio_reg = sysbus_mmio_get_region(d, 2); 410 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 411 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 412 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 413 pio_alias); 414 415 for (i = 0; i < GPEX_NUM_IRQS; i++) { 416 sysbus_connect_irq(d, i, 417 qdev_get_gpio_in(pch_pic, 16 + i)); 418 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 419 } 420 421 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 422 qdev_get_gpio_in(pch_pic, 423 VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET), 424 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 425 426 /* Network init */ 427 for (i = 0; i < nb_nics; i++) { 428 NICInfo *nd = &nd_table[i]; 429 430 if (!nd->model) { 431 nd->model = g_strdup("virtio"); 432 } 433 434 pci_nic_init_nofail(nd, pci_bus, nd->model, NULL); 435 } 436 437 /* 438 * There are some invalid guest memory access. 439 * Create some unimplemented devices to emulate this. 440 */ 441 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 442 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 443 qdev_get_gpio_in(pch_pic, 444 VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET)); 445 446 pm_mem = g_new(MemoryRegion, 1); 447 memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops, 448 NULL, "loongarch_virt_pm", PM_SIZE); 449 memory_region_add_subregion(get_system_memory(), PM_BASE, pm_mem); 450 /* acpi ged */ 451 lams->acpi_ged = create_acpi_ged(pch_pic, lams); 452 /* platform bus */ 453 lams->platform_bus_dev = create_platform_bus(pch_pic); 454 } 455 456 static void loongarch_irq_init(LoongArchMachineState *lams) 457 { 458 MachineState *ms = MACHINE(lams); 459 DeviceState *pch_pic, *pch_msi, *cpudev; 460 DeviceState *ipi, *extioi; 461 SysBusDevice *d; 462 LoongArchCPU *lacpu; 463 CPULoongArchState *env; 464 CPUState *cpu_state; 465 int cpu, pin, i; 466 467 ipi = qdev_new(TYPE_LOONGARCH_IPI); 468 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 469 470 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 471 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 472 473 /* 474 * The connection of interrupts: 475 * +-----+ +---------+ +-------+ 476 * | IPI |--> | CPUINTC | <-- | Timer | 477 * +-----+ +---------+ +-------+ 478 * ^ 479 * | 480 * +---------+ 481 * | EIOINTC | 482 * +---------+ 483 * ^ ^ 484 * | | 485 * +---------+ +---------+ 486 * | PCH-PIC | | PCH-MSI | 487 * +---------+ +---------+ 488 * ^ ^ ^ 489 * | | | 490 * +--------+ +---------+ +---------+ 491 * | UARTs | | Devices | | Devices | 492 * +--------+ +---------+ +---------+ 493 */ 494 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 495 cpu_state = qemu_get_cpu(cpu); 496 cpudev = DEVICE(cpu_state); 497 lacpu = LOONGARCH_CPU(cpu_state); 498 env = &(lacpu->env); 499 500 /* connect ipi irq to cpu irq */ 501 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); 502 /* IPI iocsr memory region */ 503 memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX, 504 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 505 cpu * 2)); 506 memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR, 507 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 508 cpu * 2 + 1)); 509 /* extioi iocsr memory region */ 510 memory_region_add_subregion(&env->system_iocsr, APIC_BASE, 511 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 512 cpu)); 513 } 514 515 /* 516 * connect ext irq to the cpu irq 517 * cpu_pin[9:2] <= intc_pin[7:0] 518 */ 519 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 520 cpudev = DEVICE(qemu_get_cpu(cpu)); 521 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 522 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 523 qdev_get_gpio_in(cpudev, pin + 2)); 524 } 525 } 526 527 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 528 d = SYS_BUS_DEVICE(pch_pic); 529 sysbus_realize_and_unref(d, &error_fatal); 530 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 531 sysbus_mmio_get_region(d, 0)); 532 memory_region_add_subregion(get_system_memory(), 533 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 534 sysbus_mmio_get_region(d, 1)); 535 memory_region_add_subregion(get_system_memory(), 536 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 537 sysbus_mmio_get_region(d, 2)); 538 539 /* Connect 64 pch_pic irqs to extioi */ 540 for (int i = 0; i < PCH_PIC_IRQ_NUM; i++) { 541 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 542 } 543 544 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 545 qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START); 546 d = SYS_BUS_DEVICE(pch_msi); 547 sysbus_realize_and_unref(d, &error_fatal); 548 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 549 for (i = 0; i < PCH_MSI_IRQ_NUM; i++) { 550 /* Connect 192 pch_msi irqs to extioi */ 551 qdev_connect_gpio_out(DEVICE(d), i, 552 qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START)); 553 } 554 555 loongarch_devices_init(pch_pic, lams); 556 } 557 558 static void loongarch_firmware_init(LoongArchMachineState *lams) 559 { 560 char *filename = MACHINE(lams)->firmware; 561 char *bios_name = NULL; 562 int bios_size; 563 564 lams->bios_loaded = false; 565 if (filename) { 566 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 567 if (!bios_name) { 568 error_report("Could not find ROM image '%s'", filename); 569 exit(1); 570 } 571 572 bios_size = load_image_targphys(bios_name, VIRT_BIOS_BASE, VIRT_BIOS_SIZE); 573 if (bios_size < 0) { 574 error_report("Could not load ROM image '%s'", bios_name); 575 exit(1); 576 } 577 578 g_free(bios_name); 579 580 memory_region_init_ram(&lams->bios, NULL, "loongarch.bios", 581 VIRT_BIOS_SIZE, &error_fatal); 582 memory_region_set_readonly(&lams->bios, true); 583 memory_region_add_subregion(get_system_memory(), VIRT_BIOS_BASE, &lams->bios); 584 lams->bios_loaded = true; 585 } 586 587 } 588 589 static void reset_load_elf(void *opaque) 590 { 591 LoongArchCPU *cpu = opaque; 592 CPULoongArchState *env = &cpu->env; 593 594 cpu_reset(CPU(cpu)); 595 if (env->load_elf) { 596 cpu_set_pc(CPU(cpu), env->elf_address); 597 } 598 } 599 600 static void fw_cfg_add_kernel_info(FWCfgState *fw_cfg) 601 { 602 /* 603 * Expose the kernel, the command line, and the initrd in fw_cfg. 604 * We don't process them here at all, it's all left to the 605 * firmware. 606 */ 607 load_image_to_fw_cfg(fw_cfg, 608 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 609 loaderparams.kernel_filename, 610 false); 611 612 if (loaderparams.initrd_filename) { 613 load_image_to_fw_cfg(fw_cfg, 614 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 615 loaderparams.initrd_filename, false); 616 } 617 618 if (loaderparams.kernel_cmdline) { 619 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 620 strlen(loaderparams.kernel_cmdline) + 1); 621 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 622 loaderparams.kernel_cmdline); 623 } 624 } 625 626 static void loongarch_firmware_boot(LoongArchMachineState *lams) 627 { 628 fw_cfg_add_kernel_info(lams->fw_cfg); 629 } 630 631 static void loongarch_direct_kernel_boot(LoongArchMachineState *lams) 632 { 633 MachineState *machine = MACHINE(lams); 634 int64_t kernel_addr = 0; 635 LoongArchCPU *lacpu; 636 int i; 637 638 kernel_addr = load_kernel_info(); 639 if (!machine->firmware) { 640 for (i = 0; i < machine->smp.cpus; i++) { 641 lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); 642 lacpu->env.load_elf = true; 643 lacpu->env.elf_address = kernel_addr; 644 } 645 } 646 } 647 648 static void loongarch_init(MachineState *machine) 649 { 650 LoongArchCPU *lacpu; 651 const char *cpu_model = machine->cpu_type; 652 ram_addr_t offset = 0; 653 ram_addr_t ram_size = machine->ram_size; 654 uint64_t highram_size = 0; 655 MemoryRegion *address_space_mem = get_system_memory(); 656 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 657 int i; 658 hwaddr fdt_base; 659 660 if (!cpu_model) { 661 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 662 } 663 664 if (!strstr(cpu_model, "la464")) { 665 error_report("LoongArch/TCG needs cpu type la464"); 666 exit(1); 667 } 668 669 if (ram_size < 1 * GiB) { 670 error_report("ram_size must be greater than 1G."); 671 exit(1); 672 } 673 create_fdt(lams); 674 /* Init CPUs */ 675 for (i = 0; i < machine->smp.cpus; i++) { 676 cpu_create(machine->cpu_type); 677 } 678 fdt_add_cpu_nodes(lams); 679 /* Add memory region */ 680 memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram", 681 machine->ram, 0, 256 * MiB); 682 memory_region_add_subregion(address_space_mem, offset, &lams->lowmem); 683 offset += 256 * MiB; 684 memmap_add_entry(0, 256 * MiB, 1); 685 highram_size = ram_size - 256 * MiB; 686 memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem", 687 machine->ram, offset, highram_size); 688 memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem); 689 memmap_add_entry(0x90000000, highram_size, 1); 690 691 /* initialize device memory address space */ 692 if (machine->ram_size < machine->maxram_size) { 693 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 694 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 695 696 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 697 error_report("unsupported amount of memory slots: %"PRIu64, 698 machine->ram_slots); 699 exit(EXIT_FAILURE); 700 } 701 702 if (QEMU_ALIGN_UP(machine->maxram_size, 703 TARGET_PAGE_SIZE) != machine->maxram_size) { 704 error_report("maximum memory size must by aligned to multiple of " 705 "%d bytes", TARGET_PAGE_SIZE); 706 exit(EXIT_FAILURE); 707 } 708 /* device memory base is the top of high memory address. */ 709 machine->device_memory->base = 0x90000000 + highram_size; 710 machine->device_memory->base = 711 ROUND_UP(machine->device_memory->base, 1 * GiB); 712 713 memory_region_init(&machine->device_memory->mr, OBJECT(lams), 714 "device-memory", device_mem_size); 715 memory_region_add_subregion(address_space_mem, machine->device_memory->base, 716 &machine->device_memory->mr); 717 } 718 719 /* Add isa io region */ 720 memory_region_init_alias(&lams->isa_io, NULL, "isa-io", 721 get_system_io(), 0, VIRT_ISA_IO_SIZE); 722 memory_region_add_subregion(address_space_mem, VIRT_ISA_IO_BASE, 723 &lams->isa_io); 724 /* load the BIOS image. */ 725 loongarch_firmware_init(lams); 726 727 /* fw_cfg init */ 728 lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine); 729 rom_set_fw(lams->fw_cfg); 730 if (lams->fw_cfg != NULL) { 731 fw_cfg_add_file(lams->fw_cfg, "etc/memmap", 732 memmap_table, 733 sizeof(struct memmap_entry) * (memmap_entries)); 734 } 735 fdt_add_fw_cfg_node(lams); 736 loaderparams.ram_size = ram_size; 737 loaderparams.kernel_filename = machine->kernel_filename; 738 loaderparams.kernel_cmdline = machine->kernel_cmdline; 739 loaderparams.initrd_filename = machine->initrd_filename; 740 /* load the kernel. */ 741 if (loaderparams.kernel_filename) { 742 if (lams->bios_loaded) { 743 loongarch_firmware_boot(lams); 744 } else { 745 loongarch_direct_kernel_boot(lams); 746 } 747 } 748 /* register reset function */ 749 for (i = 0; i < machine->smp.cpus; i++) { 750 lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); 751 qemu_register_reset(reset_load_elf, lacpu); 752 } 753 /* Initialize the IO interrupt subsystem */ 754 loongarch_irq_init(lams); 755 fdt_add_irqchip_node(lams); 756 platform_bus_add_all_fdt_nodes(machine->fdt, "/intc", 757 VIRT_PLATFORM_BUS_BASEADDRESS, 758 VIRT_PLATFORM_BUS_SIZE, 759 VIRT_PLATFORM_BUS_IRQ); 760 lams->machine_done.notify = virt_machine_done; 761 qemu_add_machine_init_done_notifier(&lams->machine_done); 762 fdt_add_pcie_node(lams); 763 /* 764 * Since lowmem region starts from 0, FDT base address is located 765 * at 2 MiB to avoid NULL pointer access. 766 * 767 * Put the FDT into the memory map as a ROM image: this will ensure 768 * the FDT is copied again upon reset, even if addr points into RAM. 769 */ 770 fdt_base = 2 * MiB; 771 qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size); 772 rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base); 773 } 774 775 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) 776 { 777 if (lams->acpi == ON_OFF_AUTO_OFF) { 778 return false; 779 } 780 return true; 781 } 782 783 static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, 784 void *opaque, Error **errp) 785 { 786 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 787 OnOffAuto acpi = lams->acpi; 788 789 visit_type_OnOffAuto(v, name, &acpi, errp); 790 } 791 792 static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, 793 void *opaque, Error **errp) 794 { 795 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 796 797 visit_type_OnOffAuto(v, name, &lams->acpi, errp); 798 } 799 800 static void loongarch_machine_initfn(Object *obj) 801 { 802 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 803 804 lams->acpi = ON_OFF_AUTO_AUTO; 805 lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 806 lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 807 } 808 809 static bool memhp_type_supported(DeviceState *dev) 810 { 811 /* we only support pc dimm now */ 812 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 813 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 814 } 815 816 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 817 Error **errp) 818 { 819 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 820 } 821 822 static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev, 823 DeviceState *dev, Error **errp) 824 { 825 if (memhp_type_supported(dev)) { 826 virt_mem_pre_plug(hotplug_dev, dev, errp); 827 } 828 } 829 830 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 831 DeviceState *dev, Error **errp) 832 { 833 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 834 835 /* the acpi ged is always exist */ 836 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lams->acpi_ged), dev, 837 errp); 838 } 839 840 static void virt_machine_device_unplug_request(HotplugHandler *hotplug_dev, 841 DeviceState *dev, Error **errp) 842 { 843 if (memhp_type_supported(dev)) { 844 virt_mem_unplug_request(hotplug_dev, dev, errp); 845 } 846 } 847 848 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 849 DeviceState *dev, Error **errp) 850 { 851 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 852 853 hotplug_handler_unplug(HOTPLUG_HANDLER(lams->acpi_ged), dev, errp); 854 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lams)); 855 qdev_unrealize(dev); 856 } 857 858 static void virt_machine_device_unplug(HotplugHandler *hotplug_dev, 859 DeviceState *dev, Error **errp) 860 { 861 if (memhp_type_supported(dev)) { 862 virt_mem_unplug(hotplug_dev, dev, errp); 863 } 864 } 865 866 static void virt_mem_plug(HotplugHandler *hotplug_dev, 867 DeviceState *dev, Error **errp) 868 { 869 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 870 871 pc_dimm_plug(PC_DIMM(dev), MACHINE(lams)); 872 hotplug_handler_plug(HOTPLUG_HANDLER(lams->acpi_ged), 873 dev, &error_abort); 874 } 875 876 static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev, 877 DeviceState *dev, Error **errp) 878 { 879 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 880 MachineClass *mc = MACHINE_GET_CLASS(lams); 881 882 if (device_is_dynamic_sysbus(mc, dev)) { 883 if (lams->platform_bus_dev) { 884 platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev), 885 SYS_BUS_DEVICE(dev)); 886 } 887 } else if (memhp_type_supported(dev)) { 888 virt_mem_plug(hotplug_dev, dev, errp); 889 } 890 } 891 892 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 893 DeviceState *dev) 894 { 895 MachineClass *mc = MACHINE_GET_CLASS(machine); 896 897 if (device_is_dynamic_sysbus(mc, dev) || 898 memhp_type_supported(dev)) { 899 return HOTPLUG_HANDLER(machine); 900 } 901 return NULL; 902 } 903 904 static void loongarch_class_init(ObjectClass *oc, void *data) 905 { 906 MachineClass *mc = MACHINE_CLASS(oc); 907 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 908 909 mc->desc = "Loongson-3A5000 LS7A1000 machine"; 910 mc->init = loongarch_init; 911 mc->default_ram_size = 1 * GiB; 912 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 913 mc->default_ram_id = "loongarch.ram"; 914 mc->max_cpus = LOONGARCH_MAX_VCPUS; 915 mc->is_default = 1; 916 mc->default_kernel_irqchip_split = false; 917 mc->block_default_type = IF_VIRTIO; 918 mc->default_boot_order = "c"; 919 mc->no_cdrom = 1; 920 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 921 hc->plug = loongarch_machine_device_plug_cb; 922 hc->pre_plug = virt_machine_device_pre_plug; 923 hc->unplug_request = virt_machine_device_unplug_request; 924 hc->unplug = virt_machine_device_unplug; 925 926 object_class_property_add(oc, "acpi", "OnOffAuto", 927 loongarch_get_acpi, loongarch_set_acpi, 928 NULL, NULL); 929 object_class_property_set_description(oc, "acpi", 930 "Enable ACPI"); 931 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 932 } 933 934 static const TypeInfo loongarch_machine_types[] = { 935 { 936 .name = TYPE_LOONGARCH_MACHINE, 937 .parent = TYPE_MACHINE, 938 .instance_size = sizeof(LoongArchMachineState), 939 .class_init = loongarch_class_init, 940 .instance_init = loongarch_machine_initfn, 941 .interfaces = (InterfaceInfo[]) { 942 { TYPE_HOTPLUG_HANDLER }, 943 { } 944 }, 945 } 946 }; 947 948 DEFINE_TYPES(loongarch_machine_types) 949