1 /* 2 * QEMU PIIX PCI ISA Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/range.h" 27 #include "hw/southbridge/piix.h" 28 #include "hw/irq.h" 29 #include "hw/isa/isa.h" 30 #include "hw/xen/xen.h" 31 #include "sysemu/xen.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/reset.h" 34 #include "sysemu/runstate.h" 35 #include "migration/vmstate.h" 36 37 #define XEN_PIIX_NUM_PIRQS 128ULL 38 39 #define TYPE_PIIX3_PCI_DEVICE "pci-piix3" 40 #define PIIX3_PCI_DEVICE(obj) \ 41 OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE) 42 43 #define TYPE_PIIX3_DEVICE "PIIX3" 44 #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen" 45 46 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) 47 { 48 qemu_set_irq(piix3->pic[pic_irq], 49 !!(piix3->pic_levels & 50 (((1ULL << PIIX_NUM_PIRQS) - 1) << 51 (pic_irq * PIIX_NUM_PIRQS)))); 52 } 53 54 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) 55 { 56 int pic_irq; 57 uint64_t mask; 58 59 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; 60 if (pic_irq >= PIIX_NUM_PIC_IRQS) { 61 return; 62 } 63 64 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); 65 piix3->pic_levels &= ~mask; 66 piix3->pic_levels |= mask * !!level; 67 } 68 69 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) 70 { 71 int pic_irq; 72 73 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; 74 if (pic_irq >= PIIX_NUM_PIC_IRQS) { 75 return; 76 } 77 78 piix3_set_irq_level_internal(piix3, pirq, level); 79 80 piix3_set_irq_pic(piix3, pic_irq); 81 } 82 83 static void piix3_set_irq(void *opaque, int pirq, int level) 84 { 85 PIIX3State *piix3 = opaque; 86 piix3_set_irq_level(piix3, pirq, level); 87 } 88 89 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) 90 { 91 PIIX3State *piix3 = opaque; 92 int irq = piix3->dev.config[PIIX_PIRQCA + pin]; 93 PCIINTxRoute route; 94 95 if (irq < PIIX_NUM_PIC_IRQS) { 96 route.mode = PCI_INTX_ENABLED; 97 route.irq = irq; 98 } else { 99 route.mode = PCI_INTX_DISABLED; 100 route.irq = -1; 101 } 102 return route; 103 } 104 105 /* irq routing is changed. so rebuild bitmap */ 106 static void piix3_update_irq_levels(PIIX3State *piix3) 107 { 108 PCIBus *bus = pci_get_bus(&piix3->dev); 109 int pirq; 110 111 piix3->pic_levels = 0; 112 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { 113 piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq)); 114 } 115 } 116 117 static void piix3_write_config(PCIDevice *dev, 118 uint32_t address, uint32_t val, int len) 119 { 120 pci_default_write_config(dev, address, val, len); 121 if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { 122 PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); 123 int pic_irq; 124 125 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); 126 piix3_update_irq_levels(piix3); 127 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { 128 piix3_set_irq_pic(piix3, pic_irq); 129 } 130 } 131 } 132 133 static void piix3_write_config_xen(PCIDevice *dev, 134 uint32_t address, uint32_t val, int len) 135 { 136 xen_piix_pci_write_config_client(address, val, len); 137 piix3_write_config(dev, address, val, len); 138 } 139 140 static void piix3_reset(void *opaque) 141 { 142 PIIX3State *d = opaque; 143 uint8_t *pci_conf = d->dev.config; 144 145 pci_conf[0x04] = 0x07; /* master, memory and I/O */ 146 pci_conf[0x05] = 0x00; 147 pci_conf[0x06] = 0x00; 148 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */ 149 pci_conf[0x4c] = 0x4d; 150 pci_conf[0x4e] = 0x03; 151 pci_conf[0x4f] = 0x00; 152 pci_conf[0x60] = 0x80; 153 pci_conf[0x61] = 0x80; 154 pci_conf[0x62] = 0x80; 155 pci_conf[0x63] = 0x80; 156 pci_conf[0x69] = 0x02; 157 pci_conf[0x70] = 0x80; 158 pci_conf[0x76] = 0x0c; 159 pci_conf[0x77] = 0x0c; 160 pci_conf[0x78] = 0x02; 161 pci_conf[0x79] = 0x00; 162 pci_conf[0x80] = 0x00; 163 pci_conf[0x82] = 0x00; 164 pci_conf[0xa0] = 0x08; 165 pci_conf[0xa2] = 0x00; 166 pci_conf[0xa3] = 0x00; 167 pci_conf[0xa4] = 0x00; 168 pci_conf[0xa5] = 0x00; 169 pci_conf[0xa6] = 0x00; 170 pci_conf[0xa7] = 0x00; 171 pci_conf[0xa8] = 0x0f; 172 pci_conf[0xaa] = 0x00; 173 pci_conf[0xab] = 0x00; 174 pci_conf[0xac] = 0x00; 175 pci_conf[0xae] = 0x00; 176 177 d->pic_levels = 0; 178 d->rcr = 0; 179 } 180 181 static int piix3_post_load(void *opaque, int version_id) 182 { 183 PIIX3State *piix3 = opaque; 184 int pirq; 185 186 /* 187 * Because the i8259 has not been deserialized yet, qemu_irq_raise 188 * might bring the system to a different state than the saved one; 189 * for example, the interrupt could be masked but the i8259 would 190 * not know that yet and would trigger an interrupt in the CPU. 191 * 192 * Here, we update irq levels without raising the interrupt. 193 * Interrupt state will be deserialized separately through the i8259. 194 */ 195 piix3->pic_levels = 0; 196 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { 197 piix3_set_irq_level_internal(piix3, pirq, 198 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq)); 199 } 200 return 0; 201 } 202 203 static int piix3_pre_save(void *opaque) 204 { 205 int i; 206 PIIX3State *piix3 = opaque; 207 208 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { 209 piix3->pci_irq_levels_vmstate[i] = 210 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i); 211 } 212 213 return 0; 214 } 215 216 static bool piix3_rcr_needed(void *opaque) 217 { 218 PIIX3State *piix3 = opaque; 219 220 return (piix3->rcr != 0); 221 } 222 223 static const VMStateDescription vmstate_piix3_rcr = { 224 .name = "PIIX3/rcr", 225 .version_id = 1, 226 .minimum_version_id = 1, 227 .needed = piix3_rcr_needed, 228 .fields = (VMStateField[]) { 229 VMSTATE_UINT8(rcr, PIIX3State), 230 VMSTATE_END_OF_LIST() 231 } 232 }; 233 234 static const VMStateDescription vmstate_piix3 = { 235 .name = "PIIX3", 236 .version_id = 3, 237 .minimum_version_id = 2, 238 .post_load = piix3_post_load, 239 .pre_save = piix3_pre_save, 240 .fields = (VMStateField[]) { 241 VMSTATE_PCI_DEVICE(dev, PIIX3State), 242 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, 243 PIIX_NUM_PIRQS, 3), 244 VMSTATE_END_OF_LIST() 245 }, 246 .subsections = (const VMStateDescription*[]) { 247 &vmstate_piix3_rcr, 248 NULL 249 } 250 }; 251 252 253 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) 254 { 255 PIIX3State *d = opaque; 256 257 if (val & 4) { 258 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 259 return; 260 } 261 d->rcr = val & 2; /* keep System Reset type only */ 262 } 263 264 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) 265 { 266 PIIX3State *d = opaque; 267 268 return d->rcr; 269 } 270 271 static const MemoryRegionOps rcr_ops = { 272 .read = rcr_read, 273 .write = rcr_write, 274 .endianness = DEVICE_LITTLE_ENDIAN 275 }; 276 277 static void piix3_realize(PCIDevice *dev, Error **errp) 278 { 279 PIIX3State *d = PIIX3_PCI_DEVICE(dev); 280 281 if (!isa_bus_new(DEVICE(d), get_system_memory(), 282 pci_address_space_io(dev), errp)) { 283 return; 284 } 285 286 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, 287 "piix3-reset-control", 1); 288 memory_region_add_subregion_overlap(pci_address_space_io(dev), 289 PIIX_RCR_IOPORT, &d->rcr_mem, 1); 290 291 qemu_register_reset(piix3_reset, d); 292 } 293 294 static void pci_piix3_class_init(ObjectClass *klass, void *data) 295 { 296 DeviceClass *dc = DEVICE_CLASS(klass); 297 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 298 299 dc->desc = "ISA bridge"; 300 dc->vmsd = &vmstate_piix3; 301 dc->hotpluggable = false; 302 k->realize = piix3_realize; 303 k->vendor_id = PCI_VENDOR_ID_INTEL; 304 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ 305 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; 306 k->class_id = PCI_CLASS_BRIDGE_ISA; 307 /* 308 * Reason: part of PIIX3 southbridge, needs to be wired up by 309 * pc_piix.c's pc_init1() 310 */ 311 dc->user_creatable = false; 312 } 313 314 static const TypeInfo piix3_pci_type_info = { 315 .name = TYPE_PIIX3_PCI_DEVICE, 316 .parent = TYPE_PCI_DEVICE, 317 .instance_size = sizeof(PIIX3State), 318 .abstract = true, 319 .class_init = pci_piix3_class_init, 320 .interfaces = (InterfaceInfo[]) { 321 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 322 { }, 323 }, 324 }; 325 326 static void piix3_class_init(ObjectClass *klass, void *data) 327 { 328 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 329 330 k->config_write = piix3_write_config; 331 } 332 333 static const TypeInfo piix3_info = { 334 .name = TYPE_PIIX3_DEVICE, 335 .parent = TYPE_PIIX3_PCI_DEVICE, 336 .class_init = piix3_class_init, 337 }; 338 339 static void piix3_xen_class_init(ObjectClass *klass, void *data) 340 { 341 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 342 343 k->config_write = piix3_write_config_xen; 344 }; 345 346 static const TypeInfo piix3_xen_info = { 347 .name = TYPE_PIIX3_XEN_DEVICE, 348 .parent = TYPE_PIIX3_PCI_DEVICE, 349 .class_init = piix3_xen_class_init, 350 }; 351 352 static void piix3_register_types(void) 353 { 354 type_register_static(&piix3_pci_type_info); 355 type_register_static(&piix3_info); 356 type_register_static(&piix3_xen_info); 357 } 358 359 type_init(piix3_register_types) 360 361 /* 362 * Return the global irq number corresponding to a given device irq 363 * pin. We could also use the bus number to have a more precise mapping. 364 */ 365 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) 366 { 367 int slot_addend; 368 slot_addend = (pci_dev->devfn >> 3) - 1; 369 return (pci_intx + slot_addend) & 3; 370 } 371 372 PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus) 373 { 374 PIIX3State *piix3; 375 PCIDevice *pci_dev; 376 377 /* 378 * Xen supports additional interrupt routes from the PCI devices to 379 * the IOAPIC: the four pins of each PCI device on the bus are also 380 * connected to the IOAPIC directly. 381 * These additional routes can be discovered through ACPI. 382 */ 383 if (xen_enabled()) { 384 pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, 385 TYPE_PIIX3_XEN_DEVICE); 386 piix3 = PIIX3_PCI_DEVICE(pci_dev); 387 pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, 388 piix3, XEN_PIIX_NUM_PIRQS); 389 } else { 390 pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, 391 TYPE_PIIX3_DEVICE); 392 piix3 = PIIX3_PCI_DEVICE(pci_dev); 393 pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, 394 piix3, PIIX_NUM_PIRQS); 395 pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); 396 } 397 *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); 398 399 return piix3; 400 } 401